CN107170366B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN107170366B CN107170366B CN201710601241.5A CN201710601241A CN107170366B CN 107170366 B CN107170366 B CN 107170366B CN 201710601241 A CN201710601241 A CN 201710601241A CN 107170366 B CN107170366 B CN 107170366B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses display panel and display device, this display panel includes: the display device comprises a display area and a non-display area, wherein the non-display area comprises an upper frame area and a lower frame area which are arranged along a first direction; the fan-out area is located the lower frame region, the fan-out area comprises the first sub fan-out area, the second sub fan-out area and the third sub fan-out area that arrange along the second direction in proper order, first sub fan-out area and third sub fan-out area include many first fan-out lead wires, the second sub fan-out area includes many second fan-out lead wires, be located first sub fan-out area and third sub fan-out area, each first fan-out lead wire that arranges in proper order along the second direction sets up on first metal level and second metal level in turn, each second fan-out lead wire sets up at the second metal level. The first fan-out leads in the first sub-fan-out region and the third sub-fan-out region are alternately arranged on the first metal layer and the second metal layer, so that the height of the lower frame region along the first direction can be reduced, and the narrow frame design of the display panel is realized.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a display device including the display panel.
Background
The packaging technology of the driving chip of the display panel mainly includes a cog (chip on glass) technology and a cof (chip on flash) technology. At present, a COF technology is mainly used for packaging a driving chip in a display panel, and the driving chip is directly packaged on a flexible circuit board. Since the COF technology can package the driving chip on the flexible circuit board instead of the lower frame region of the non-display region of the display panel, the area of the lower frame region of the non-display region of the display panel packaged by the COF technology is smaller, thereby increasing the area occupied by the display region of the display panel.
In the display panel packaged by the COF technology, the data lines and the like may be electrically connected to the flexible circuit board through the fan-out leads, so that the driving chip on the flexible circuit board may provide corresponding signals to the data lines and the like. Each fan-out lead is located in a fan-out area in a fan shape, which is located in a lower bezel area between the display area and the flexible circuit board. In the display panel, the driver chip needs to provide signals for the signal lines such as a large number of data lines, and therefore, a large number of fan-out leads electrically connected to the flexible circuit board need to be arranged in the fan-out area. Moreover, each fan-out lead in the display panel is usually disposed on the same metal layer, which causes the fan-out area to occupy a large area in the lower frame area. However, in the display panel packaged by the COF technology, the area of the lower bezel region between the display region and the flexible circuit board is small, and thus in order to meet the area requirement of the fan-out region, the distance between the display region and the flexible circuit board needs to be increased, which may make it difficult to realize a narrow bezel design of the display panel.
Disclosure of Invention
In view of the above-mentioned drawbacks in the prior art, embodiments of the present application provide a display panel and a display device including the display panel to solve the technical problems mentioned in the above background.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a display panel, including: the array substrate, the flexible circuit board and the driving chip are arranged on the flexible circuit board; an array substrate, comprising: the display device comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises an upper frame area and a lower frame area which are arranged along a first direction, and a first side frame area and a second side frame area which are arranged along a second direction, and the first direction is vertical to the second direction; the fan-out area is positioned in the lower frame area and consists of a first sub fan-out area, a second sub fan-out area and a third sub fan-out area which are sequentially arranged along a second direction, the first sub fan-out area and the third sub fan-out area comprise a plurality of first fan-out leads, the second sub fan-out area comprises a plurality of second fan-out leads, the first fan-out leads which are positioned in the first sub fan-out area and the third sub fan-out area and sequentially arranged along the second direction are alternately arranged on a first metal layer and a second metal layer, the second fan-out leads are arranged on the second metal layer, and the first metal layer and the second metal layer are made of different metal materials; the flexible circuit board is bound in a lower frame area of the array substrate, and each first fan-out lead and each second fan-out lead are electrically connected with the flexible circuit board.
In a second aspect, an embodiment of the present application further provides a display device, including the display panel described above.
The display panel and the display device provided by the embodiment of the application, the driving chip can be arranged on the flexible circuit board, the flexible circuit board can be bound in a lower frame area of the array substrate, the fan-out area is located in the lower frame area, a first sub fan-out area, a second sub fan-out area and a third sub fan-out area in the fan-out area can be sequentially arranged along the second direction, a plurality of first fan-out leads can be arranged in the first sub fan-out area and the third sub fan-out area, each first fan-out lead can be sequentially arranged along the second direction, each first fan-out lead in the first sub fan-out area and the third sub fan-out area can be alternately arranged on the first metal layer and the second metal layer, so that the distance between the first sub fan-out area and the third sub fan-out area along the first direction can be reduced, and the display panel can realize a narrow frame design.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1A shows a schematic structural diagram of an embodiment of a display panel according to the present application;
FIG. 1B is a schematic diagram showing the connection of first and second fan-out leads of FIG. 1A;
FIG. 2 shows a schematic structural diagram of another embodiment of a display panel according to the present application;
fig. 3 shows a schematic structural diagram of an embodiment of a display device according to the present application.
Detailed Description
The principles and features of the present application are described in further detail below with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1A-1B, fig. 1A is a schematic structural diagram of a display panel according to an embodiment of the present application, and fig. 1B is a schematic connection diagram of a first fan-out lead and a second fan-out lead in fig. 1A. As shown in fig. 1A, the display panel 100 of the present embodiment may include an array substrate 110, a flexible circuit board 120, and a driving chip 130, and the array substrate 110 may include a display area 101 and a non-display area, and the non-display area may include a fan-out area 103.
In this embodiment, the display panel 100 may be a display panel packaged by COF technology. In the display panel 100, the driving chip 130 may be disposed on the flexible circuit board 120, and the flexible circuit board 120 may be bonded on the array substrate 110, as shown in fig. 1A. In the array substrate 110, the non-display area may surround the display area 101, and as shown in fig. 1A, the non-display area may include an upper frame area 1021, a lower frame area 1022, a first side frame area 1023, and a second side frame area 1024, and the upper frame area 1021 and the lower frame area 1022 may be arranged in a first direction D1, and the first side frame area 1023 and the second side frame area 1024 may be arranged in a second direction D2. Here, the first direction D1 and the second direction D2 may be perpendicular to each other, as shown in fig. 1A.
In this embodiment, the array substrate 110 may include a fan-out region 103, and the fan-out region 103 may be located in the lower frame region 1022, as shown in fig. 1A. The fan-out region 103 may include a first sub-fan-out region 1031, a second sub-fan-out region 1032 and a third sub-fan-out region 1033, and the first sub-fan-out region 1031, the second sub-fan-out region 1032 and the third sub-fan-out region 1033 may be sequentially arranged along the second direction D2, as shown in fig. 1A and 1B. The first sub-fan-out region 1031 may include a plurality of first fan-out leads 10311, the third sub-fan-out region 1033 may also include a plurality of first fan-out leads 10311, and the second sub-fan-out region 1032 may include a plurality of second fan-out leads 10321, as shown in fig. 1B. The first fan-out leads 10311 in the first and third sub-fan-out regions 1031 and 1033 may be sequentially arranged along the second direction D2, and the second fan-out leads 10321 in the second sub-fan-out region 1032 may be sequentially arranged along the second direction D2, as shown in fig. 1A. Further, in the first sub-fan-out region 1031, the respective first fan-out leads 10311 arranged in the second direction D2 may be alternately disposed on the first metal layer and the second metal layer, that is, any two adjacent first fan-out leads 10311 may be disposed on different metal layers, as shown in fig. 1B. Likewise, in the third sub-fan-out region 1033, the first fan-out leads 10311 arranged in the second direction D2 may also be alternately disposed on the first metal layer M1 and the second metal layer M2, as shown in fig. 1B, that is, any two adjacent first fan-out leads 10311 may be disposed on different metal layers. Unlike the first and third sub-fanout regions 1031 and 1033, in the second sub-fanout region 1032 described above, the second fan-out leads 10321 arranged in the second direction D2 may each be provided at the second metal layer M2, as shown in fig. 1B. Here, by providing the respective first fan-out leads 10311 in the first and third sub-fan-out regions 1031 and 1033 at the first and second metal layers, respectively, the number of the first fan-out leads 10311 provided in the same metal layer can be reduced. Therefore, compared with a display panel in which the first fan-out leads 10311 are disposed on the same metal layer in the prior art, the display panel passed through by the present embodiment may dispose the first fan-out leads 10311 on two different metal layers, and under the condition that the distance between adjacent first fan-out leads 10311 is not changed, the display panel of the present embodiment may reduce the area occupied by the first sub-fan-out region 1031 and the third sub-fan-out region 1033 where the first sub-fan-out leads 10311 are located. Specifically, the distance between the first sub-fan-out region 1031 and the third sub-fan-out region 1033 along the first direction D1 may be reduced, that is, the distance between the lower bezel region 1022 where the fan-out region 103 is located along the first direction D1 may be reduced, so that the display panel may implement a narrow bezel design.
In this embodiment, the flexible circuit board 120 may be bound to the lower frame region 1022 of the array substrate 110, as shown in fig. 1A, and the first fan-out lead 10311 and the second fan-out lead 10321 located in the fan-out region 103 may be electrically connected to the flexible circuit board 120. Accordingly, the driving chip 130 may provide respective signals to each of the first and second fan-out leads 10311 and 10321 through the flexible circuit board 120.
In some optional implementations of the present embodiment, each of the first fan-out leads 10311 may include a diagonal portion 1 and a straight portion 2, as shown in fig. 1B, the diagonal portion 1 of the first fan-out lead 10311 may intersect the first direction D1, and the straight portion 2 of the first fan-out lead 10311 may be parallel to the first direction D1. In each first fan-out lead 10311 located in the first metal layer, a distance between diagonal line portions 1 of adjacent first fan-out leads 10311 may be a, as shown in fig. 1B. In each first fan-out lead 10311 located in the second metal layer, the distance between the diagonal portions 1 of the adjacent first fan-out leads 10311 may also be a. It should be noted that, in the array substrate 110, the line width of the first fan-out lead 10311 may be B, as shown in fig. 1B, the distance a and the line width B may satisfy that a/B is greater than or equal to 0.8 and less than or equal to 1.2, and as can be seen, the line width of the first fan-out lead 10311 in this embodiment may not be greatly different from the distance between two adjacent oblique line portions 1 in the same metal layer. In the prior art, all the fan-out leads in the display panel are usually disposed on the same metal layer, and the distance between the adjacent fan-out leads does not greatly differ from the line width of the fan-out leads, but the adjacent first fan-out leads 10311 in this embodiment may be disposed on different metal layers, and therefore, in the first sub-fanout region 1031 and the third sub-fanout region 1033, the number of the first fan-out leads 10311 located on the same metal layer is reduced by half and the distance of the oblique line portions 1 of the adjacent first fan-out leads 10311 is unchanged, which may reduce the distance occupied by the oblique line portions 1 of the first fan-out leads 10311 located on the same metal layer along the first direction D1, thereby may reduce the distance of the lower bezel region 1022 along the first direction D1, and may enable the display panel 100 to implement a narrow bezel design. In this embodiment, the second fan-out leads 10321 are all disposed on the second metal layer M2, and the second fan-out leads 10321 include only straight portions parallel to the first direction D1. Since the second fanout line 10321 is parallel to the first direction D1 itself, its distance in the first direction D1 has reached the narrowest.
The display panel provided by the above embodiment of the present application, wherein the driving chip 130 may be disposed on the flexible circuit board 120, the flexible circuit board 120 may be bound to the lower frame region 1022 of the array substrate 120, the fan-out region 103 is located in the lower frame region 1022, the first sub-fan-out region 1031, the second sub-fan-out region 1032 and the third sub-fan-out region 1033 in the fan-out region 103 may be sequentially arranged along the second direction D2, the first sub-fan-out region 1031 and the third sub-fan-out region 1033 may be provided with a plurality of first fan-out leads 10311, each of the first fan-out leads 10311 is sequentially arranged along the second direction D2 and alternately arranged on the first metal layer and the second metal layer, so that the distance of the first and third sub fan-out areas 1031 and 1033 in the first direction D1 can be reduced, that is, the distance of the lower border region 1022 in the first direction D1 can be reduced, and the display panel can implement a narrow border design.
Please refer to fig. 2, which shows a schematic structural diagram of another embodiment of a display panel according to the present application. As shown, the display panel 200 in this embodiment may include an array substrate 210, a flexible circuit board 220, and a driving chip 230, and the array substrate 210 may include a display area 201 and a non-display area, and the non-display area may include a fan-out region 203, a first shift register 204, a first signal line 205, and a second shift register 206.
In this embodiment, the driving chip 230 may be disposed on the flexible circuit board 220, and the flexible circuit board 220 may be bonded to the array substrate 210. The non-display region of the array substrate 210 may surround the display region 201, and the non-display region may include an upper bezel region 2021 and a lower bezel region 2022 sequentially arranged along a first direction D1, and a first side bezel region 2023 and a second side bezel region 2024 sequentially arranged along a second direction D2, as shown in fig. 2. The lower bezel region 2022 may be provided with a fan-out region 203, and the fan-out region 203 may include a first sub fan-out region 2031, a second sub fan-out region 2032, and a third sub fan-out region 2033 arranged in sequence along the second direction D2, as shown in fig. 2, the first sub fan-out region 2031 and the third sub fan-out region 2033 may include a plurality of first fan-out leads 20311, and the second sub fan-out region 2032 may include a plurality of second fan-out leads 20321. As in the above-described embodiment, the first fan-out leads 20311 sequentially arranged in the second direction D2 in the first and third sub-fan-out regions 2031 and 2033 in this embodiment may be alternately disposed on the first and second metal layers. The first metal layer and the second metal layer may be made of different metal materials. The flexible circuit board 120 may be bonded to the lower frame region 2022, as shown in fig. 2, and each of the first fan-out lead 20311 and the second fan-out lead 20321 may be electrically connected to the flexible circuit board 220, so that the driving chip 230 may output corresponding signals to the first fan-out lead 20311 and the second fan-out lead 20321.
In this embodiment, the display panel 200 may include a plurality of signal lines, and each signal line may be electrically connected to the first fan-out lead 20311 or the second fan-out lead 20321, so that the driving chip 230 and the like may provide signals for each signal line. The first side frame region 2023 and the second side frame region 2024 may be disposed with a plurality of first signal lines 205, as shown in fig. 2. At least a portion of the first fan-out leads 20311 in the first sub-fan-out region 2031 may be electrically connected to the first signal lines 205 located in the first side frame region 2023, and at least a portion of the first fan-out leads 20311 in the third sub-fan-out region 2033 may be electrically connected to the first signal lines 205 located in the second side frame region 2024. The driving chip 230 may provide signals to the corresponding first signal lines 205 through the first fan-out leads 20311.
It is understood that each of the first signal lines 205 located in the first side frame region 2023 may include a dc signal line and a pulse signal line. The dc signal line may receive a dc signal output by the driving chip 230, and the pulse signal line may receive a pulse signal output by the driving chip 230. In each of the first signal lines 205, the direct current signal line may be electrically connected to the first fan-out lead 20311 disposed on the first metal layer, and the pulse signal line may be electrically connected to the first fan-out lead 20311 disposed on the second metal layer. The first metal layer and the second metal layer are formed of different metal materials, and the resistivity of the first metal layer is different from that of the second metal layer. The pulse signal line may be electrically connected to the first fan-out lead 20311 located in the lower resistivity one of the first and second metal layers, and the direct current signal line may be electrically connected to the first fan-out lead 20311 located in the higher resistivity one of the first and second metal layers. The resistance of the first fan-out lead 20311 has less influence on the dc signal, and therefore, electrically connecting the first fan-out lead 20311 having a lower resistivity to the dc signal line can avoid the occurrence of signal delay as much as possible.
In this embodiment, the display panel 200 may further include a shift register for providing a shift signal. Specifically, the first side frame region 2023 may be provided with a first shift register 204, and the second side frame region 2024 may be provided with a second shift register 206, as shown in fig. 2. The first shift register 204 may be electrically connected to the first fan-out lead 20311 of the first sub-fan-out region 2031 through the first signal line 205 of the first side frame region 2023, and the second shift register 206 may be electrically connected to the first fan-out lead 20311 of the third sub-fan-out region 2033 through the first signal line 205 of the second side frame region 2024. It is understood that the first side frame region 2023 may have a plurality of first signal lines 205 for providing the first shift register 204 with a dc signal and a pulse signal. For example, the first side frame region 2023 may be provided with a trigger pulse signal line for supplying a start pulse signal (CKH), a shift pulse signal line for supplying a shift pulse Signal (STV), an enable signal line for supplying an enable signal (DE), and the like, wherein signals output by the trigger pulse signal line and the shift pulse signal line may be pulse signals, and signals output by the enable signal line may be dc signals. Therefore, a signal line for outputting a pulse signal, such as a trigger pulse signal line and a shift pulse signal line, connected to the first shift register 204 may be electrically connected to the first fan-out lead 20311 provided in the first sub-fan-out region 2031 and located in the metal layer having a relatively low resistivity, and a signal line for outputting a dc signal, such as an enable signal line connected to the first shift register 204, may be electrically connected to the first fan-out lead 20311 provided in the first sub-fan-out region 2031 and located in the metal layer having a relatively high resistivity. Similarly, the second bezel region 2024 may also be provided with a trigger pulse signal line and a shift pulse signal line for supplying a pulse signal to the second shift register 206, an enable signal line for supplying a dc signal, and the like, where the trigger pulse signal line and the shift pulse signal line for outputting the pulse signal may be electrically connected to the first fan-out lead 20311 provided in the first sub-fan-out region 2031 and located in the metal layer having the smaller resistivity, and the enable signal line for outputting the dc signal may be electrically connected to the first fan-out lead 20311 provided in the first sub-fan-out region 2031 and located in the metal layer having the larger resistivity.
In some optional implementations of the present embodiment, the display panel 200 may further include a plurality of data lines 207, as shown in fig. 2, each data line 207 extends along the first direction D1, and each data line 207 may be located in the display area 201. Each second fan-out lead 20321 in the second sub-fan-out region 2032 may be electrically connected to a data line 207, so that the data line 207 may be electrically connected to the flexible circuit board 220 through the second fan-out lead 20321, and the driving chip 230 may provide data signals to each data line 207.
In general, in order to reduce the occupation of the pins of the driving chip 230, the display panel 200 may further be provided with a multiplexer 208, and the multiplexer 208 may be formed of a thin film transistor or the like. The first signal line 205 and the data line 207 and the like in the display panel 200 may be electrically connected to the first fan-out lead 20311 or the second fan-out lead 20321 located in the fan-out region 203 through the multiplexer 208.
In some optional implementations of this embodiment, the data line 207 may be located in the second metal layer. The display panel 200 may further include a plurality of scan lines for outputting scan signals to the pixel electrodes, and each of the scan lines may be located in the first metal layer, and the resistivity of the first metal layer is generally greater than that of the second metal layer. In this case, the dc signal line of each first signal line 205 may be electrically connected to the first fan-out lead 20311 located at the first metal layer, and the pulse signal line of each first signal line 205 may be electrically connected to the first fan-out lead 20311 located at the second metal layer. In some optional implementations of this embodiment, when the first metal layer in the array substrate 210 is a metal layer where the scan lines are located, and the second metal layer is a metal layer where the data lines 207 are located, the resistivity of the first metal layer is generally greater than that of the second metal layer, which may cause the resistance of the first fan-out lead 20311 located in the first metal layer to be greater than that of the first fan-out lead 20311 located in the second metal layer. In order to reduce the resistance of the first fan-out lead 20311 located on the first metal layer, the array substrate 210 may further include at least one connection trace, and each connection trace may be located on a second metal layer with a smaller resistivity. Each first fan-out lead 20311 at the first metal layer can be electrically connected to the flexible circuit board 220 by a connection trace. Compared to electrically connecting the first fan-out lead 20311 on the first metal layer directly to the flexible circuit board 220 at the first metal layer, electrically connecting the first fan-out lead 20311 on the first metal layer to the flexible circuit board 220 through a connection trace can reduce the resistance value of the flexible circuit board 220 to a signal line electrically connected to the first fan-out lead 20311, so that signal delay can be further avoided. It is understood that an insulating layer may be disposed between the first metal layer and the second metal layer, and a plurality of through holes may be disposed on the insulating layer, and the first fan-out lead 20311 on the first metal layer may be electrically connected to the corresponding connection trace through the through holes, so that the first fan-out lead 20311 on the first metal layer may be electrically connected to the flexible circuit board 220 through the corresponding connection trace, and the driving chip 230 may output a corresponding signal to a signal line electrically connected to the first fan-out lead 20311.
In the display panel 200 provided in the above-described embodiment of the present application, the distance of the fan-out region 203 along the first direction D1 may be reduced by alternately disposing the first fan-out lead 20311 on the first metal layer and the second metal layer, so that the display panel 200 may implement a narrow bezel design, and by connecting the first signal line 205 outputting the pulse signal to the first fan-out lead 20311 on the metal layer with the lower resistivity among the first metal layer and the second metal layer and connecting the first signal line 205 outputting the dc signal to the first fan-out lead 20311 on the metal layer with the higher resistivity, it may be avoided that the pulse signal line is electrically connected to the first fan-out lead 20311 on the metal layer with the higher resistivity to cause signal delay.
The display panel 200 may further include some well-known structures, such as a common electrode, a driving circuit, and the like. Such well-known structures have not been mentioned in the foregoing embodiments in order to not unnecessarily obscure the embodiments of the present disclosure.
In addition, the present application also provides a display device 300, which may include the display panel in the above embodiments. Here, as shown in fig. 3, fig. 3 is a schematic diagram illustrating a display device provided in an embodiment of the present application. The display device 300 may be a mobile phone as shown in fig. 3, and the structure and function of the display panel in the display device 300 are the same as those in the above embodiments, and are not described again here. It can be understood by those skilled in the art that the display device may also be a computer, a television, a wearable smart device, etc., which are not listed here.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (6)
1. A display panel, comprising: the array substrate, the flexible circuit board and the driving chip are arranged on the flexible circuit board;
the array substrate includes:
the display area comprises a plurality of data lines extending along a first direction, the non-display area comprises an upper frame area and a lower frame area which are arranged along the first direction, and a first side frame area and a second side frame area which are arranged along a second direction, wherein the first direction is vertical to the second direction;
a fan-out area located in the lower frame area, the fan-out area being composed of a first sub fan-out area, a second sub fan-out area and a third sub fan-out area sequentially arranged along the second direction, the first sub fan-out area and the third sub fan-out area including a plurality of first fan-out leads sequentially arranged along the second direction, the second sub fan-out area including a plurality of second fan-out leads sequentially arranged along the second direction, wherein the first fan-out leads are alternately arranged on the first metal layer and the second metal layer in the first sub fan-out area and the third sub fan-out area, the first sub fan-out leads and the second sub fan-out leads are mutually independent and insulated, the first sub fan-out leads are arranged on the first metal layer, the second sub fan-out lead is arranged on a second metal layer; in a direction perpendicular to the array substrate, the projection of the first sub fan-out lead on the array substrate is positioned between the projections of two adjacent second sub fan-out leads on the array substrate; the second fan-out lead only comprises a third sub-fan-out lead, the third sub-fan-out lead extends along the first direction and is arranged on the second metal layer, and the first metal layer and the second metal layer are made of different metal materials;
the flexible circuit board is bound in a lower frame area of the array substrate, and each first fan-out lead and each second fan-out lead are electrically connected with the flexible circuit board;
the first side frame area and the second side frame area are both provided with a plurality of first signal wires;
the plurality of first signal lines comprise direct current signal lines and pulse signal lines;
at least part of the direct current signal lines are electrically connected with the first sub-fan-out lead, at least part of the pulse signal lines are electrically connected with the second sub-fan-out lead, and at least part of the data lines are electrically connected with the third sub-fan-out lead;
the first side frame area is provided with a first shift register, and the second side frame area is provided with a second shift register;
the first shift register is electrically connected with the first fan-out lead wire positioned in the first sub fan-out area through a first signal wire positioned in the first side frame area, and the second shift register is electrically connected with the first fan-out lead wire positioned in the third sub fan-out area through a first signal wire positioned in the second side frame area.
2. The display panel of claim 1, wherein the first metal layer is a metal layer where the scan lines are located, and the second metal layer is a metal layer where the data lines are located.
3. The display panel according to claim 2, further comprising:
at least one connecting wire located on the second metal layer, each connecting wire corresponding to each first fan-out lead located on the first metal layer;
an insulating layer is arranged between the first metal layer and the second metal layer, and a plurality of through holes are formed in the insulating layer;
the first fan-out lead positioned on the first metal layer is electrically connected with the corresponding connecting wire through the through hole, so that each first fan-out lead positioned on the first metal layer is electrically connected with the flexible circuit board through the corresponding connecting wire.
4. The display panel of claim 1, wherein each of the first fan-out leads includes a straight portion and a diagonal portion, wherein the straight portion is parallel to the first direction and the diagonal portion intersects the first direction;
the distance between the oblique line parts of two adjacent first fan-out leads positioned on the first metal layer is a, and the distance between the oblique line parts of two adjacent first fan-out leads positioned on the second metal layer is a;
the line width of the first fan-out lead is b, wherein a and b satisfy that a/b is more than or equal to 0.8 and less than or equal to 1.2.
5. The display panel according to any one of claims 1 to 4, wherein the resistivity of the first metal layer is different from the resistivity of the second metal layer.
6. A display device characterized by comprising a display panel according to any one of claims 1 to 5.
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| CN201710601241.5A CN107170366B (en) | 2017-07-21 | 2017-07-21 | Display panel and display device |
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| CN201710601241.5A CN107170366B (en) | 2017-07-21 | 2017-07-21 | Display panel and display device |
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| CN107170366B true CN107170366B (en) | 2020-04-17 |
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