CN114677987A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114677987A CN114677987A CN202210447564.4A CN202210447564A CN114677987A CN 114677987 A CN114677987 A CN 114677987A CN 202210447564 A CN202210447564 A CN 202210447564A CN 114677987 A CN114677987 A CN 114677987A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application discloses a display panel and a display device, which comprise a display area and a fan-out area, wherein the fan-out area comprises a first fan-out wiring area and a second fan-out wiring area arranged on at least one side of the first fan-out wiring area, a plurality of signal wires are arranged on the first fan-out wiring area, and the signal wires are used for being connected with the display area and providing driving signals for the display area; and a plurality of auxiliary wires are arranged on the second fan-out wire area, and the auxiliary wires are electrically connected with the first common electrode to form resistance compensation for the signal output end of the drive IC and/or the auxiliary wires and the second common electrode to form capacitance compensation for the signal output end of the drive IC.
Description
Technical Field
The present application relates generally to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the further improvement of the display requirement, the pixel resolution of the display device is larger and larger, correspondingly, more and more data lines are connected with the pixels, and the number of the upper output terminals of the corresponding ICs is larger and larger to match the number of the data lines in the display area.
When the IC is output, the panel load value can be stably output under the condition that the normal panel has RC load, and if the RC load value on the display panel drifts, the signal output end can generate shaking oscillation; when the screen resolution is smaller than the minimum resolution that the IC can support, the redundant IC input terminal still generates an output action at this terminal, and then the input terminal on the panel will generate a swing oscillation phenomenon at the signal output terminal under the condition of no load or insufficient load, and this swing oscillation phenomenon will cause redundant power consumption.
Disclosure of Invention
In view of the above-mentioned defects or shortcomings in the prior art, it is desirable to provide a display panel and a display device, which can reduce the shaking oscillation phenomenon of the signal output terminal, reduce power consumption, and improve the display effect.
In a first aspect, the present application provides a display panel comprising a display area and a fan-out area, the fan-out area comprising a first fan-out routing area and a second fan-out routing area disposed on at least one side of the first fan-out routing area, wherein,
a plurality of signal wires are arranged on the first fan-out wire area and are used for being connected with the display area and providing driving signals for the display area;
and a plurality of auxiliary wires are arranged on the second fan-out wire routing area, and the auxiliary wires are electrically connected with the first common electrode to form resistance compensation for the signal output end of the drive IC and/or the auxiliary wires and the second common electrode to form capacitance compensation for the signal output end of the drive IC.
Optionally, the fan-out area includes a first input pin area near one side of the display area and a second input pin area near one side of the driver IC; the second input pin area comprises a second signal input terminal connected with the signal routing and a suspending input terminal connected with the auxiliary routing.
Optionally, the display area includes a plurality of data lines extending in a first direction, and the first input pin area includes first signal input terminals in one-to-one correspondence with the data lines.
Optionally, a signal output end on the driver IC is configured to output a data driving signal, where the signal output end includes a first output terminal and a second output terminal, the first output terminal is bound to the signal input terminal, and the second output terminal is bound to the floating input terminal.
Optionally, the first common electrode is disposed on a side of the second fan-out routing area close to the display area.
Optionally, the fan-out area includes a substrate base plate and the second common electrode disposed on the substrate base plate, an orthogonal projection of the second common electrode on the substrate base plate and an orthogonal projection of the auxiliary trace on the substrate base plate are at least partially overlapped, and the second common electrode is used for forming a capacitance compensation for a signal output terminal of a driver IC with the auxiliary trace and/or the first common electrode. Forming capacitance compensation for signal output terminal of drive IC
Optionally, an orthographic projection of the first common electrode on the substrate base plate at least partially overlaps with an orthographic projection of the second common electrode on the substrate base plate.
Optionally, the fan-out region includes a source-drain metal layer disposed on the substrate, and the source-drain metal layer is used to form the plurality of signal traces and the plurality of auxiliary traces.
Optionally, the source-drain metal layer and the first common electrode are overlapped in the second fan-out region, so that the first common electrode and the auxiliary routing line are electrically connected.
In a second aspect, the present application provides a display device comprising a display panel as described in any of the above.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the display panel that this application embodiment provided, through setting up supplementary line of walking, to having signal output on the drive IC nevertheless not carried out load compensation by the unsettled input terminal that display panel used, prevent that drive IC signal output part from taking place to whip and vibrate, reduce drive IC's consumption, improve display effect.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 3 is an enlarged schematic view of position P1 in FIG. 2;
FIG. 4 is an enlarged schematic view of position P2 in FIG. 2;
FIG. 5 is an enlarged schematic view of position P3 in FIG. 2;
FIG. 6 is an enlarged schematic view of position P4 in FIG. 2;
fig. 7 is a schematic structural diagram of a driving IC according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of another display device provided in an embodiment of the present application;
FIG. 9 is a schematic cross-sectional view taken at position P2 in FIG. 2;
fig. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
As shown in fig. 1, the display device mainly includes a display panel and a driver IC. In practice, since display is performed by combining the driving of the source driver circuit and the gate driver circuit, a data connection portion (which may be referred to as Pad, Pin, terminal, Pad, or the like) for connecting to the source driver circuit and a gate connection portion (which may be referred to as Pad, Pin, terminal, Pad, or the like) for connecting to the gate driver circuit are directly formed when the array substrate is manufactured; and the array substrate is also provided with a data line routing and a grid line routing so that the data line is connected with the data connecting part through the data line routing and the grid line is connected with the grid connecting part through the grid line routing.
When the screen resolution of the display panel is smaller than the minimum resolution that can be supported by the IC, for example, when the screen resolution is 340 × 800, the number of output pins of the required data driving signals is 1020, and the number of output pins of the minimum resolution data driving signals that can be supported by the IC is 1080, that is, the output pins of 41 data driving signals are redundant (floating) and are not used, but there are still signals output on the 41 floating pins, and at this time, RC (Resistor/Capacitor) load value drift occurs. Therefore, when the output pin has no load or a load value is insufficient, a swing oscillation phenomenon occurs at the signal output terminal, and the swing oscillation phenomenon causes excessive power consumption.
The research shows that the simulation condition that can be ensured at the IC end is that the behavior of converging the oscillation can be seen under the ideal condition, but the oscillation can occur if the load required by a single signal routing is not met in the practical IC application, the smaller the resistor R is, the smaller the capacitor C is, the larger the amplitude of the oscillation is, the longer the convergence time is, and the larger the redundant power consumption is.
In order to solve the problem of oscillation risk caused by the IC, the wiring design for RC compensation is carried out at the panel display panel end, the oscillation risk of the IC suspension output end is reduced, and meanwhile, the unnecessary power consumption caused by oscillation is reduced.
As shown in fig. 2 to 6 in detail, the present application provides a display panel, which includes a display area AA and a fan-out area, wherein the fan-out area includes a first fan-out routing area D1 and a second fan-out routing area D2 disposed on at least one side of the first fan-out routing area D1, wherein,
a plurality of signal wires 10 are arranged on the first fan-out wire area D1, and the signal wires 10 are used for being connected with the display area AA and providing driving signals for the display area AA;
a plurality of auxiliary traces 20 are disposed on the second fan-out trace region D2, where the auxiliary traces 20 are electrically connected to the first common electrode 80 to form a resistance compensation for a signal output terminal of the driver IC and/or the auxiliary traces 20 and the second common electrode 90 to form a capacitance compensation for the signal output terminal of the driver IC.
In the embodiment of the present application, the display area AA includes a plurality of data lines extending in a first direction and a plurality of gate lines extending in a second direction, and the gate lines and the data lines cross to define a plurality of pixel regions.
It should be noted that the signal trace 10 may be a gate trace or a data line trace, and in the implementation of the present application, the data line trace is taken as an example for exemplary illustration. In this embodiment of the application, the driving IC may be a single touch driving IC or a single data driving IC, which is not limited in this embodiment of the application, and in different embodiments, different setting manners may be adopted.
Optionally, the fan-out area includes a first input pin area 30 near one side of the display area AA and a second input pin area 40 near one side of the driving IC; the first input pin area 30 includes first signal input terminals 50 corresponding to the data lines one to one. The second input pin area 40 includes a second signal input terminal 41 connected to the signal trace 10 and a floating input terminal 42 connected to the auxiliary trace 20.
In the embodiment of the present application, a first end of the signal trace 10 is connected to the data line in the display area AA through the first signal input terminal 50, a second end of the signal trace is connected to the second signal input terminal 41, and the second signal input terminal 41 is used for being bonded to the driving IC. The first end of the auxiliary trace 20 is connected to the first common electrode 80, and the second end is connected to the floating input terminal 42 for bonding with the driving IC.
Correspondingly, the signal output end on the driver IC is used for outputting a data driving signal, the signal output end includes a first output terminal 71 and a second output terminal 72, the first output terminal 71 is bonded to the signal input terminal, and the second output terminal 72 is bonded to the floating input terminal 42.
In the embodiments of the present application, the connection mode between the display panel and the driver IC is not limited. For example, the display panel and the driver IC may be connected to each other by COG Bonding (Bonding) through an ACF (Anisotropic Conductive Film), and the PCB and the glass panel may be connected by an FPC (Flexible Printed Circuit).
The display panel may also realize an ultra-narrow bezel by COF (Chip On Film) technology. The COF technology is a die-on-film packaging technology for fixing a driver IC to a flexible wiring board. By introducing this technique into a display device, the size of a circuit region (also referred to as a PAD region) of the display device can be reduced, thereby realizing an ultra-narrow bezel.
As shown in fig. 7, in the embodiment of the present invention, the signal output end of the driving IC includes a first output pin area, a second output pin area, a third output pin area, and a fourth output pin area arranged from the center to two sides, where the number of the second output pin area, the third output pin area, and the fourth output pin area is two and is respectively arranged at two sides of the first output pin area.
The first output pin area is provided with a first output terminal 71, the second output pin area is provided with a second output terminal 72, the third output pin area is provided with a third output terminal 73, and the fourth output pin area is provided with a fourth output terminal 74.
The terminals in the first output pin area provide driving signals to the data lines of the display panel through the driving IC via signal lines, and the number of the first output terminals 71 in the first output pin area is equal to the number of the data lines in the display area AA and the number of the first signal input terminals 50 in the first input pin area 30 and the second signal input terminals 41 in the second input pin area 40 in this embodiment.
The terminals on the second output pin area provide output signals through the driver IC, but the signals are not used by the display area AA, and the number of the second output terminals 72 in the second output pin area is equal to the number of the auxiliary traces 20 and the number of the floating signal terminals in the second input pin area 40 in the embodiment of the present application.
For example, when the screen resolution is 340 × 800, the number of output pins of the required data driving signals is 1020, and the number of output pins of the minimum resolution data driving signal that can be supported by the IC is 1080, the number of first signal output terminals on the first output pin area is 1020, and the number of second signal output terminals on the second output pin area is 41.
No output signal is provided by the driver IC on the third output terminal 73 in the third output pin field. The third output terminal 73 is determined by the model and specification of the driver IC, and the third output terminal 73 does not need to output a signal with respect to the resolution of the display panel, and therefore does not need to perform load compensation.
The fourth output pin area is used for connecting a grid driving circuit of the display panel and providing a grid driving signal for the display panel. In the embodiment of the present application, the gate driving circuit employs a GOA (gate On array) circuit, the fourth signal output terminal is connected to the GOA circuit, and the gate driving circuit provides the gate driving signals to the gate lines extending along the second direction Y in the display area AA.
In the embodiment of the present application, the first direction and the second direction may be perpendicular to each other or nearly perpendicular to each other, and the present application does not limit the specific directions of the first direction and the second direction. In this application, the arrangement direction of the pixel columns is exemplarily taken as a first direction, and the arrangement direction of the pixel rows is taken as a second direction. Of course, in other embodiments, the first direction and the second direction may be interchanged, the first direction may be an arrangement direction of pixel rows, and the second direction may be an arrangement direction of pixel columns.
It should be noted that, in the embodiment of the present application, the fan-out area is exemplarily illustrated as being disposed on the lower frame of the display panel, but the embodiment of the present application is not limited thereto, and the fan-out area may be disposed on the upper frame, the left frame, or the right frame of the display panel. In addition, the total number of terminals in each lead area is not limited in the embodiment of the present application, and in different embodiments, different settings may be performed depending on different devices and application scenarios; the number of terminal rows per lead field can be adjusted depending on the device or application scenario. Can be two rows and also can be 3-5 rows.
In this embodiment of the application, the first output pin area is disposed in the middle of the driver IC, and the second output pin area is disposed in two parts, where the two parts are respectively located at two sides of the first output pin area, and each second output pin area is used for connecting the auxiliary routing 20 corresponding to the compensation area on the second fan-out routing area D2, so as to narrow the frame and avoid the problems of increase of fan-out routing oblique angle and narrowing of line width.
It should be noted that the display device in the embodiment of the present application may further include a plurality of driver ICs, as shown in fig. 8. Each driving IC is connected to the display panel through a fan-out area, each fan-out area may include a first fan-out routing area D1 and a second fan-out routing area D2, and each fan-out area may further include a first fan-out routing area D1 and two second fan-out routing areas D2 respectively located at one side of the first fan-out routing area D1.
Of course, in the case of providing the two fan-out regions, the first output pin region and the second output pin region may be provided in each of the two fan-out regions; for example, for a source drive IC (generally including a plurality), the source drive ICs may be dispersedly disposed in two connection regions; each fan-out area can also be provided with a fourth output pin area, for example, for a gate driving circuit, a double-side driven GOA circuit can be adopted; the present invention is not limited to this, and the setting may be selected according to actual needs.
The width and length for different auxiliary traces 20 can be determined by the output signal to be compensated. The shape of the auxiliary trace 20 in this application is generally the same as the shape of the data trace, and the trace manner is similar. In some special routing forms, the routing manner can be determined according to the signal on the signal output terminal and the required load value. The load value of the auxiliary trace 20 is adjusted by increasing the width of the trace, extending the length of the trace, etc. for different output signals.
Specifically, the auxiliary trace 20 may be a linear, a folded-line, or a curved trace. When the auxiliary wire 20 is designed to be a linear wire, the process design difficulty of the auxiliary wire 20 can be reduced, and when the auxiliary wire 20 is designed to be a folded wire or a curved wire, the extending length of the auxiliary wire 20 can be reduced, which is beneficial to reducing the wiring difficulty of the wire, and what wire mode the auxiliary wire 20 specifically adopts can be set according to actual needs, and no specific limitation is made here.
In this embodiment, the auxiliary wires 20 are made of a conductive material, so that the resistors can be used for RC load compensation of the output end. In the embodiment of the present invention, the material of the signal trace 10 and the auxiliary trace 20 is not limited, and the signal trace and the auxiliary trace can be electrically conductive. Such as but not limited to a metallic material. In application, the signal trace 10 and the auxiliary trace 20 may be disposed in a single layer, or may be disposed in the same layer as the conductive pattern on the substrate, for example, the source/drain metal layer 6 and the gate metal layer 4 may be disposed in the same layer.
In an embodiment of the present application, as shown in fig. 9, the fan-out area includes a first common electrode 80 disposed on a side of the second fan-out routing area D2 close to the display area AA, and the auxiliary routing 20 is electrically connected to the first common electrode 80. The second common electrode 90 is used for being connected to a VCOM signal, so as to form a capacitance with the auxiliary trace 20 and/or the first common electrode layer 80, and perform capacitance compensation on a signal input end of the driving IC; one end of the auxiliary wire 20 is connected to the signal output end of the driver IC, and the other end is electrically connected to the first common electrode 80 for resistance compensation, thereby preventing oscillation.
Optionally, the fan-out area includes a substrate 1 and a second common electrode 90 disposed on the substrate 1, an orthogonal projection of the second common electrode 90 on the substrate 1 is at least partially overlapped with an orthogonal projection of the auxiliary trace 20 and the first common electrode 80 on the substrate 1, and the second common electrode 90 is used for forming capacitance compensation for a signal output end of the driver IC with the auxiliary trace 20 and the first common electrode 80.
In the embodiment of the present application, a certain overlapping area exists between the second common electrode 90 and the auxiliary trace 20, so that a capacitor can be formed between the auxiliary trace 20 and the second common electrode 90, and thus a load on the auxiliary trace 20 can be increased.
It should be noted that, in the embodiment of the present application, the second common electrode 90 may be located only in the second fan-out trace area D2, and only provide the load value compensation for the auxiliary trace 20, which is determined according to the load value on the data trace, since the load value required by the first signal output terminal is provided by the data trace and the data line on the display area AA, the load value is sufficient to provide stable output of the first signal output terminal on the driving IC, and the second common electrode 90 is not needed to provide the compensation.
In addition, the orthographic projection of the first common electrode 80 on the substrate 1 is at least partially overlapped with the orthographic projection of the second common electrode 90 on the substrate 1. Due to the overlapping area between the first common electrode 80 and the second common electrode 90, capacitance can be formed between the auxiliary trace 20 and the second common electrode 90, and thus the load on the auxiliary trace 20 can be increased.
In different embodiments, the first common electrode 80 and the second common electrode 90 may be planar electrodes or slit electrodes, and the slit shape may be an oblique strip shape, a zigzag shape, an X shape, a Y shape, or the like. The shape of the common electrode can be selected according to the needs according to different devices and application scenes.
In the embodiment of the present application, as shown in fig. 10, the substrate is an array substrate, where the array substrate includes a substrate 1, an active layer 2, a gate insulating layer 3, a gate metal layer 4, an interlayer dielectric layer 5, a source-drain metal layer 6, and a planarization layer 7, which are stacked.
Optionally, the fan-out region includes a source-drain metal layer 6 disposed on the substrate of the substrate 1, where the source-drain metal layer 6 is used to form the plurality of signal traces 10 and the plurality of auxiliary traces 20. The auxiliary wiring 20 and the signal wiring 10 can be formed through the same conductive layer and the same process with the source-drain metal layer 6, the manufacturing process is simple, the cost is low, and the thickness of the array substrate is small because no additional conductive layer is needed to be added for forming the auxiliary wiring 20 and the signal wiring 10. The first common electrode 80 and the second common electrode 90 may be ITO.
Optionally, the source-drain metal layer 6 is lapped with the first common electrode 80 in the second fan-out region, and a via hole is formed between the source-drain metal layer 6 and the first common electrode 80, so that the first common electrode 80 is electrically connected with the auxiliary trace 20. The specific arrangement is not particularly limited herein.
It should be noted that the second common electrode 90 and the first common electrode 80 may be disposed according to actual situations, for example, the second common electrode 90 may be disposed separately, or the first common electrode 80 may be disposed separately, or the second common electrode 90 and the first common electrode 80 may be disposed simultaneously, and the specific disposing manner is not limited in this respect.
The application provides a display device comprising a display panel as described in any of the above. The display device may be: liquid crystal panels, electronic paper, Organic Light-Emitting Diode (OLED) panels, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigators and other products or components with display functions.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Terms such as "disposed" and the like, as used herein, may refer to one element being directly attached to another element or one element being attached to another element through intervening elements. Features described herein in one embodiment may be applied to another embodiment, either alone or in combination with other features, unless the feature is not applicable or otherwise stated in the other embodiment.
The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the scope of the described embodiments. It will be appreciated by those skilled in the art that many variations and modifications may be made to the teachings of the invention, which fall within the scope of the invention as claimed.
Claims (10)
1. A display panel comprising a display area and a fan-out area, the fan-out area comprising a first fan-out routing area and a second fan-out routing area disposed on at least one side of the first fan-out routing area, wherein,
a plurality of signal wires are arranged on the first fan-out wire area and are used for being connected with the display area and providing driving signals for the display area;
and a plurality of auxiliary wires are arranged on the second fan-out wire area, and the auxiliary wires are electrically connected with the first common electrode to form resistance compensation on a signal output end of the drive IC and/or form capacitance compensation with the second common electrode.
2. The display panel according to claim 1, wherein the fan-out region includes a first input pin region near a side of the display region and a second input pin region near a side of a driver IC; the second input pin area comprises a second signal input terminal connected with the signal routing and a suspended input terminal connected with the auxiliary routing.
3. The display panel according to claim 2, wherein the display region includes a plurality of data lines extending in a first direction, and the first input pin region includes first signal input terminals in one-to-one correspondence with the data lines.
4. The display panel according to claim 2, wherein the signal output terminal on the driving IC is configured to output a data driving signal, and the signal output terminal comprises a first output terminal and a second output terminal, the first output terminal is bonded to the signal input terminal, and the second output terminal is bonded to the floating input terminal.
5. The display panel of claim 1, wherein the first common electrode is disposed on a side of the second fan-out routing area near the display area.
6. The display panel according to claim 1, wherein the fan-out area comprises a substrate base plate and the second common electrode disposed on the substrate base plate, an orthogonal projection of the second common electrode on the substrate base plate at least partially overlaps an orthogonal projection of the auxiliary trace on the substrate base plate, and the second common electrode is used for forming capacitance compensation for a signal output terminal of a driving IC with the auxiliary trace and/or the first common electrode.
7. The display panel according to claim 6, wherein an orthogonal projection of the first common electrode on the base substrate at least partially overlaps with an orthogonal projection of the second common electrode on the base substrate.
8. The display panel of claim 5, wherein the fan-out region comprises a source-drain metal layer disposed on a substrate, the source-drain metal layer being used to form the plurality of signal traces and the plurality of auxiliary traces.
9. The display panel according to claim 8, wherein the source-drain metal layer overlaps the first common electrode in the second fan-out region to electrically connect the first common electrode and the auxiliary trace.
10. A display device comprising the display panel according to any one of claims 1 to 9.
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| CN202210447564.4A CN114677987B (en) | 2022-04-26 | 2022-04-26 | Display panel and display device |
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| CN202210447564.4A CN114677987B (en) | 2022-04-26 | 2022-04-26 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024044946A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Display panel, circuit board, and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107436696A (en) * | 2016-05-26 | 2017-12-05 | 鸿富锦精密工业（深圳）有限公司 | Touch panel and the display device with the touch panel |
| CN109032424A (en) * | 2018-09-05 | 2018-12-18 | 张家港康得新光电材料有限公司 | A kind of touch panel, preparation method and touch control display apparatus |
| CN109557734A (en) * | 2018-10-31 | 2019-04-02 | 武汉华星光电技术有限公司 | Display panel and display module |
-
2022
- 2022-04-26 CN CN202210447564.4A patent/CN114677987B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107436696A (en) * | 2016-05-26 | 2017-12-05 | 鸿富锦精密工业（深圳）有限公司 | Touch panel and the display device with the touch panel |
| CN109032424A (en) * | 2018-09-05 | 2018-12-18 | 张家港康得新光电材料有限公司 | A kind of touch panel, preparation method and touch control display apparatus |
| CN109557734A (en) * | 2018-10-31 | 2019-04-02 | 武汉华星光电技术有限公司 | Display panel and display module |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024044946A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Display panel, circuit board, and display device |
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| CN114677987B (en) | 2023-07-07 |
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