CN114397786B

CN114397786B - Display substrate and display device

Info

Publication number: CN114397786B
Application number: CN202210090005.2A
Authority: CN
Inventors: 王彦明; 王翠娥; 蔡修军; 王立冬; 王冬; 杜润飞; 陈高伟; 崔利宝; 马晓; 张铮; 曹学文; 王大威
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2022-01-25
Filing date: 2022-01-25
Publication date: 2024-05-17
Anticipated expiration: 2042-01-25
Also published as: CN114397786A

Abstract

The application discloses a display substrate and a display device, wherein the display substrate comprises a display area and a non-display area positioned at the periphery of the display area, and the display substrate comprises an input end and two output ends positioned in the non-display area; the two output ends are respectively arranged at two sides of the input end; the input end comprises a first pad area, and the first pad area is provided with a plurality of input pads; the two output ends comprise a second bonding pad area and a third bonding pad area, a plurality of first output bonding pads are arranged on the second bonding pad area, and a plurality of second output bonding pads are arranged on the third bonding pad area.

Description

Display substrate and display device

Technical Field

The application relates to the technical field of display, in particular to a display substrate and a display device.

Background

With the continuous development of display technology and the continuous increase of public demands, high-screen-ratio display has become an increasing trend of being unblockable, and a mobile device with a high-screen-ratio has a narrower frame and a wider display area compared with the existing mobile device, and has a smaller overall dimension under the same screen size. Therefore, how to narrow the LCD screen lower bezel is important.

Disclosure of Invention

In view of the foregoing drawbacks or shortcomings in the prior art, it is desirable to provide a display substrate and a display device, which can narrow a lower frame of a display panel, can narrow a lateral width of an FPC, and improve a whole screen occupation ratio.

In a first aspect, the present application provides

The display substrate is characterized by comprising a display area and a non-display area positioned at the periphery of the display area, wherein the display substrate comprises an input end and two output ends positioned in the non-display area;

The two output ends are respectively arranged at two sides of the input end;

the input end comprises a first pad area, and the first pad area is provided with a plurality of input pads;

the two output ends comprise a second bonding pad area and a third bonding pad area, a plurality of first output bonding pads are arranged on the second bonding pad area, and a plurality of second output bonding pads are arranged on the third bonding pad area.

Optionally, the input pad is used for being connected with a flexible circuit board and providing an input signal through the flexible circuit board;

The first output pad is used for being connected with the display panel and providing a first driving signal for the display panel;

the second output pad is used for being connected with the GOA unit of the display panel and providing a second driving signal for the GOA unit.

Optionally, the input pads are arranged in an array along a first direction in the first pad area, the widths of the plurality of input pads are different, and the first direction is parallel to critical lines of the display area and the non-display area.

Optionally, the input pads are arranged in a plurality of rows and an array on the first pad area, and input signals of the input pads located in the same column are the same.

Optionally, two of the second pad regions are symmetrically disposed about the first pad region, and/or two of the third pad regions are symmetrically disposed about the first pad region.

Optionally, the second pad area is used for connecting with a contact control wire and/or a source wire, and the first output pads are arranged on the second pad area in an array along a first direction.

Optionally, the display panel includes a first display area and a second display area disposed along a first direction, and the second pad area is electrically connected with the first display area on the same side through a first wire; the second pad region is electrically connected with the second display region on the same side through a second wire.

Optionally, the first output pads are arranged in a plurality of rows on the second pad area in an array manner, and the number of the first output pads on each row is the same.

Optionally, the first output pads include a plurality of pad rows arrayed in the second direction on the second pad region, the pad rows include a first pad row and at least one second pad row, the first pad row is disposed on a side far from the display region, and the number of the first output pads on the first pad row is smaller than the number of the first output pads on the second pad row.

Optionally, the first output pads between two adjacent pad rows are arranged in a staggered array.

Optionally, the third pad region is located at a side of the second pad region remote from the first pad region, and the second output pads are arranged in an array along a first direction on the third pad region.

Optionally, a lower edge of the third pad region is flush with a lower edge of the second pad region.

Optionally, the third pad area is flush with the first pad row along the second direction, and the area where the third pad area and the first pad row are located corresponds to two side edges of the area where the second pad row is located.

Optionally, the third pad area is located at a side of the first pad row close to the first pad area; or the third pad region is positioned at one side of the first pad row away from the first pad region.

Optionally, the third pad area is disposed on a side of the display substrate away from the display panel, the second output pad is electrically connected with the GOA unit through a third wire, and the third wire is connected with an upper edge of the third pad area.

Optionally, the third pad area is disposed on a side of the display substrate, which is close to the display area, and the second output pad is electrically connected to the GOA unit through a fourth wire, and the fourth wire is connected to a lower edge of the third pad area.

Optionally, the second output pad is electrically connected with the GOA unit through a third wire and a fourth wire; one of the third wire and the fourth wire is connected with the upper edge of the third pad area, and the other wire is connected with the lower edge of the third pad area.

Optionally, a redundant pad area is arranged on one side of the output end, close to the display area, of the display substrate, and a plurality of redundant pads are arranged on the redundant pad area in an array manner.

In a second aspect, the present application provides a display device comprising a display substrate as described in any one of the above.

Optionally, the device further comprises a flip chip film, wherein the flip chip film comprises a flexible circuit board and a drive IC (integrated circuit) arranged on the flexible circuit board, and the first bonding pad area is electrically connected with the flip chip film through an input wiring;

the flip chip film is provided with a first bonding area bonded with the input wiring, and the first bonding area is provided with first pins which are in one-to-one correspondence with the input bonding pads;

And a second bonding area bonded with the flexible circuit board is further arranged on the flip chip film, and second pins corresponding to the first pins one by one are arranged on the second bonding area.

Optionally, a third bonding area matched with the second bonding area is arranged on the flexible circuit board, and third pins corresponding to the second pins one to one are arranged on the third bonding area.

Optionally, the display device further comprises a driving IC bonded with the display substrate, a fourth bonding area matched with the first bonding pad area is arranged on the driving IC, and fourth pins corresponding to the input bonding pads one to one are arranged on the fourth bonding area.

The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:

according to the driving device provided by the embodiment of the application, the physical width of the driving device is narrowed through the adjustment of the positions and the number of the bonding pads, the total width of the input end is narrowed, the size of the FPC bonding area is narrowed, and the scheme of simultaneously narrowing the driving device and the FPC to realize a narrow frame is realized.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

Fig. 1 is a schematic structural diagram of an external appearance of a conventional display device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an external appearance of a conventional elliptical display device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a conventional COG according to an embodiment of the present application;

FIG. 4 is a partially enlarged schematic illustration of a conventional COG according to an embodiment of the present application;

Fig. 5 is a schematic structural diagram of a display substrate according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another display substrate according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a bonding method between a driving IC and an FPC in a conventional COG according to an embodiment of the present application;

FIG. 8 is an enlarged schematic view of a portion of a first pad area according to an embodiment of the present application;

FIG. 9 is an enlarged schematic view of a portion of a second pad area and a third pad area provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of a first output pad according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another first output pad according to an embodiment of the present application;

FIG. 12 is an enlarged schematic view of a portion of a redundant pad area provided by an embodiment of the present application;

FIG. 13 is a schematic view of a prior art embodiment of a narrowed dimension of a lower frame;

Fig. 14 is a schematic view illustrating a narrowed dimension of a lower frame of a display device according to an embodiment of the present application;

FIGS. 15-20 are schematic diagrams illustrating different positional relationships of a display substrate according to embodiments of the present application;

FIG. 21 is a schematic structural diagram of a flip chip film according to an embodiment of the present application;

fig. 22 is a schematic diagram of an input trace according to an embodiment of the present application.

Detailed Description

The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the application are shown in the drawings.

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.

The liquid crystal display panel mainly includes a glass panel, a PCB (Printed Circuit Board, a printed circuit board), a driving IC (INTEGRATED CIRCUIT, an integrated circuit board), etc., and generally uses a COG Bonding (Bonding) method, and connects the glass panel and the driving IC through an ACF (Anisotropic Conductiveadhesive Film, anisotropic conductive film), and the PCB is connected with the glass panel through an FPC (Flexible Printed Circuit, a flexible circuit board).

In addition, the prior art realizes an ultra-narrow frame by COF (Chip OnFilm, flip chip film) technology. The COF technology is a die-attach technology for fixing a driver IC to a flexible wiring board. By introducing the technology into the display device, the size of a circuit area (also called a PAD area) of the display device can be reduced, so that an ultra-narrow frame is realized.

Although COF technology can achieve a smaller Panel lower frame than COG technology, the overall width of FPC is large due to too many traces; the COF substrate has a thick bending resilience force and the COF bending protrusion Panel is 0.4-0.5 than the FPC protrusion of the COG scheme. The COF scheme may achieve a smaller Panel 1.6mm lower frame than the COG scheme, but the overall width of the bonding region is large, e.g., 53mm, due to too many traces, compared to 36mm for the COG scheme FPC 300.

With the change of the appearance of the LCD full screen display device, the conventional small chamfer form has gradually evolved into a circular or oval shape, and fig. 1 shows the appearance of a conventional display device; fig. 2 shows an oval display device appearance. The overall screen occupation ratio is improved, the lower Panel frame of the Panel is required to be narrowed, and the transverse width of the FPC300 is required to be narrowed, so that the evolution of the appearance brings more serious test to the realization of the narrow frame.

In fig. 3, a lower frame design in a conventional COG scheme is shown, and a driving IC is provided with a first pad area a 'and two third pad areas C' on a side far from a display panel, wherein the first pad area a 'is used for providing an input signal to the driving IC100' through an FPC300', the third pad areas C' are located on both sides of the first pad area a ', and each of the third pad areas C' is connected to a GOA (GATE DRIVER on Array, array substrate row driving) unit on the same side to provide a GOA driving signal to the GOA unit. The driving IC100' is provided with a second pad region B ' at a side close to the display panel, and a first output pad on the second pad region B ' is used for electrically connecting with a source trace of the display panel and a Rx trace of a touch for providing a source signal and a touch signal to the display panel.

The lower frame of the traditional COG LTPS display panel is limited by a process, and the lower frame reaches the bottleneck of 2.9 mm; the number of bonding pins of the FPC300 'is generally 250-300, and is limited by the number and width of input pads of the IC connected with the bonding pins and the wiring width of the FPC300, and the transverse width of the FPC300' has no narrowing scheme.

When the display panel is applied, the panel is connected with the second bonding pad area B' of the IC through bonding pads by the fan-out wires, the panel fan-out wires are gradually converged to the driving IC side from the display panel side, and the width is gradually reduced, as shown in fig. 4. For example, for LTPS display panels, the source and Rx traces are about 1656, so when the second pad region B' is provided, 2-4 rows of the first output pad array are typically required, and the number of the first output pads is typically 1656; the number of second output pads in the third pad area is generally 20 to 25.

The first pad area a 'is connected with the bonding area of the FPC300' through a fan-out trace, and the fan-out trace is fanned out from the driving IC100 'side to the FPC300' side by a trapezoid trace which is changed from small to large. For example, the total number of input pads is 700-800, where many signals are the same, typically 250-300 to the FPC300 bonding PIN, the Pitch (Pitch) of the PIN of the FPC300 is typically 0.11-0.12 mm, but the Pitch (Pitch) between pads of the driver IC is typically 0.044mm, and obviously the two pitches (Pitch) are not an order of magnitude.

Assuming that the process Pitch (Pitch) of the FPC300' is not limited, simply narrowing the width of the FPC300' will bring about inconsistent Pitch with the bonding area of the IC100', and at this time, the fan-out cable-stayed angle of the panel will increase, the line width will be narrowed, and the drawbacks of increasing the distance between the IC100' and the FPC300' and increasing the cable impedance will be contradicted with the narrowing of the lower frame.

Referring to fig. 5 in detail, the present application provides a display substrate, which includes a display area and a non-display area located at the periphery of the display area, wherein the display substrate includes an input end 10 and two output ends 20 located in the non-display area;

The two output ends 20 are respectively arranged at two sides of the input end 10;

the input terminal 10 includes a first pad area a, on which a plurality of input pads 1 are disposed, and the two output terminals 20 each include a first pad area B and a third pad area C; a plurality of first output pads 2 are arranged on the first pad area B; the third pad area C is provided with a plurality of second output pads 3.

In the embodiment of the present application, the input pad 1 is used for being connected with the flexible circuit board FPC300 and providing an input signal through the flexible circuit board FPC 300; the first output pad 2 is used for being connected with the display panel 400 and providing a first driving signal to the display panel 400;

the second output pad 3 is used to connect with and provide a second driving signal to the GOA unit of the display panel 400.

In the embodiment of the application, the input end 10 is arranged in the middle of the driving IC, the output end 20 is arranged as two parts, the two parts are respectively positioned at two sides of the input end 10, each output end 20 is used for connecting with the fan-out wiring at one side corresponding to the display panel 400, and the problems of increasing the oblique angle of the fan-out wiring and narrowing the line width are avoided while the frame is narrowed. It should be noted that, in the embodiment of the present application, the display substrate 100 is disposed at the lower frame of the display panel 400 for illustration, but the embodiment of the present application is not limited thereto, and the display substrate 100 may be disposed at the upper frame, the left frame or the right frame of the display panel 400. In addition, the total number of pads on each pad area is not limited in the embodiment of the present application, and in different embodiments, different settings may be performed according to the device and the application scenario.

In addition, in the embodiment of the present application, a first direction X and a second direction Y are defined to correspond to one edge direction of the display area, and are parallel to a critical line of the display area and the non-display area, respectively, and the first direction X is perpendicular to the second direction Y. In the present application, the first direction X is taken as the transverse direction of the display area, the second direction Y is taken as the longitudinal direction of the display area, and the first direction and the second direction can be interchanged in some embodiments. The lower frame narrowing in the present application may be a single longitudinal narrowing or a single transverse narrowing, or may be a simultaneous longitudinal and transverse narrowing. The embodiment of the application is not limited to this, and in different embodiments, the adjustment is performed according to the narrowing requirement.

Example 1

As shown in fig. 6, in the embodiment of the present application, the lower edge of the first pad area a is as close to the lower edge of the display substrate 100 as possible, and when the number of pads is large, the pad array extends from the lower edge of the display substrate 100 to the upper edge and is arranged in an array manner, so that the lower frame of the display device can be narrowed longitudinally. It should be noted that, in the embodiment of the present application, the lower edge of the display substrate 100 is defined as the edge near the FPC300, and the upper edge of the display substrate 100 is defined as the edge near the display panel 400. The first pad area a is electrically connected to the flip chip film COF200 through the input trace 8.

Fig. 7 shows a bonding manner between the display substrate 100 'and the FPC300' in the conventional COG, where the IC input pad 1 'is set to have an equal width, and is connected to the bonding pins of the FPC through the gradually increasing input trace 8', and in terms of design and process, the impedance between the IC input pad 1 'and the bonding pins of the FPC300' needs to satisfy a certain condition, such as < 5 Ω to 10 Ω, otherwise, the transmission efficiency will be affected. In some embodiments, the pads are identical signals and are connected together by wires to achieve the purpose of reducing impedance, but the fanout wire manner is disadvantageous for frame reduction.

In the embodiment of the present application, as shown in fig. 8, the input pads 1 are arranged in an array along the first direction X in the first pad area a, and the widths of the plurality of input pads 1 are different.

It should be noted that, the bonding impedance between the input pad 1 and the bonding pin of the FPC300 accounts for more than 60-70% of the total impedance, so when the widths of the different pads are set, the total area of the pads corresponding to each signal needs to be similar to the total area of the pads with the same signals in the prior art. Therefore, in the setting, the setting mode of the input pads 1 in the multiple-line equal-width mode may be adopted, as shown in the position (I) in fig. 8, or the setting mode of the input pads 1 in the multiple-line unequal-width mode may be adopted, as shown in the position (II) in fig. 8, and the selection setting may be performed on the basis of meeting the bonding impedance requirement.

In order to realize that the number of the first pad area a corresponds to the number of pads or pins on the bonding area of the FPC300, the number of columns of the input pads 1 needs to be similar to the total number of pins of the FPC300, and in this embodiment of the present application, when in setting, the input pads 1 are arranged in a plurality of rows and an array along the second direction Y on the first pad area a, and the input signals of the input pads 1 located in the same column are the same.

It should be noted that, in the embodiment of the present application, a schematic structure diagram of adding one row of pads above the pads corresponding to the same signal is shown, and when the pads are specifically set, two or three rows may be set, which is not limited in the present application, and of course, when different signals are set, the widths of the individual pads may be individually widened, so that the number of the total width and the total Pin of the input pad 1 in the lateral direction is narrowed without affecting the bonding impedance requirement. For example, after the input pads 1 are adjusted on the first pad area a, the total number of input pads 1 with 700-800 numbers is made to form the corresponding FPC300 with the total pin number of 250-300 numbers.

In the embodiment of the present application, the first pad area B is disposed at the left and right sides of the first pad area a, so that the longitudinal reduction of the display substrate 100 can be achieved, the display panel 400 includes a first display area and a second display area disposed along a first direction, and the first pad area B is electrically connected to the first display area located at the same side through a first trace 4; the first pad area B is electrically connected to the second display area on the same side through a second trace 5.

In order to achieve the reduction of the lower frame, the lower edge of the first pad region B is as close to the lower edge of the display substrate 100 as possible, and when the number of pads is large, the pad array is arranged to extend from the lower edge of the display substrate 100 to the upper edge, as shown in fig. 9, so that a narrow frame of the display device can be achieved. Preferably, the lower edge of the first pad region B is flush with the lower edge of the first pad region a.

The first pad area B is used for connecting with a contact control wire and/or a source wire, and the first output pads 2 are arranged on the first pad area B in an array along a first direction X. In the embodiment of the present application, the display substrate 100 may be a single touch driving IC or a single data driving IC, which is not limited in the embodiment of the present application, and in different embodiments, different arrangement manners may be adopted.

The longitudinal width of the display substrate 100 is reduced by disposing the first pad areas B on both sides of the first pad area a, but for LTPS, the first output pads 2 are arranged in a multi-row array on the first pad area B for further reduction of the lateral width due to resolution and other factors, for example, the source wiring and the Touch Rx wiring total about 1656 wirings.

In the embodiment of the present application, the number of the pad rows on the first pad area B may be adjusted according to the device or the application scenario. Two rows or 3-5 rows are possible. For example, when the total number of the existing signal lines (e.g., 1656 or more) is kept unchanged, the number of lines is adjusted to 3-5 lines, 828 pads can be distributed on the left and right sides, and the size of the pads and Pitch can be kept unchanged.

It should be noted that in the preferred embodiment of the present application, the number of the first output pads 2 on each row is the same. But for different layouts, for example even and odd rows, can be adjusted according to the number of pads so that the first output pads 2 are approximately equal in each row.

In the embodiment of the present application, there is also provided a layout manner of the first output pads 2 in the first pad area B, where the first output pads 2 between two adjacent pad rows are arranged in a staggered array, as shown in fig. 10 to 11. Fig. 10 shows a schematic layout of a first output pad 2 arranged in two rows, and fig. 11 shows a schematic layout of a first output pad 2 arranged in three rows, wherein each row of pads are staggered to facilitate Panel routing, and if the routing width is insufficient, the spacing between the pads can be increased appropriately. Of course, in other embodiments, the Panel wire may employ Gate, SD, ITO multi-layer wires, which reduces the wire impedance and reduces the wire area. This is not limiting in embodiments of the present application.

In an embodiment of the present application, two of the second pad areas are symmetrically disposed with respect to the first pad area, and/or two of the third pad areas are symmetrically disposed with respect to the first pad area. The third pad region C is located at a side of the first pad region B remote from the first pad region a, and the second output pads 3 are arranged in an array along the first direction X on the third pad region C. In order to reduce the lower frame, the lower edge of the third pad area C is flush with the lower edge of the first pad area B.

Wherein the number of the second output pads 3 corresponds to the number of GOA units of the display panel 400, and the second output pads 3 on the third pad area C of the display substrate 100 are connected to GOA units on the same side through GOA wires. It should be noted that, in different embodiments, different numbers of the second output pads 3 may be provided according to driving manners of the GOA units, for example, the number of the second output pads 3 on the third pad area C on a single side is 20 to 25 for the LTPS display device.

When the second output pads 3 are arranged, according to the difference in the number of GOA units and the reduction scheme, in a multi-row array on the third pad area C. In the embodiment of the present application, the number of the pad rows on the first pad area B may be adjusted according to the device or the application scenario, for example, two rows of pad rows are disposed on the third pad area C.

In addition, as shown in fig. 9, the display substrate 100 is provided with a redundant pad area F on a side of the output terminal 20 near the display area, and a plurality of redundant pads 9 are arrayed on the redundant pad area F. For an IC with a longitudinal height of the first pad area B being less than 0.15mm than the longitudinal width of the IC, in order to avoid the bonding under-voltage hidden trouble caused by no pad above the first output pad 2, a plurality of compensating redundant pads 9 may be designed on the upper edge of the IC for supporting the upper edge of the IC.

It should be noted that, in the embodiment of the present application, the arrangement position of the redundant pads 9 is not limited, and in some embodiments, the number of the redundant pads 9 and the inter-pad pitch are not limited, and the position of the redundant pad region F corresponding to the first pad region B may also be extended from the first pad region B to the third pad region C on the outer side.

After the redundant pad 9 is set, the source trace and the touch trace need to avoid the redundant pad 9, as shown in fig. 12, so the design will increase the lower frame by about 0.065 mm. The position, shape, etc. of the redundant pad 9 may be determined according to the height of the first pad region B to the edge of the IC in a specific application, and the present application is not limited thereto.

In the embodiment of the present application, by adjusting the height of the bonding pads and the array row number, the first bonding pad area a and the second bonding pad area B (which may include the redundant bonding pad area F) may be disposed in parallel at the same level, and fig. 13 shows a schematic diagram of the narrowing dimension of the lower frame in the prior art, where a0 is the distance from the side edge of the driving IC to the side frame of the display panel 400, B0 is the longitudinal height of the panel fan-out wiring area, h0 is the longitudinal height of the driving IC, and fig. 14 shows a schematic diagram of the narrowing dimension of the lower frame of the display device in an embodiment of the present application. The technical scheme of the application realizes the narrowing of the longitudinal height of the IC from h0 to h1. Next, a reduction in the lateral width of the IC is achieved, in which the distance between the leftmost or rightmost side edge of the driving IC and the side frame of the display panel 400 is narrowed from a0 to a1, so that the longitudinal height of the fanout wiring region can be narrowed from b0 to b1.

For example, when a0=19.5 narrows to a1=17.5 mm, b0=1.33 can narrow to b1=1.13 mm, and the bezel narrows to 0.2mm. The vertical narrowing frame is more than 0.35mm, and the maximum narrowing for the non-redundant bonding pad 9 is more than 0.4 mm. Therefore, the technical scheme of the application comprehensively narrows 0.55-0.6 mm. Meanwhile, the FPC300 may be narrowed from conventional 36mm to within 20mm in lateral width.

It should be noted that, when the frame narrowing design is performed, the process needs to be considered comprehensively, if the vertical width of the IC cannot be reduced, the capability of the process can be considered, for example, the vertical width is raised from 70-80nm to 30-40nm, so that more transistors and processing units can be placed. Under the condition of narrowing the vertical height of the IC, the transverse length of the IC can be properly widened, and the area of the IC is kept unchanged. For example, each pad region adopts a row of pad rows arranged in an array, and the IC height can be narrowed to about 0.5-0.6 nm, and the redundant pad 9 is not required to be designed at the upper edge of the IC. And in specific application, selecting according to different devices and application scenes.

Example two

In the embodiment of the present application, in order to further reduce the frame, the position of the third pad area C may be further adjusted. When in application, the selection can be performed according to different application scenes or different devices.

In one embodiment of the present application, as shown in fig. 15, the third pad region C is located at a side of the first pad region B remote from the first pad region a, and the third pad region C is disposed at a side of the display substrate 100 remote from the display panel 400. Preferably, the lower edge of the third pad region C is flush with the lower edge of the first pad region B. The second output pads 3 are arranged in an array along the first direction X on the third pad area C. The second output pad 3 is electrically connected to the GOA unit through a third trace 6, and the third trace 6 is connected to an upper edge of the third pad region C.

In this embodiment, the third pad area C is located at the left and right lower corners of the driving IC, and the GOA routing is located below the panel fan routing area, so that the panel fan routing is not affected; in addition, no other circuit is arranged at the lower edge of the driving IC, and a large-fillet design, such as a circular arc shape or an oval shape display device, can be correspondingly arranged. However, this design requires that the panel fanout traces be located away from the side frames, as close as possible to the middle of the display panel 400, the side frame of the display device may be enlarged somewhat because the fanout traces do not reach the edges of the IC.

In order to further optimize the side frame narrowing scheme of the display device, the location of the GOA trace may be adjusted, for example, as shown in fig. 16, the third pad region C is disposed on a side of the display substrate 100 near the display region, the second output pad 3 is electrically connected to the GOA unit through a fourth trace 7, and the fourth trace 7 is connected to a lower edge of the third pad region C. Optimizing the GOA routing to be routed from the lower edge of the third pad area C may reduce the side frame.

Of course, the third pad region C may be disposed at an intermediate position of the longitudinal height of the driving IC, and as shown in fig. 17, the second output pad 3 may be electrically connected to the GOA unit through a third trace 6 and a fourth trace 7, one of the third trace 6 and the fourth trace 7 may be connected to an upper edge of the third pad region C, and the other may be connected to a lower edge of the third pad region C. For example, the third trace 6 is electrically connected to an upper edge of the third pad region C, and the fourth trace 7 is electrically connected to a lower edge of the third pad region C.

It should be noted that, in the embodiment of the present application, the manner of the GOA unit routing is not limited, and in different embodiments, different settings may be performed according to different devices or application scenarios. In addition, for a larger number of second output pads 3, a multi-row pad row array arrangement, for example, two rows, may be employed. When two rows are provided, it may be adopted that the pad row on the side close to the display panel 400 is connected by the third wiring 6, and the pad row on the side far from the display panel 400 is connected by the fourth wiring 7.

In one embodiment of the present application, as shown in fig. 18, the first output pad 2 includes a plurality of pad rows arrayed in the second direction Y on the first pad region B, the pad rows including a first pad row 11 and at least one second pad row 12, the first pad row 11 being disposed on a side away from the display panel 400, the number of the first output pads 2 on the first pad row 11 being smaller than the number of the first output pads 2 on the second pad row 12. Wherein the third pad area C is positioned flush with the first pad row 11 in the second direction.

In this embodiment, the layout of the first output pads 2 on the first pad area B is optimized at the same time, so that the first pad row 11 and the third pad area C correspond to the positions of the second pad row 12 as much as possible, and preferably, the areas where the third pad area C and the first pad row 11 are located correspond to the edges of the two sides of the area where the second pad row 12 is located. Bonding imbalance is prevented by equalizing the layout of the pads.

When the third pad area C is set, the third pad area C is located at a side of the first pad row 11 close to the first pad area a, as shown in fig. 18; for the manner of GOA routing, the second output pad 3 may be electrically connected to the GOA unit through a fourth wire 7, and the fourth wire 7 is connected to the lower edge of the third pad area C. Or the third pad area C is located at a side of the first pad row 11 away from the first pad area a as shown in fig. 19. The second output pad 3 is electrically connected with the GOA unit through a third wire 6 and a fourth wire 7, one of the third wire 6 and the fourth wire 7 is connected with the upper edge of the third pad area C, and the other is connected with the lower edge of the third pad area C.

Still further, as shown in fig. 20, a scheme may be adopted, in which the second pad region is disposed on a side of the display substrate close to the display panel in the conventional scheme is integrated, and in order to further narrow the size of the lower frame relative to the conventional scheme, a row of first output pad regions may be disposed along a side of the display substrate close to the display panel, which covers the first pad region a and the second pad region B at the same time, and the remaining first output pads may be disposed in the second pad regions B distributed on both sides.

It should be noted that in the embodiment of the present application, a plurality of schemes are provided for the setting manner of the third pad area C, and when in specific application, different schemes may be adopted to reduce the lower frame of the display device according to different devices or different application scenarios.

Example III

With continued reference to fig. 5-6, the present application provides a display device including a display substrate 100 as described above.

The display substrate provided by the embodiment of the application can be applied to a COF scheme and a COG scheme, and the application is not limited to the COF scheme. In the embodiment of the present application, the physical width of the driving IC is narrowed by providing the adjustment of the positions and the number of pads on the display substrate 100, while narrowing the total width of the IC input pad 1 region. In order to realize the scheme of narrow frame and reduce the size of the FPC300, the application uses the COF200 (COF 200) as the transfer between the driving IC and the FPC300, and bonds with the driving IC at one end and the FPC300 at the other end, thereby realizing the narrowing of the lateral width of the bonding region. The scheme occupies smaller module appearance space, improves the whole screen occupation ratio, and is more suitable for special-shaped LCD module structures, in particular to whole appearance structures such as circular, elliptic and the like.

For example, for COF technology, the display device further includes a flip chip film, where the flip chip film includes a flexible circuit board and a driving IC disposed on the flexible circuit board, and the first pad area a is electrically connected to the flip chip film COF200 through an input trace 8; a first bonding area D bonded with the input wire 8 is arranged on the flip chip film COF200, and first pins corresponding to the input pads 1 one by one are arranged on the first bonding area D; the flip chip film COF200 is further provided with a second bonding area E bonded with the flexible circuit board FPC300, and the second bonding area E is provided with second pins corresponding to the first pins one by one, as shown in fig. 21.

In the embodiment of the present application, the input pad 1 with non-uniform width is used in the first pad area a, and when the input trace 8 is set, the trace mode is the same width as the pad, as shown in fig. 22. Accordingly, the first pin of the first bonding region D on the COF200 may make a one-to-one correspondence with the input pad 1 on the first pad region a, and the first bonding region D may be narrowed while narrowing the first pad region a of the driving IC.

Through analog calculation and optimization, the input pads 1 of the IC and pins on the COF200 can be approximately equal in width, the width is narrowed from the conventional 36mm width to within 20mm of the new scheme, and the number of pins of the COF200 is reduced from 320 to 260.

And a third bonding area matched with the second bonding area E is arranged on the Flexible Printed Circuit (FPC) 300, and third pins corresponding to the second pins one by one are arranged on the third bonding area. The pins of the first Pin of the first bonding area D, the second Pin of the second bonding area E, and the third Pin of the third bonding area are in the same sequence, i.e. the signals of pins at corresponding positions are the same.

And the second bonding area E and the third bonding area are as wide as possible. The conventional bonding region has a pin pitch of 44 μm and a width of 24 μm, but for 44 μm process pitch control, the conventional 0.12mm FPC300 cannot be used, and a COF Film process with higher precision, typically 26 μm, is required, so that the conventional bonding region can be better compatible with 44 μm process requirements.

On the COF200, the upper end is a first bonding region D, the pin pitch of the first bonding region D is 44 μm, and the pin pitch is similar to the pad pitch on the first pad region A of the drive IC end. The wiring on the COF200 is gradually widened from 24 μm to about 70 μm from the upper end, the pitch of the bottom wiring is about 120 μm, and the pitch of the pins of the second bonding region E is about 120 μm. When the COF is arranged, the longitudinal height of the COF200 is as small as possible, the wiring impedance is reduced, and the lower end of the COF Film is bonded with the FPC300 to realize physical connection.

However, the width of COFFilm in the technical solution provided in the present application may be narrowed from 35.8mm to 17mm, which is a half width of the conventional FPC300 solution. Therefore, the frame narrowing scheme provided by the embodiment of the application can be better suitable for large-fillet equipment. For example, a display device having a circular or elliptical shape.

For example, for COG technology, the display device further includes a driving IC bonded to the display substrate, where a fourth bonding area matched with the first bonding pad area is disposed on the driving IC, and fourth pins corresponding to the input pads one to one are disposed on the fourth bonding area. The setting of the fourth bonding area is the same as the setting of the bonding area of the flip chip film in the embodiment of the present application, and the present application is not described herein again.

In the embodiment of the application, four corners of the display device are rounded, as shown in fig. 2. For example, the fillet radius of the non-display area of the display panel 400 is 18mm to 26mm; the lower frame is 2.9 mm-2.35 mm. The transverse width of the first bonding area D is 36-20 mm.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the invention. Terms such as "disposed" or the like as used herein may refer to either one element being directly attached to another element or one element being attached to another element through an intermediate member. Features described herein in one embodiment may be applied to another embodiment alone or in combination with other features unless the features are not applicable or otherwise indicated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. Those skilled in the art will appreciate that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed.

Claims

1. The display substrate is characterized by comprising a display area and a non-display area positioned at the periphery of the display area, wherein the display substrate comprises an input end and two output ends positioned in the non-display area;

The two output ends are respectively arranged at two sides of the input end;

The two output ends comprise a second bonding pad area and a third bonding pad area, a plurality of first output bonding pads are arranged on the second bonding pad area, and a plurality of second output bonding pads are arranged on the third bonding pad area;

The first output pad comprises a plurality of pad rows arranged in an array along a second direction on the second pad region, the pad rows comprise a first pad row and at least one second pad row, and the first pad row is arranged at one side far away from the display region;

the third pad area and the first pad row are positioned flush in the second direction, and the area where the third pad area and the first pad row are positioned corresponds to the two side edges of the area where the second pad row is positioned.

2. The display substrate of claim 1, wherein the input pad is for connection with a flexible circuit board and provides an input signal through the flexible circuit board;

The first output pad is used for being connected with the display substrate and providing a first driving signal for the display substrate;

the second output pad is used for being connected with the GOA unit of the display substrate and providing a second driving signal for the GOA unit.

3. The display substrate according to claim 1, wherein the input pads are arranged in an array in a first direction in the first pad region, the widths of the plurality of input pads being different, the first direction being parallel to critical lines of the display region and the non-display region.

4. The display substrate according to claim 1, wherein the input pads are arranged in a plurality of rows and an array on the first pad region, and input signals of the input pads located in the same column are the same.

5. The display substrate according to claim 1, wherein two of the second pad regions are symmetrically disposed about the first pad region and/or two of the third pad regions are symmetrically disposed about the first pad region.

6. The display substrate according to claim 1, wherein the second pad region is used for connecting a contact control trace and/or a source trace, and the first output pads are arrayed along a first direction on the second pad region.

7. A display substrate according to claim 3, wherein the display area comprises a first display area and a second display area arranged along a first direction, the second pad area on one side of the first pad area being electrically connected to the first display area on the same side by a first trace; the second pad region located at the other side of the first pad region is electrically connected with the second display region located at the same side through a second wire.

8. The display substrate of claim 4, wherein the first output pads are arranged in a plurality of rows of arrays on the second pad region, the number of first output pads being the same on each row.

9. The display substrate of claim 4, wherein the number of first output pads on the first pad row is less than the number of first output pads on the second pad row.

10. A display substrate according to claim 8 or 9, wherein the first output pads between two adjacent rows of pads are arranged in a staggered array.

11. The display substrate according to claim 2, wherein the third pad region is located at a side of the second pad region remote from the first pad region, and the second output pads are arranged in an array along a first direction on the third pad region.

12. The display substrate of claim 11, wherein a lower edge of the third pad region is flush with a lower edge of the second pad region.

13. The display substrate of claim 11, wherein the third pad region is located on a side of the first pad row adjacent to the first pad region; or the third pad region is positioned at one side of the first pad row away from the first pad region.

14. The display substrate of claim 11, wherein the third pad region is disposed at a side of the display substrate remote from the display region, the second output pad is electrically connected to the GOA unit through a third trace, and the third trace is connected to an upper edge of the third pad region.

15. The display substrate of claim 11, wherein the third pad region is disposed at a side of the display substrate adjacent to the display region, the second output pad is electrically connected to the GOA unit through a fourth trace, and the fourth trace is connected to a lower edge of the third pad region.

16. The display substrate of claim 11, wherein the second output pad is electrically connected to the GOA unit through a third trace and a fourth trace; one of the third wire and the fourth wire is connected with the upper edge of the third pad area, and the other wire is connected with the lower edge of the third pad area.

17. The display substrate according to claim 1, wherein a redundant pad area is provided on a side of the output end, which is close to the display area, and a plurality of redundant pads are arranged on the redundant pad area in an array manner.

18. A display device comprising a display substrate according to any one of claims 1-17.

19. The display device of claim 18, further comprising a flip-chip film comprising a flexible circuit board and a drive IC disposed on the flexible circuit board, the first pad region being electrically connected to the flip-chip film through an input trace;

20. The display device of claim 19, wherein a third bonding region is disposed on the flexible circuit board and mates with the second bonding region, and wherein third pins are disposed on the third bonding region and in one-to-one correspondence with the second pins.

21. The display device of claim 20, further comprising a driver IC bonded to the display substrate, wherein a fourth bonding region is disposed on the driver IC and is matched with the first bonding pad region, and wherein fourth pins corresponding to the input bonding pads one to one are disposed on the fourth bonding region.