CN114397786A

CN114397786A - Display substrate and display device

Info

Publication number: CN114397786A
Application number: CN202210090005.2A
Authority: CN
Inventors: 王彦明; 王翠娥; 蔡修军; 王立冬; 王冬; 杜润飞; 陈高伟; 崔利宝; 马晓; 张铮; 曹学文; 王大威
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2022-01-25
Filing date: 2022-01-25
Publication date: 2022-04-26

Abstract

The application discloses a display substrate and a display device, wherein the display substrate comprises a display area and a non-display area which is arranged on the periphery of the display area, and the display substrate comprises an input end and two output ends which are arranged in the non-display area; the two output ends are respectively arranged at two sides of the input end; the input end comprises a first bonding pad area, and the first bonding pad area is provided with a plurality of input bonding pads; the two output ends comprise a second bonding pad area and a third bonding pad area, the second bonding pad area is provided with a plurality of first output bonding pads, and the third bonding pad area is provided with a plurality of second output bonding pads.

Description

Display substrate and display device

Technical Field

The present application relates generally to the field of display technologies, and in particular, to a display substrate and a display device.

Background

With the development of display technology and the increasing public demand, the high screen ratio display has become an increasingly non-blocking trend, and the mobile device with high screen ratio has a narrower frame, a wider display area, and a smaller overall size with the same screen size compared to the existing mobile device. Therefore, how to narrow the lower frame of the LCD screen is very important.

Disclosure of Invention

In view of the above-mentioned defects or shortcomings in the prior art, it is desirable to provide a display substrate and a display device, which can narrow the lower frame of the display panel, narrow the lateral width of the FPC, and improve the overall screen occupation ratio.

In a first aspect, the present application provides

A display substrate is characterized by comprising a display area and a non-display area positioned at the periphery of the display area, wherein the display substrate comprises an input end and two output ends positioned in the non-display area;

the two output ends are respectively arranged at two sides of the input end;

the input end comprises a first bonding pad area, and the first bonding pad area is provided with a plurality of input bonding pads;

the two output ends comprise a second bonding pad area and a third bonding pad area, the second bonding pad area is provided with a plurality of first output bonding pads, and the third bonding pad area is provided with a plurality of second output bonding pads.

Optionally, the input pad is used for connecting with a flexible circuit board and providing an input signal through the flexible circuit board;

the first output pad is used for being connected with the display panel and providing a first driving signal to the display panel;

the second output pad is used for being connected with a GOA unit of the display panel and providing a second driving signal for the GOA unit.

Optionally, the input pads are arranged in an array along a first direction in the first pad area, widths of the input pads are different, and the first direction is parallel to a critical line of the display area and the non-display area.

Optionally, the input pads are arranged in a plurality of rows on the first pad region, and the input signals of the input pads located in the same column are the same.

Optionally, two of the second pad regions are symmetrically disposed with respect to the first pad region, and/or two of the third pad regions are symmetrically disposed with respect to the first pad region.

Optionally, the second pad area is used for connecting a touch trace and/or a source trace, and the first output pads are arrayed on the second pad area along a first direction.

Optionally, the display panel includes a first display region and a second display region arranged along a first direction, and the second pad region is electrically connected to the first display region located on the same side through a first routing line; the second pad area is electrically connected with the second display area located on the same side through a second routing wire.

Optionally, the first output pads are arranged in a plurality of rows on the second pad region, and the number of the first output pads in each row is the same.

Optionally, the first output pads include a plurality of pad rows arranged in an array along the second direction on the second pad region, where the pad rows include a first pad row and at least one second pad row, the first pad row is disposed on a side away from the display region, and the number of the first output pads on the first pad row is less than the number of the first output pads on the second pad row.

Optionally, the first output pads between two adjacent pad rows are arranged in a staggered array.

Optionally, the third pad region is located on a side of the second pad region away from the first pad region, and the second output pads are arranged in an array along the first direction on the third pad region.

Optionally, a lower edge of the third pad region is flush with a lower edge of the second pad region.

Optionally, the third pad area is flush with the first pad row in position along the second direction, and the area where the third pad area and the first pad row are located corresponds to the two side edges of the area where the second pad row is located.

Optionally, the third pad region is located on a side of the first pad row close to the first pad region; or, the third pad region is located on a side of the first pad row away from the first pad region.

Optionally, the third pad area is disposed on a side of the display substrate away from the display panel, the second output pad is electrically connected to the GOA unit through a third trace, and the third trace is connected to an upper edge of the third pad area.

Optionally, the third pad area is disposed on a side of the display substrate close to the display area, the second output pad is electrically connected to the GOA unit through a fourth trace, and the fourth trace is connected to a lower edge of the third pad area.

Optionally, the second output pad is electrically connected to the GOA unit through a third trace and a fourth trace; one of the third wire and the fourth wire is connected with the upper edge of the third bonding pad area, and the other one of the third wire and the fourth wire is connected with the lower edge of the third bonding pad area.

Optionally, the display substrate is provided with a redundant pad area on one side of the output end close to the display area, and a plurality of redundant pads are arranged in an array on the redundant pad area.

In a second aspect, the present application provides a display device comprising a display substrate as described in any of the above.

Optionally, the chip on film package further comprises a chip on film, the chip on film package comprises a flexible circuit board and a driver IC disposed on the flexible circuit board, and the first pad region is electrically connected to the chip on film package through an input trace;

a first bonding area bonded with the input wiring is arranged on the chip on film, and first pins which are in one-to-one correspondence with the input bonding pads are arranged on the first bonding area;

the chip on film is also provided with a second bonding area bonded with the flexible circuit board, and the second bonding area is provided with second pins in one-to-one correspondence with the first pins.

Optionally, a third bonding area matched with the second bonding area is arranged on the flexible circuit board, and third pins in one-to-one correspondence with the second pins are arranged on the third bonding area.

Optionally, the display device further includes a driver IC disposed on the display substrate in a bonding manner, the driver IC is provided with a fourth bonding region matched with the first bonding pad region, and the fourth bonding region is provided with fourth pins corresponding to the input bonding pads one to one.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

the drive arrangement that this application embodiment provided, the adjustment through the position of pad and quantity realizes narrowing drive arrangement's physical width, narrows down the total width of input simultaneously, narrows down the size in FPC bonding area simultaneously, and the scheme of narrowing down in order to realize the narrow frame when realizing drive arrangement and FPC.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a schematic structural diagram of an appearance of a conventional display device according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram illustrating an appearance of a conventional elliptical display device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a conventional COG provided in an embodiment of the present application;

fig. 4 is a partially enlarged schematic view of a prior COG provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another display substrate provided in an embodiment of the present application;

FIG. 7 is a diagram illustrating a bonding manner between a driver IC and an FPC in a conventional COG according to an embodiment of the present disclosure;

fig. 8 is a partially enlarged schematic view of a first pad region according to an embodiment of the present disclosure;

fig. 9 is a partially enlarged schematic view of a second pad region and a third pad region provided in an embodiment of the present application;

fig. 10 is a schematic routing diagram of a first output pad according to an embodiment of the present application;

fig. 11 is a schematic routing diagram of another first output pad according to an embodiment of the present application;

fig. 12 is a partially enlarged schematic view of a redundant pad area according to an embodiment of the present application;

FIG. 13 is a schematic illustration of a bottom frame narrowing dimension in accordance with an exemplary embodiment of the present application;

FIG. 14 is a schematic view of a narrowing dimension of a bottom bezel of a display device according to an embodiment of the present application;

FIGS. 15-20 are schematic diagrams illustrating different positions of a display substrate according to embodiments of the present disclosure;

fig. 21 is a schematic structural diagram of a chip on film according to an embodiment of the present application;

fig. 22 is a schematic diagram of an input trace according to an embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

The lcd panel mainly includes a glass panel, a PCB (Printed Circuit Board), a driver IC (Integrated Circuit), and the like, and generally, the glass panel and the driver IC are connected by using a COG Bonding (Bonding) method and an ACF (Anisotropic conductive Film), and the PCB and the glass panel are connected by using a FPC (Flexible Printed Circuit).

In addition, in the prior art, a Chip On Film (COF) technology is used to realize an ultra-narrow frame. The COF technology is a die-on-film packaging technology for fixing a driver IC to a flexible wiring board. By introducing this technique into a display device, the size of a circuit region (also referred to as a PAD region) of the display device can be reduced, thereby realizing an ultra-narrow bezel.

Although the COF technology can realize a smaller Panel lower frame than the COG technology, the overall width of the FPC is large due to too many wirings; due to the fact that the COF substrate is thick, bending resilience is large, the COF bending protrusion Panel is 0.4-0.5% higher than that of the FPC of the COG scheme. The COF scheme may achieve a smaller Panel 1.6mm lower border than the COG scheme, but the overall width of the bonding area is large due to too many traces, for example 53mm, compared to 36mm for the COG scheme, which is the lateral width of the FPC 300.

With the change of the appearance of the LCD full-screen display device, the appearance of the traditional display device is shown in FIG. 1, which has gradually evolved from the traditional small chamfer form into a circle or an ellipse; fig. 2 shows an elliptical display device appearance. The proportion of the whole screen is improved, the lower frame of the Panel is narrowed, and the transverse width of the FPC300 is required to be narrowed, so that the evolution of the appearance provides more severe test for the realization of the narrow frame.

Fig. 3 shows a lower frame design in a conventional COG scheme, where a first pad area a 'and two third pad areas C' are disposed on a side of a Driver IC away from a display panel, where the first pad area a 'is used to provide an input signal to the Driver IC 100' through an FPC300 ', the third pad areas C' are located on two sides of the first pad area a ', and each third pad area C' is connected to a GOA (Gate Driver on Array) unit located on the same side, so as to provide a GOA driving signal to the GOA unit. The driving IC100 ' is provided with a second pad region B ' on a side close to the display panel, and the first output pad on the second pad region B ' is used for being electrically connected to the source trace of the display panel and the Rx trace for touch control, and is used for providing a source signal and a touch control signal to the display panel.

The lower frame of the traditional COG LTPS display panel is limited by the process, and reaches the bottleneck of 2.9 mm; the number of bonding pins of the FPC300 'is generally 250-300, which is limited by the number and width of the IC input pads connected with the FPC and the wiring width of the FPC300, and the transverse width of the FPC 300' is not narrowed.

When the fan-out wiring structure is applied, the panel is bonded and connected with the second bonding pad area B' of the IC through the fan-out wiring, the fan-out wiring of the panel is gradually gathered to the side of the drive IC from the side of the display panel, and the width of the fan-out wiring is gradually reduced, as shown in FIG. 4. For example, for an LTPS display panel, the number of source lines and Rx lines is approximately 1656, so when the second pad region B' is disposed, it is usually necessary to dispose 2 to 4 rows of first output pad array lines, and the number of first output pads is typically 1656; the number of the second output bonding pads in the third bonding pad area is generally 20-25.

The first bonding pad area A 'is connected with the bonding area of the FPC 300' through a fan-out wire, and the fan-out wire is fanned out from the side of the driver IC100 'to the side of the FPC 300' to form a trapezoid wire which is changed from small to large. For example, the total number of input pads is 700-.

If the Pitch (Pitch) of the FPC300 ' is not limited in the process, the width of the FPC300 ' is simply narrowed, which inevitably causes the difference between the Pitch of the bonding area of the IC100 ', and at this time, the diagonal angle of the fan-out trace of the panel is increased, the line width is narrowed, which brings the disadvantages of the increase of the distance between the IC100 ' and the FPC300 ' and the increase of the trace impedance, which contradict the narrowing of the lower frame.

Referring to fig. 5 in detail, the present application provides a display substrate, which includes a display area and a non-display area located at the periphery of the display area, wherein the display substrate includes an input end 10 and two output ends 20 located in the non-display area;

the two output ends 20 are respectively arranged at two sides of the input end 10;

the input end 10 comprises a first pad area a, a plurality of input pads 1 are arranged on the first pad area a, and the two output ends 20 both comprise a first pad area B and a third pad area C; a plurality of first output bonding pads 2 are arranged on the first bonding pad area B; a plurality of second output pads 3 are disposed on the third pad region C.

In the embodiment of the present application, the input pad 1 is used for connecting with a flexible circuit board FPC300 and providing an input signal through the flexible circuit board FPC 300; the first output pad 2 is used for connecting with the display panel 400 and providing a first driving signal to the display panel 400;

the second output pad 3 is used for connecting with a GOA cell of the display panel 400 and providing a second driving signal to the GOA cell.

In this application embodiment, through setting up input 10 at driver IC's intermediate position, set up output 20 into two parts, these two parts are located the both sides of input 10 respectively, and each output 20 is used for walking the line with the fan-out that display panel 400 corresponds one side and is connected, when realizing the frame of narrowing, avoids fan-out to walk the increase of oblique angle and the problem of line width narrowing. It should be noted that, in the embodiment of the present application, the display substrate 100 is exemplarily disposed on the lower frame of the display panel 400, but the embodiment of the present application is not limited thereto, and the display substrate 100 may be disposed on the upper frame, the left frame, or the right frame of the display panel 400. In addition, the total number of the pads on each pad area is not limited in the embodiment of the present application, and in different embodiments, different settings may be performed depending on different devices and application scenarios.

In addition, in the embodiment of the present application, "a first direction X" and "a second direction Y" are defined to correspond to one edge direction of the display area, and are parallel to a critical line of the display area and the non-display area, and the first direction X is perpendicular to the second direction Y. In the present application, the first direction X is taken as a transverse direction of the display area, and the second direction Y is taken as a longitudinal direction of the display area. The narrowing of the lower frame in the application can be the narrowing in a single longitudinal direction or the narrowing in a single transverse direction, and can also be the narrowing in the longitudinal direction and the transverse direction simultaneously. This is not limited in the embodiments of the present application, and in different embodiments, the adjustment is performed according to the narrowing requirement.

Example one

As shown in fig. 6, in the embodiment of the present application, the lower edge of the first pad area a is as close as possible to the lower edge of the display substrate 100, and when the number of pads is large, the pad array extends from the lower edge to the upper edge of the display substrate 100 and is arranged in an array, so that the lower frame of the display device is longitudinally narrowed. In the embodiment of the present application, the lower edge of the display substrate 100 is defined as the edge near the FPC300, and the upper edge of the display substrate 100 is defined as the edge near the display panel 400. The first pad area a is electrically connected to the chip on film COF200 through the input trace 8.

Fig. 7 shows a bonding method between a display substrate 100 'and an FPC 300' in a conventional COG, where an IC input pad 1 'is arranged with an equal width and is connected to a bonding pin of the FPC through an increasing input trace 8', and in terms of design and process, impedance between the IC input pad 1 'and the bonding pin of the FPC 300' needs to satisfy a certain condition, such as < 5 Ω to 10 Ω, otherwise transmission efficiency will be affected. In some embodiments, multiple pads are used for the same signal and are connected together through a routing to achieve the purpose of reducing impedance, but the fan-out routing mode is not favorable for reducing the frame.

In the embodiment of the present application, as shown in fig. 8, the input pads 1 are arranged in an array along a first direction X in the first pad area a, and widths of the plurality of input pads 1 are different.

It should be noted that the bonding impedance between the input pad 1 and the bonding pin of the FPC300 accounts for more than 60-70% of the total impedance, and therefore, when the widths of the pads are set, the total area of the pad corresponding to each signal needs to be kept close to the total area of the pad corresponding to a plurality of signals in the prior art. Therefore, when setting, it is possible to adopt a manner of setting a plurality of rows of input pads 1 with the same width, as shown at the position (I) in fig. 8, and a manner of setting a plurality of rows of input pads 1 with different widths, as shown at the position (II) in fig. 8, and to perform selective setting on the basis of satisfying the bonding impedance requirement.

In order to realize that the number of the bonding pads or the pins on the bonding area of the first bonding pad area A and the FPC300 corresponds, the number of the input bonding pads 1 is required to be close to the total number of the FPC300 Pin, in the embodiment of the application, when the input bonding pads are arranged, the input bonding pads 1 are arranged in a multi-row array mode on the first bonding pad area A along the second direction Y, and are located in the same row of the input signals of the input bonding pads 1 are identical.

It should be noted that, in the embodiment of the present application, a schematic structural diagram is shown in which a row of pads is added above a pad corresponding to the same signal, and when the specific arrangement is performed, two or three rows may also be provided. For example, after the input pads 1 are adjusted on the first pad area a, the total number of input pads 1 forming 800 in total of 700 and 800 forms 250-300 corresponding FPC300 total pins.

In this embodiment of the present application, the first pad regions B are disposed at the left and right sides of the first pad region a, so that the longitudinal reduction of the display substrate 100 can be achieved, the display panel 400 includes a first display region and a second display region disposed along a first direction, and the first pad regions B are electrically connected to the first display region located at the same side through the first routing lines 4; the first pad area B is electrically connected to the second display area located on the same side through a second routing wire 5.

In order to reduce the lower frame, the lower edge of the first pad area B is located as close as possible to the lower edge of the display substrate 100, and when the number of pads is large, the pad array is arranged to extend from the lower edge to the upper edge of the display substrate 100, as shown in fig. 9, so that a narrow frame of the display device can be realized. Preferably, the lower edge of the first pad region B is flush with the lower edge of the first pad region a.

The first pad area B is used for connecting a touch trace and/or a source trace, and the first output pads 2 are arranged in an array along a first direction X on the first pad area B. In this embodiment, the display substrate 100 may be a single touch driving IC or a single data driving IC, which is not limited in this embodiment, and in different embodiments, different setting manners may be adopted.

The longitudinal width of the display substrate 100 is reduced by disposing the first pad regions B at both sides of the first pad region a, but for the LTPS, due to factors such as resolution, for example, approximately 1656 lines in total for source lines and Touch Rx lines, in order to further reduce the lateral width, the first output pads 2 are arranged in a multi-row array on the first pad region B.

In the embodiment of the present application, the number of pad rows on the first pad area B may be adjusted according to different devices or application scenarios. Can be two rows and also can be 3-5 rows. For example, when the total number of the existing signal lines (e.g., 1656 or more) is kept constant, the number of the lines is adjusted to 3-5 lines, 828 pads can be distributed on the left side and the right side respectively, and the size of the pad and the Pitch can be kept constant.

It should be noted that, in the preferred embodiment of the present application, the number of the first output pads 2 in each row is the same. But for different layouts, for example odd and even rows, it can be adjusted according to the number of pads so that the first output pads 2 are approximately equal in each row.

In the embodiment of the present application, there is also provided an arrangement manner of the first output pads 2 in the first pad region B, and the first output pads 2 between two adjacent pad rows are arranged in a staggered array, as shown in fig. 10 to 11. Fig. 10 shows a schematic diagram of routing of the first output pads 2 arranged in two rows, and fig. 11 shows a schematic diagram of routing of the first output pads 2 arranged in three rows, where the pads in each row are staggered to facilitate routing of Panel, and if the width of the routing is not enough, the distance between the pads can be increased appropriately. Certainly, in other embodiments, the Panel trace may adopt a Gate, SD, ITO multilayer trace, so as to reduce trace impedance and reduce trace area. This is not limited in the embodiments of the present application.

In an embodiment of the present application, two of the second pad regions are symmetrically disposed with respect to the first pad region, and/or two of the third pad regions are symmetrically disposed with respect to the first pad region. The third pad region C is located on a side of the first pad region B away from the first pad region a, and the second output pads 3 are arranged in an array along the first direction X on the third pad region C. In order to reduce the lower bezel, the lower edge of the third pad region C is flush with the lower edge of the first pad region B.

The number of the second output pads 3 corresponds to the number of the GOA units of the display panel 400, and the second output pads 3 located on the third pad area C of the display substrate 100 are connected to the GOA units on the same side by the GOA traces. It should be noted that, in different embodiments, different numbers of second output pads 3 may be provided according to different driving manners of the GOA unit, for example, for an LTPS display device, the number of second output pads 3 on the third pad region C on a single side is 20 to 25.

When setting, the second output pads 3 may be arranged in a plurality of rows on the third pad region C according to the difference of the number of the GOA units and the reduction scheme. In the embodiment of the present application, the number of pad rows on the first pad area B may be adjusted according to different devices or application scenarios, for example, two pad rows are disposed on the third pad area C.

In addition, as shown in fig. 9, the display substrate 100 is provided with a redundant pad area F on a side of the output end 20 close to the display area, and a plurality of redundant pads 9 are arranged on the redundant pad area F in an array manner. For the IC with the longitudinal height ratio IC longitudinal width of the first pad area B being less than 0.15mm, a plurality of compensation redundant pads 9 can be designed on the upper edge of the IC for supporting the upper edge of the IC in order to avoid the bonding undervoltage hidden trouble caused by no pad above the first output pad 2.

It should be noted that the arrangement position of the redundant pads 9 is not limited in the embodiment of the present application, in some embodiments, the redundant pad region F may be located at a position corresponding to the first pad region B, and may also extend from the first pad region B to the outer third pad region C, and the number of the redundant pads 9 and the inter-pad spacing are not limited.

After the redundant pad 9 is arranged, the source wire and the touch wire need to avoid the redundant pad 9, as shown in fig. 12, so that the lower frame is increased by about 0.065mm in the design. In a specific application, the position, shape, and the like of the redundant pad 9 may be determined according to the height from the first pad region B to the edge of the IC, which is not limited in the present application.

In the embodiment of the present application, by adjusting the height of the pad and the number of array lines, the first pad region a and the second pad region B (which may include the redundant pad region F) may be arranged in parallel at the same level, and fig. 13 shows a schematic diagram of a narrowing dimension of a lower frame in a conventional scheme, where a0 is a distance from a side edge of the driver IC to a side frame of the display panel 400, B0 is a longitudinal height of a fan-out routing region of the panel, h0 is a longitudinal height of the driver IC, and fig. 14 shows a schematic diagram of a narrowing dimension of a lower frame of a display device in an embodiment of the present application. The technical scheme of the application realizes narrowing of the longitudinal height of the IC from h0 to h 1. Secondly, the lateral width of the IC is reduced, wherein the distance between the leftmost or rightmost side edge of the driving IC and the side frame of the display panel 400 is narrowed from a0 to a1, so that the longitudinal height of the fan-out line area can be narrowed from b0 to b 1.

For example, when a0 is narrowed to a1 is narrowed to 17.5mm, b0 is narrowed to b1 is narrowed to 1.13mm, and the frame is narrowed to 0.2 mm. The vertical contractible frame is more than 0.35mm, and the maximum contractible frame is more than 0.4mm when no redundant bonding pad 9 exists. Therefore, the technical scheme of the application is comprehensively narrowed by 0.55-0.6 mm. Meanwhile, the transverse width of the FPC300 can be narrowed from the conventional 36mm to be within 20 mm.

It should be noted that, when designing the frame narrowing, the process needs to be considered comprehensively, and if the vertical width of the IC cannot be reduced, the process capability can be considered to be improved, for example, the vertical width is increased from 70-80nm to 30-40nm, so that more transistors and processing units can be placed. Under the condition of narrowing the vertical height of the IC, the transverse length of the IC can be properly widened, and the area of the IC is kept unchanged. For example, each pad area adopts a row of pad rows arranged in an array, the height of the IC can be narrowed to about 0.5-0.6 nm, and the redundant pad 9 does not need to be designed on the upper edge of the IC. In specific application, the selection is performed according to different devices and application scenes.

Example two

In the embodiment of the present application, in order to further reduce the frame, the position of the third pad region C may be further adjusted. When the device is applied, the selection can be carried out according to different application scenes or different devices.

In an embodiment of the present application, as shown in fig. 15, the third pad region C is located at a side of the first pad region B away from the first pad region a, and the third pad region C is disposed at a side of the display substrate 100 away from the display panel 400. Preferably, the lower edge of the third pad region C is flush with the lower edge of the first pad region B. The second output pads 3 are arranged in an array along the first direction X on the third pad region C. The second output pad 3 is electrically connected to the GOA unit through a third trace 6, and the third trace 6 is connected to an upper edge of the third pad region C.

It should be noted that, in this embodiment, the third pad region C is located at the lower left and right corners of the driver IC, and the GOA routing manner is located below the panel fan-out routing region, so that the panel fan-out routing is not affected; in addition, no other circuit is arranged at the lower edge of the driving IC, and a large-fillet design, such as a circular arc outline or an oval outline display device, can be correspondingly arranged. However, this design requires the fan-out traces of the panel to be far from the side frame and to be as close as possible to the middle of the display panel 400, and the side frame of the display device is enlarged a little because the fan-out traces do not reach the edge of the IC.

In order to further optimize the side frame narrowing scheme of the display device, the position of the GOA trace may be adjusted, for example, as shown in fig. 16, the third pad region C is disposed on one side of the display substrate 100 close to the display region, the second output pad 3 is electrically connected to the GOA unit through a fourth trace 7, and the fourth trace 7 is connected to the lower edge of the third pad region C. Optimizing the GOA routing to routing from the lower edge of the third pad region C can reduce the side frame.

Of course, the third pad region C may also be disposed at the middle position of the longitudinal height of the driver IC, as shown in fig. 17, the second output pad 3 is electrically connected to the GOA unit through a third trace 6 and a fourth trace 7, one of the third trace 6 and the fourth trace 7 is connected to the upper edge of the third pad region C, and the other is connected to the lower edge of the third pad region C. For example, the third routing line 6 is electrically connected to the upper edge of the third pad region C, and the fourth routing line 7 is electrically connected to the lower edge of the third pad region C.

It should be noted that, in the embodiment of the present application, a routing manner of the GOA unit is not limited, and in different embodiments, different settings may be performed according to different devices or application scenarios. In addition, for the case where the number of the second output pads 3 is large, a multi-row pad row array arrangement, for example, two rows, may be employed. When two rows are provided, it may be adopted that the pad rows near the side of the display panel 400 are connected by the third trace 6, and the pad rows far from the side of the display panel 400 are connected by the fourth trace 7.

In one embodiment of the present application, as shown in fig. 18, the first output pads 2 include a plurality of pad rows arranged in an array along the second direction Y on the first pad region B, the pad rows include a first pad row 11 and at least one second pad row 12, the first pad row 11 is disposed at a side away from the display panel 400, and the number of the first output pads 2 on the first pad row 11 is smaller than the number of the first output pads 2 on the second pad row 12. Wherein the third pad region C is positioned flush with the first pad row 11 in the second direction.

In this embodiment, the layout of the first output pads 2 on the first pad area B is optimized simultaneously, so that the first pad row 11 and the third pad area C correspond to the position of the second pad row 12 as much as possible, and preferably, the areas where the third pad area C and the first pad row 11 are located correspond to the two side edges of the area where the second pad row 12 is located. Bonding imbalance is prevented by balancing the layout of the pads.

When set, the third pad region C is located on the side of the first pad row 11 close to the first pad region a, as shown in fig. 18; for the GOA routing manner, the second output pad 3 may be electrically connected to the GOA unit through a fourth routing 7, and the fourth routing 7 is connected to the lower edge of the third pad region C. Alternatively, the third pad region C is located on a side of the first pad row 11 away from the first pad region a, as shown in fig. 19. The second output pad 3 is electrically connected to the GOA unit through a third trace 6 and a fourth trace 7, one of the third trace 6 and the fourth trace 7 is connected to the upper edge of the third pad region C, and the other is connected to the lower edge of the third pad region C.

Still further, the scheme shown in fig. 20 may also be adopted, in this embodiment, it is combined that the second pad region in the existing scheme is disposed on the side of the display substrate close to the display panel, in order to further narrow the size of the lower bezel compared to the existing scheme, a row of first output pad rows may be disposed along the side of the display substrate close to the display panel, the row may cover both the first pad region a and the second pad region B, and the remaining first output pads may be disposed in the second pad regions B distributed on both sides.

It should be noted that, in the embodiment of the present application, multiple schemes are provided for the setting manner of the third pad region C, and in specific application, different schemes may be adopted to reduce the lower frame of the display device according to different devices or different application scenarios.

EXAMPLE III

With continued reference to fig. 5-6, the present application provides a display device including the display substrate 100 as described in any one of the above.

The display substrate provided in the embodiment of the present application may be applied to a COF scheme and may also be applied to a COG scheme, which is not limited in the present application. In the embodiment of the present application, the narrowing of the physical width of the driving IC is achieved by adjusting the position and number of the pads on the display substrate 100, and the narrowing of the total width of the IC input pad 1 area is achieved at the same time. In order to realize the scheme of narrow frame and at the same time, the size of the FPC300 needs to be reduced, in this application, the chip on film COF200(COF200) is used as the switching between the driver IC and the FPC300, and is bonded to the driver IC at one end and the FPC300 at the other end, so as to narrow the lateral width of the bonding area. The scheme occupies smaller module appearance space, improves the occupation ratio of the whole screen, and is more suitable for special-shaped LCD module structures, particularly round, oval and other whole appearance structures.

For example, for the COF technology, the display device further includes a Chip On Film (COF), the chip on film includes a flexible circuit board and a driving IC disposed on the flexible circuit board, and the first pad area a is electrically connected to the COF200 through an input trace 8; a first bonding area D bonded to the input trace 8 is disposed on the chip on film COF200, and first pins corresponding to the input pads 1 one to one are disposed on the first bonding area D; the chip on film COF200 is further provided with a second bonding area E bonded to the flexible circuit board FPC300, and the second bonding area E is provided with second pins corresponding to the first pins one to one, as shown in fig. 21.

In the embodiment of the present application, the input pad 1 with a non-uniform width is used in the first pad area a, and when the input trace 8 is disposed, the trace manner used is the same width as the pad, as shown in fig. 22. Accordingly, the first pins of the first bonding region D on the COF200 may be in one-to-one correspondence with the input pads 1 on the first pad region a, narrowing the first pad region a of the driving IC while narrowing the first bonding region D.

Through simulation calculation and optimization, the input pad 1 of the IC and the pins (pins) on the COF200 can be nearly equal in width, the width is narrowed from the conventional 36mm width to be within 20mm of the new scheme, and the number of the pins of the COF200 is reduced from 320 to 260.

And a third bonding area matched with the second bonding area E is arranged on the flexible circuit board FPC300, and third pins in one-to-one correspondence with the second pins are arranged on the third bonding area. The first Pin of the first bonding area D, the second Pin of the second bonding area E, and the Pin of the third bonding area are in the same sequence, that is, the signals of the pins in the corresponding positions are the same.

The second bonding area E and the third bonding area are as wide as possible. The pin pitch of the conventional bonding area is 44 μm, the width is 24 μm, and for the 44 μm process pitch control, the conventional 0.12mm FPC300 cannot correspond to the pin pitch control, a COF Film process with higher precision is required, generally 26 μm, and the 44 μm process requirements can be better compatible.

On the COF200, the upper end is a first bonding area D, and the pin pitch of the first bonding area D is 44 μm, which is close to the pad pitch of the first pad area A of the driving IC end. The trace on the COF200 is gradually widened from 24 μm to about 70 μm from the upper end to the lower end, the pitch of the trace at the bottom is about 120 μm, and the pin pitch of the second bonding area E is about 120 μm. When the COF Film is arranged, the longitudinal height of the COF200 is as small as possible, wiring impedance is reduced, and the lower end of the COF Film is bonded with the FPC300 to realize physical connection.

However, in the solution provided in the present application, the COFFilm width can be narrowed from 35.8mm to 17mm of the conventional FPC300 solution, which is a half width. Therefore, the frame narrowing scheme provided by the embodiment of the application can be better suitable for large-fillet equipment. For example, a display device having a circular or elliptical shape.

For example, for the COG technology, the display device further includes a driver IC bonded to the display substrate, the driver IC is provided with a fourth bonding area matched with the first bonding pad area, and the fourth bonding area is provided with fourth pins corresponding to the input bonding pads one to one. The setting of the fourth bonding area is the same as the setting of the bonding area of the chip on film in the embodiment of the present application, and details are not described herein again.

In the embodiment of the present application, four corners of the display device are rounded, as shown in fig. 2. For example, the fillet radius of the non-display area of the display panel 400 is 18mm to 26 mm; the lower frame is 2.9 mm-2.35 mm. The transverse width of the first bonding area D is 36-20 mm.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Terms such as "disposed" and the like, as used herein, may refer to one element being directly attached to another element or one element being attached to another element through intervening elements. Features described herein in one embodiment may be applied to another embodiment, either alone or in combination with other features, unless the feature is otherwise inapplicable or otherwise stated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the scope of the described embodiments. It will be appreciated by those skilled in the art that many variations and modifications may be made to the teachings of the invention, which fall within the scope of the invention as claimed.

Claims

1. A display substrate is characterized by comprising a display area and a non-display area positioned at the periphery of the display area, wherein the display substrate comprises an input end and two output ends positioned in the non-display area;

the two output ends are respectively arranged at two sides of the input end;

2. The display substrate of claim 1, wherein the input pad is configured to connect to a flexible circuit board and provide an input signal through the flexible circuit board;

3. The display substrate according to claim 1, wherein the input pads are arranged in an array along a first direction in the first pad region, widths of the plurality of input pads are different, and the first direction is parallel to a critical line of the display region and the non-display region.

4. The display substrate of claim 1, wherein the input pads are arranged in a plurality of rows and arrays on the first pad region, and input signals of the input pads located in a same column are the same.

5. The display substrate of claim 1, wherein two of the second pad regions are symmetrically disposed with respect to the first pad region, and/or two of the third pad regions are symmetrically disposed with respect to the first pad region.

6. The display substrate according to claim 1, wherein the second pad region is used for connecting a touch trace and/or a source trace, and the first output pads are arranged in an array along a first direction on the second pad region.

7. The display substrate according to claim 3, wherein the display area comprises a first display area and a second display area arranged along a first direction, and the second pad area is electrically connected to the first display area located on the same side through a first trace; the second pad area is electrically connected with the second display area located on the same side through a second routing wire.

8. The display substrate of claim 4, wherein the first output pads are arranged in a plurality of rows on the second pad region, and wherein the number of the first output pads in each row is the same.

9. The display substrate according to claim 4, wherein the first output pads comprise a plurality of pad rows arrayed in the second direction on the second pad region, the pad rows comprise a first pad row and at least one second pad row, the first pad row is disposed on a side away from the display region, and the number of the first output pads on the first pad row is smaller than the number of the first output pads on the second pad row.

10. The display substrate of claim 8 or 9, wherein the first output pads between two adjacent pad rows are arranged in a staggered array.

11. The display substrate according to claim 2, wherein the third pad region is located on a side of the second pad region away from the first pad region, and the second output pads are arrayed in the first direction on the third pad region.

12. The display substrate of claim 11, wherein the lower edge of the third pad region is flush with the lower edge of the second pad region.

13. The display substrate according to claim 9, wherein the third pad region is flush with the first pad row in position along a second direction, and a region where the third pad region and the first pad row are located corresponds to two side edges of a region where the second pad row is located.

14. The display substrate according to claim 11, wherein the third pad region is located on a side of the first pad row near the first pad region; or, the third pad region is located on a side of the first pad row away from the first pad region.

15. The display substrate according to claim 11, wherein the third pad region is disposed on a side of the display substrate away from the display region, the second output pad is electrically connected to the GOA unit through a third trace, and the third trace is connected to an upper edge of the third pad region.

16. The display substrate according to claim 11, wherein the third pad region is disposed on a side of the display substrate close to the display region, the second output pad is electrically connected to the GOA unit through a fourth trace, and the fourth trace is connected to a lower edge of the third pad region.

17. The display substrate according to claim 11, wherein the second output pad is electrically connected to the GOA unit through a third trace and a fourth trace; one of the third wire and the fourth wire is connected with the upper edge of the third bonding pad area, and the other one of the third wire and the fourth wire is connected with the lower edge of the third bonding pad area.

18. The display substrate of claim 1, wherein the display substrate is provided with a redundant pad area on a side of the output end close to the display area, and a plurality of redundant pads are arrayed on the redundant pad area.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. The display device according to claim 19, further comprising a chip on film, the chip on film comprising a flexible circuit board and a driving IC disposed on the flexible circuit board, the first pad area being electrically connected to the chip on film through input traces;

21. The display device according to claim 20, wherein a third bonding area is disposed on the flexible circuit board, and the third bonding area is engaged with the second bonding area, and a third pin corresponding to the second pin is disposed on the third bonding area.

22. The display device according to claim 19, further comprising a driving IC bonded to the display substrate, wherein a fourth bonding region is disposed on the driving IC, and the fourth bonding region is engaged with the first bonding pad region, and the fourth bonding region has fourth pins corresponding to the input bonding pads one to one.