CN112514543A - Laminate and method for producing same - Google Patents
Laminate and method for producing same Download PDFInfo
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- CN112514543A CN112514543A CN201880095957.5A CN201880095957A CN112514543A CN 112514543 A CN112514543 A CN 112514543A CN 201880095957 A CN201880095957 A CN 201880095957A CN 112514543 A CN112514543 A CN 112514543A
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- electroless plating
- plating layer
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Chemically Coating (AREA)
Abstract
A method for manufacturing a laminated body (60a), wherein a base body comprises: a substrate (10) having an electrode layer (12) on a main surface (10 a); an electroless plating layer (20) which is disposed at least on the electrode layer (12); and an insulating layer (32) which is disposed on the base material (10) and has an opening (32a) through which a plating layer including the electroless plating layer (20) is exposed, wherein the method for manufacturing the laminate comprises: and a bump forming step of forming a metal bump (50) in contact with the plating layer in the opening (32a) by subjecting the base body to electrolytic plating.
Description
Technical Field
The present invention relates to a laminate capable of mounting a semiconductor element and a method for manufacturing the same.
Background
With the miniaturization, thinning, and densification of electronic components, there is an increasing demand for miniaturization, thinning, and densification of module substrates for mounting semiconductor elements to obtain electronic components. In order to meet such a demand, it is important to mount a semiconductor element on a narrow mounting surface. From such a viewpoint, for example, patent document 1 listed below discloses a module substrate having a space (cavity) for housing a semiconductor element.
Prior art documents
Patent document
Patent document 1: japanese patent laid-open publication No. 2015-60912
Disclosure of Invention
Technical problem to be solved by the invention
In some cases, another module board or electronic component is connected to a module board having a space for incorporating a semiconductor element, and it is conceivable to form a metal bump for connection to the other module board or electronic component on a base material and to incorporate a semiconductor element in a position on the base material different from the formation position of the metal bump. Here, when forming a metal bump on a substrate, a method of forming a metal bump in an opening by plating after forming an insulating layer having the opening on the substrate is considered. In this case, if a thick metal layer (for example, copper foil) is used as the plated power supply layer, the step of removing the power supply layer may be complicated when it is necessary to remove the power supply layer from the viewpoint of suppressing the occurrence of disturbance or the like after the metal bump is formed. Therefore, a method for easily obtaining a laminate that can be used as a module substrate for mounting a semiconductor element is required.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a laminate body capable of easily obtaining a laminate body capable of mounting a semiconductor element. It is another object of the present invention to provide a laminate obtained by the above production method.
Means for solving the technical problem
In one aspect of the method for producing a laminate according to the present invention, the base includes: a substrate having an electrode layer on a surface thereof; an electroless plating layer at least disposed on the electrode layer; and an insulating layer disposed on the base material and having an opening through which a plating layer including the electroless plating layer is exposed, the method for manufacturing the laminate including: and a bump forming step of forming a metal bump in contact with the plating layer in the opening by performing electrolytic plating on the base.
According to the method for manufacturing a laminate, a plating layer including an electroless plating layer can be used as a power supply layer for forming the metal bump. In addition, when it is necessary to remove the power supply layer from the viewpoint of suppressing the occurrence of disturbance or the like after the metal bump is formed, the plating layer including the relatively thin electroless plating layer can be easily removed, and thus a laminate body on which the semiconductor element can be mounted can be easily obtained. Further, according to the method for producing a laminate, it is not necessary to form the power supply layer after forming the insulating layer on the base material, and it is possible to suppress the complexity of the production process of the laminate on which the semiconductor element can be mounted. Further, according to the laminate obtained by the above-described method for manufacturing a laminate, since the semiconductor element can be built in (three-dimensionally mounted) at a position on the base material different from the position where the metal bump is formed, and can be connected to another semiconductor element, a module board, or an electronic component via the metal bump, it is possible to realize miniaturization, thinning, or densification of the electronic component including the semiconductor element.
In the method for manufacturing a laminate according to the present invention, the step of forming an opening in an insulator disposed on the substrate to obtain the insulating layer may be further provided before the bump forming step.
In the method for manufacturing a laminate according to the present invention, the method may further include an electroless plating layer forming step of forming the electroless plating layer by performing electroless plating on the electrode layer before the bump forming step. In the method for producing a laminate according to the present invention, the step of forming a protective layer having an opening through which the electrode layer is exposed on the base material may be further provided before the step of forming the electroless plating layer.
In the method for manufacturing a laminate according to the present invention, an insulating layer removing step of removing the insulating layer may be further provided after the bump forming step. In the method for manufacturing a laminate according to the present invention, the step of removing the portion of the electroless plating layer disposed at a position different from the position where the metal bump is formed may be further provided after the step of removing the insulating layer. In the method for manufacturing a laminate according to the present invention, the step of forming a protective layer covering the electrode layer may be further provided after the step of removing the insulating layer.
In one aspect of the method for producing a laminate according to the present invention, the electroless-plated layer may be exposed through the opening of the insulating layer.
One aspect of the laminate according to the present invention includes: a substrate having an electrode layer on a surface thereof; an electroless plating layer at least disposed on the electrode layer; and a metal bump which is in contact with a plating layer including the electroless plating layer on the electroless plating layer.
According to such a laminate, the semiconductor element can be built in (three-dimensionally mounted) at a position on the base material different from the position where the metal bump is formed, and the laminate can be connected to another semiconductor element, a module board, or an electronic component via the metal bump.
In one aspect of the laminate according to the present invention, the metal bump may be in contact with an electroless plating layer.
In the laminate and the method for manufacturing the same according to the aspect of the present invention, the electrode layer may be a circuit pattern. The length of the metal bump in the stacking direction of the electrode layer and the electroless plating layer may be 10 μm or more and may exceed 150 μm. The electrode layer and the electroless-plated layer may not be adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material, or may be adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer.
Effects of the invention
According to the present invention, a method for manufacturing a laminate body capable of easily obtaining a laminate body capable of mounting a semiconductor element can be provided. Further, according to the present invention, a laminate obtained by such a production method can be provided.
Drawings
Fig. 1 is a schematic cross-sectional view for explaining an example of a method for producing a laminate.
Fig. 2 is a schematic cross-sectional view for explaining an example of the method of manufacturing the laminate.
Fig. 3 is a schematic cross-sectional view for explaining an example of the method of manufacturing the laminate.
Fig. 4 is a schematic cross-sectional view for explaining an example of the method of manufacturing the laminate.
Fig. 5 is a schematic cross-sectional view for explaining another example of the method of manufacturing the laminate.
Fig. 6 is a schematic cross-sectional view for explaining another example of the method of manufacturing the laminate.
Fig. 7 is a schematic cross-sectional view for explaining another example of the method of manufacturing the laminate.
Fig. 8 is a schematic cross-sectional view for explaining another example of the method of manufacturing the laminate.
Detailed Description
In the present specification, the numerical range shown by the term "to" indicates a range in which the numerical values before and after the term "to" are included as the minimum value and the maximum value, respectively. In the numerical ranges recited in the present specification, the upper limit or the lower limit of a numerical range in one stage may be replaced with the upper limit or the lower limit of a numerical range in another stage. "a or B" may include either a or B, and may include both.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings as appropriate. However, the present invention is not limited to the following embodiments. The sizes of the components in the drawings are conceptual, and the relative relationship between the sizes of the components is not limited to the relationship shown in the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals, and redundant description is omitted.
In the method for manufacturing a laminate according to the present embodiment, the base includes: a substrate having an electrode layer on a surface thereof; an electroless plating layer at least disposed on the electrode layer; and an insulating layer (1 st insulating layer) disposed on the base material and having an opening through which a plating layer including the electroless plating layer is exposed, the method for manufacturing the laminate including: and a bump forming step of forming a metal bump in contact with the plating layer in the opening by performing electrolytic plating on the base. The laminate according to the present embodiment can be obtained by the method for producing a laminate according to the present embodiment. The laminate according to the present embodiment includes: a substrate having an electrode layer on a surface thereof; an electroless plating layer at least disposed on the electrode layer; and a metal bump which is in contact with a plating layer including the electroless plating layer on the electroless plating layer.
The laminate according to the present embodiment can be used as a module substrate for mounting a semiconductor element. The laminate according to the present embodiment has a space for mounting a semiconductor element at a position on the base material different from the position where the metal bump is formed. The laminate according to the present embodiment includes a plating layer including an electroless plating layer and a metal bump, and can be confirmed by the crystalline state of the constituent materials of these members, for example, by a metal microscope. As the electrode layer, for example, a circuit pattern can be used. The laminate according to the present embodiment may be formed as follows: the semiconductor device further comprises an insulating layer which is arranged on the substrate and is provided with an opening, and the metal bump is arranged in the opening.
The plating layer may include an electroless plating layer, and the outermost layer of the plating layer may not be formed of an electroless plating layer. That is, the plating layer may be formed of, for example, an electroless plating layer, or may be formed of an electroless plating layer and an electrolytic plating layer disposed on the electroless plating layer. The thickness of the electrolytic plating layer disposed on the electroless plating layer is, for example, 1 to 5 μm. In the laminate according to the present embodiment, the metal bump may be in contact with the electroless-plated layer, or may be in contact with an electrolytic-plated layer disposed on the electroless-plated layer. The electroless-plated layer may be exposed through the opening of the insulating layer, and the electrolytic-plated layer disposed on the electroless-plated layer may be exposed through the opening of the insulating layer.
The method of manufacturing a laminate according to the present embodiment may include a base material preparation step, a plating layer formation step, or an insulating layer formation step before the bump formation step, and for example, may include the base material preparation step, the plating layer formation step, and the insulating layer formation step in this order before the bump formation step. In the substrate preparation step, a substrate having an electrode layer on a surface thereof is prepared. The plating layer forming step may include an electroless plating layer forming step of forming an electroless plating layer by performing electroless plating on the electrode layer disposed on the surface of the base material, or may include an electrolytic plating layer forming step of forming an electrolytic plating layer by performing electrolytic plating on the electroless plating layer formed in the electroless plating layer forming step. When the plating layer is formed of an electroless plating layer, the electroless plating layer forming step can be performed as the plating layer forming step. In the insulating layer forming step, an opening is formed in an insulator disposed on a substrate to obtain an insulating layer.
The method for manufacturing a laminate according to the present embodiment may include an insulating layer removing step of removing the insulating layer formed in the insulating layer forming step after the bump forming step.
The method for manufacturing a laminate according to the present embodiment may include a plating layer removing step of removing a portion of the plating layer, which is disposed at a position different from a position where the metal bump is formed, after the insulating layer removing step. By removing a part of the plating layer, the interference caused by the plating layer is easily suppressed. In the case where the plating layer has an electroless plating layer and an electrolytic plating layer disposed on the electroless plating layer, the plating layer removing step may include an electrolytic plating layer removing step of removing a portion disposed at a position different from a position where the metal bump is formed in the electrolytic plating layer, or may include an electroless plating layer removing step of removing a portion disposed at a position different from a position where the metal bump is formed in the electroless plating layer. The electrolytic plating layer removing step and the electroless plating layer removing step may be performed separately or simultaneously. That is, the electroless plating layer may be removed after the electrolytic plating layer is removed, or may be removed simultaneously with the electrolytic plating layer. By removing a part of the electrolytic plating layer and/or the electroless plating layer, the interference caused by these plating layers is easily suppressed. When the plating layer is formed of an electroless plating layer, the electroless plating layer removing step can be performed as the plating layer removing step. The electroless plating layer may have a 1 st portion (exposed portion, portion not covered by the insulating layer before the insulating layer removing step) arranged at a position where the metal bump is formed (a position where the metal bump is formed in a direction orthogonal to a stacking direction of the electrode layer and the electroless plating layer, a contact position of the metal bump and the plating layer, the same applies hereinafter) and a 2 nd portion (unexposed portion, portion covered by the insulating layer before the insulating layer removing step) arranged at a position different from the position where the metal bump is formed, and at least a part of the 2 nd portion may be removed in the electroless plating layer removing step.
The laminate according to the present embodiment may further include a protective layer (2 nd insulating layer) covering the electrode layer. The method for manufacturing a laminate according to the present embodiment may include a protective layer forming step of forming a protective layer (2 nd insulating layer) covering the electrode layer. The protective layer forming step can be performed before the electroless plating layer forming step and/or after the insulating layer removing step. The protective layer may cover the electrode layer in a state where the protective layer is in contact with the electrode layer, and the electrode layer may be covered with a layer (for example, an electroless plating layer) disposed between the electrode layer and the protective layer.
The thickness of the electroless plating layer in the stacking direction of the electrode layer and the electroless plating layer may be in the following range. The thickness of the electroless plating layer may be 0.1 μm or more, 0.7 μm or more, 1.0 μm or more, or 2.0 μm or more, from the viewpoint of ease of power supply at the time of electrolytic plating for forming a metal bump. The thickness of the electroless plating layer may be 5.0 μm or less, 2.0 μm or less, 1.0 μm or less, or 0.7 μm or less, from the viewpoint of easily removing unnecessary electroless plating layer in the electroless plating layer removing step. From these viewpoints, the thickness of the electroless plating layer may be 0.1 to 5.0 μm.
The length (height) of the metal bump in the stacking direction of the electrode layer and the electroless-plated layer may be in the following range. From the viewpoint of easily ensuring a sufficient space for mounting a semiconductor element, the length of the metal bump may be 10 μm or more, may exceed 10 μm, may be 50 μm or more, may exceed 50 μm, may exceed 80 μm, may exceed 100 μm or more, may exceed 100 μm, may exceed 150 μm or more, may exceed 200 μm or more, and may exceed 250 μm or more. From the viewpoint of facilitating the reduction in size, the reduction in thickness, or the increase in density of electronic components, the length of the metal bump may be 500 μm or less, 250 μm or less, 200 μm or less, or 150 μm or less. From these viewpoints, the length of the metal bump may be 10 to 500 μm. The length of the metal bump may be less than 40 μm.
The length (diameter) of the metal bump in the direction orthogonal to the stacking direction of the electrode layer and the electroless plating layer may be in the following range. The length of the metal bump may be 50 μm or more, may exceed 50 μm, may be 80 μm or more, may exceed 80 μm, may exceed 100 μm or more, may exceed 150 μm, may be 200 μm or more, may exceed 200 μm, and may be 250 μm or more, from the viewpoint of facilitating the formation of the metal bump (for example, facilitating the penetration of a plating solution, which will be described later, into an opening of an insulating layer) and from the viewpoint of suppressing the variation in the height of the metal bump. From the viewpoint of facilitating the miniaturization and high-density realization of electronic components by facilitating the arrangement of a plurality of metal bumps at high density, the length of the metal bump may be 500 μm or less, 250 μm or less, or 200 μm or less. From these viewpoints, the length of the metal bump may be 50 to 500 μm.
The length (thickness) of the insulating layer and the length of the opening of the insulating layer in the stacking direction of the electrode layer and the electroless-plated layer may be in the following ranges. From the viewpoint of easily ensuring a sufficient space for mounting a semiconductor element, the length of the insulating layer and the opening may be 10 μm or more, may exceed 10 μm, may be 50 μm or more, may exceed 50 μm, may exceed 80 μm, may exceed 100 μm or more, may exceed 100 μm, may exceed 150 μm or more, may exceed 150 μm, may exceed 200 μm, may exceed 250 μm or more. From the viewpoint of facilitating the reduction in size, reduction in thickness, or increase in density of electronic components, the length of the insulating layer and the opening may be 500 μm or less, 250 μm or less, 200 μm or less, or 150 μm or less. From these viewpoints, the length of the insulating layer and the opening may be 10 to 500 μm. The length of the insulating layer and the opening may be less than 40 μm.
The diameter of the opening of the insulating layer in the direction orthogonal to the stacking direction of the electrode layer and the electroless plating layer may be in the following range. The diameter of the opening may be 50 μm or more, may exceed 50 μm, may be 80 μm or more, may exceed 80 μm, may exceed 100 μm or more, may be 150 μm or more, may exceed 150 μm, may exceed 200 μm or more, and may be 250 μm or more, from the viewpoint of easy formation of the opening (e.g., easy immersion of a developer described later) and from the viewpoint of easy suppression of variation in the height of the metal bump. The diameter of the opening may be 500 μm or less, 250 μm or less, or 200 μm or less, from the viewpoint of ease of forming the opening (ease of planarizing the bottom surface of the opening), and from the viewpoint of ease of miniaturization or high density of the electronic component due to ease of disposing a plurality of metal bumps at high density. From these viewpoints, the diameter of the opening may be 50 to 500 μm.
The electrode layer and the electroless-plated layer may not be adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material. In this case, excellent adhesion between the electrode layer and the electroless plating layer can be easily obtained. In this case, the insulating layer having an opening with a diameter equal to or smaller than that of the electrode layer can be formed on the electrode layer without disposing the electrode layer in the opening of the insulating layer. In this case, in the method of manufacturing a laminate according to the present embodiment, the 1 st portion disposed at the position where the metal bump is formed in the electroless plating layer and the 2 nd portion disposed at the position different from the position where the metal bump is formed in the electroless plating layer may be adjacent to each other in the direction orthogonal to the stacking direction of the electrode layer and the electroless plating layer on the electrode layer of the base.
The electrode layer and the electroless-plated layer may be adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material. In this case, an opening for exposing the plating layer including the electroless plating layer is easily formed in the insulating layer. In this case, the insulating layer having a larger diameter than the electrode layer can be formed on the substrate by forming the electrode layer in the opening of the insulating layer. At this time, for example, the electrode layer and the electroless-plated layer may be adjacent to each other in a direction orthogonal to the lamination direction of the electrode layer and the electroless-plated layer in the surface of the base material at the formation position of the metal bump. For example, the 1 st portion disposed at the position where the metal bump is formed in the electroless plating layer and the 2 nd portion disposed at the position different from the position where the metal bump is formed in the electroless plating layer may not be adjacent to each other in the direction orthogonal to the stacking direction of the electrode layer and the electroless plating layer on the electrode layer of the base.
The electronic component according to the present embodiment includes the laminate according to the present embodiment and a semiconductor element stacked (mounted) on the laminate. The method for manufacturing an electronic component according to the present embodiment includes a semiconductor element stacking step of stacking (mounting) a semiconductor element on the laminate according to the present embodiment. The semiconductor element is laminated at a position different from a position where the metal bump is formed on the base material of the laminate. The metal bumps of the laminate in the electronic component according to the present embodiment can be electrically connected to other semiconductor elements, module boards, or electronic components.
Specific examples of the laminate, the electronic component, and the methods for producing these according to the present embodiment will be described below.
Fig. 1 to 4 are schematic cross-sectional views for explaining an example of a method for producing a laminate. In the method of manufacturing this laminate, first, as shown in fig. 1(a), in the base material preparation step, a base material (base substrate) 10 having an electrode layer 12 on a main surface (front surface) 10a is prepared. The electrode layer 12 is, for example, a circuit pattern. The substrate 10 can be used as a substrate for obtaining a laminate for mounting a semiconductor element. As the substrate, for example, a wiring board (multilayer wiring board or the like) can be used.
The electrode layers 12 are disposed on both surfaces (both main surfaces) of the substrate 10, but may be disposed on only one of the main surfaces. The substrate 10 has multiple (e.g., 2) insulating layers 14, but may have a single insulating layer. The substrate 10 has an electrode layer 16 disposed between the insulating layers 14. The electrode layer 16 is, for example, a circuit pattern. The substrate 10 may have a through electrode 18 penetrating the insulating layer 14. The 2 electrode layers 12 disposed at positions facing each other on both surfaces of the substrate 10 are connected to the electrode layer 16 via the through electrode 18, respectively, whereby these electrode layers 12 are electrically connected to each other. As the constituent material of each of the electrode layer 12, the electrode layer 16, and the through electrode 18, for example, a metal material such as copper, aluminum, nickel, tin, gold, or silver can be mentioned, and copper can be used from the viewpoint of facilitating the high-speed signal by reducing the connection resistance due to its excellent electrical conductivity. Examples of the material constituting the insulating layer 14 include Glass epoxy (Glass epoxy) and Glass polyimide. The thickness (total thickness) of the substrate 10 is, for example, 15 to 1000. mu.m. The thickness of the electrode layer 12 is, for example, 3 to 50 μm. The thickness of the insulating layer 14 is, for example, 15 to 200 μm. The thickness of the electrode layer 16 is, for example, 3 to 50 μm.
Next, as shown in fig. 1(b), in the electroless plating layer forming step, the electrode layer 12 disposed on the main surface 10a of the substrate 10 is subjected to electroless plating (for example, electroless copper plating) to form the electroless plating layer 20. The electroless plating layer 20 can be used as a power supply layer in forming a metal bump 50 (see fig. 3(a)) described later. The electroless plating layer 20 is formed on the entire or a part of the main surface of the substrate 10, functions as a power supply layer when the metal bump 50 is formed, and may be formed on the entire or a part of the electrode layer 12. The electroless plating layers 20 are formed on both surfaces of the base 10, but may be formed only on the main surface on the side where the metal bump 50 is formed (the upper side in fig. 1 (b)). The electroless plating layer 20 on the main surface on the side where the metal bump 50 is formed has a 1 st portion 20a arranged at the formation position of the metal bump 50 and a 2 nd portion 20b arranged at a position different from the formation position of the metal bump 50.
The electroless plated layer 20 can be obtained by, for example, subjecting the substrate 10 to a plating catalyst application treatment for attaching palladium, and then immersing the substrate 10 in an electroless plating solution. As a constituent material of the electroless plating layer 20, for example, a metal material such as copper, nickel, tin, gold, silver, or the like can be mentioned, and copper can be used from the viewpoint of facilitating the high-speed signal by reducing the connection resistance due to excellent electrical conductivity. The constituent materials of the electroless-plating layer 20 and the electrode layer 12 may be the same as each other.
Next, as shown in fig. 2, in the insulating layer forming step, an opening (through-hole) is formed in the insulator 30 disposed on the substrate 10 to obtain an insulating layer 32 having an opening (through-hole) 32 a. Examples of a method for forming an opening in the insulator 30 include a method of exposing and developing a photosensitive (photocurable) resin composition, a method of physically removing the resin composition with a laser, a drill, or the like. Examples of the material constituting the photosensitive resin composition include polyimide and the like. When the photosensitive resin composition is used, the insulating layer forming step includes an insulator forming step, an exposure step, and a development step in this order.
In the insulator forming step, as shown in fig. 2(a), an insulator 30 is formed on the substrate 10. The insulator 30 can be formed by transferring the insulator 30 formed on a support (not shown) in advance onto the substrate 10, coating the photosensitive resin composition on the substrate 10, and drying the coating. The thickness of the insulator 30 can also be adjusted within a desired range by transferring the insulator 30 onto the substrate 10a plurality of times.
In the exposure step, the insulator 30 is exposed to light and cured. In the case of using a positive photosensitive resin composition, a portion of the insulator 30 other than a formation position of the opening is exposed to light and cured. In the case of using the negative photosensitive resin composition, a portion of the insulator 30 where the opening is formed is exposed to light and cured. Examples of the exposure method include: a method of curing only a desired portion by irradiating light in a state where a mask is disposed on the insulator 30; a method of irradiating a pattern-like light to cure only a desired portion (a projection exposure method, a contact exposure method, a direct writing exposure method, or the like). The wavelength of the light is, for example, 350 to 450 nm. The irradiation energy of the light is, for example, 50 to 3000mJ/cm2。
In the developing step, the exposed insulator 30 is developed, and as shown in fig. 2(b), an insulating layer 32 having an opening 32a is obtained. In the developing step, the exposed portions in the case of using the positive photosensitive resin composition or the unexposed portions in the case of using the negative photosensitive resin composition are removed. Examples of the developing method include a method using an alkaline aqueous solution (e.g., an aqueous sodium carbonate solution) and a developer containing an organic solvent (e.g., cyclopentanone, γ -butyrolactone, mesitylene).
The base 40 is obtained by such an insulating layer forming process. The base 40 includes: a substrate 10 having an electrode layer 12 on a main surface 10 a; an electroless plating layer 20 disposed at least on the electrode layer 12; and an insulating layer 32 which is disposed on the base 10 and has an opening 32a through which the electroless-plated layer 20 (the plated layer formed of the electroless-plated layer 20) is exposed. The insulating layer 32 can function as an anti-plating layer in the bump forming process. The insulating layer 32 covers the 2 nd portion 20b disposed at a position different from the position where the metal bump 50 is formed in the electroless-plated layer 20. In the base body 40, the electrode layer 12 is not disposed in the opening 32a of the insulating layer 32, and the insulating layer 32 having the opening 32a smaller in diameter than the electrode layer 12 is formed on the electrode layer 12. The 1 st portion 20a disposed at the position where the metal bump 50 is formed in the electroless plating layer 20 and the 2 nd portion 20b disposed at the position different from the position where the metal bump 50 is formed in the electroless plating layer 20 are adjacent to each other in the direction orthogonal to the stacking direction of the electrode layer 12 and the electroless plating layer 20 on the electrode layer 12 of the base body 40.
Next, as shown in fig. 3 a, in the bump forming step, electrolytic plating (for example, electrolytic copper plating) is performed in the opening 32a of the insulating layer 32 in the base 40, and a metal bump (electrolytic plating layer, conductor post) 50 in contact with the electroless plating layer 20 is formed in the opening 32 a. Thus, a laminate 60a including the substrate 10, the electroless-plated layer 20, the insulating layer 32, and the metal bump 50 is obtained. The metal bump 50 is filled into the opening 32 a. The cross-sectional shapes of the metal bump 50 and the opening 32a perpendicular to the stacking direction of the electrode layer 12 and the electroless plating layer 20 include a circle, a polygon (e.g., a rectangle), and the like. As a constituent material of the metal bump 50, for example, a metal material such as copper, nickel, tin, gold, silver, or the like can be mentioned, and copper can be used from the viewpoint of facilitating the high-speed signal by reducing the connection resistance due to excellent electrical conductivity and facilitating the narrow pitch in flip chip mounting. The constituent materials of the metal bump 50 and the electroless-plated layer 20 may be the same as each other. Examples of the electrolytic plating method include a method using a copper sulfate plating solution, a copper pyrophosphate plating solution, an electrolytic nickel plating solution, and the like.
The metal bump 50 may be pressed in a length direction of the metal bump 50 after the bump forming process. Further, a polishing step of polishing the surface of the stacked body 60a (the surface of the insulating layer 32 and the front end of the metal bump 50) may be performed between the bump forming step and the subsequent insulating layer removing step. By which the length of the metal bump 50 can be adjusted.
Next, as shown in fig. 3(b), the insulating layer 32 is removed in the insulating layer removing step, thereby obtaining a stacked body 60 b. Thereby, the insulating layer 32 is entirely or partially removed, and the 2 nd portion 20b disposed at a position different from the position where the metal bump 50 is formed in the electroless-plated layer 20 is exposed. Thus, for example, the metal bump 50 which is not in contact with the insulating layer (including all the insulating layers 32) can be obtained. The insulating layer 32 can be removed, for example, by a sodium hydroxide solution. From the viewpoint of suppressing the residue of the insulating layer 32 from remaining, desmear treatment or plasma treatment may be performed after the insulating layer removing step.
Next, as shown in fig. 4 a, in the electroless plating layer removing step (plating layer removing step), at least a part of the 2 nd portion 20b, which is disposed at a position different from the formation position of the metal bump 50, of the electroless plating layer 20 on the side where the metal bump 50 is formed (upper side of fig. 4 a), is removed to obtain a stacked body 60 c. This exposes the electrode layer 12 covered with the electroless plating layer 20. The 2 nd portion 20b of the electroless-plated layer 20 can be removed by an etching process. In order to improve the insulation reliability by removing the catalyst (for example, palladium) applied to the electrode layer 12 in forming the electroless plating layer 20, the catalyst removal treatment may be performed after the etching treatment. In the electroless plating layer removing step, the entire or a part of the 2 nd portion 20b of the electroless plating layer 20 can be removed. In the electroless plating layer removing step, the electroless plating layer 20 on the side opposite to the side where the metal bump 50 is formed (the lower side in fig. 4 (a)) is removed, but the electroless plating layer 20 may not be removed.
Next, as shown in fig. 4(b), in the protective layer forming step, a protective layer (2 nd insulating layer, resist layer) 70 is formed so as to cover at least a part of the electrode layer 12. As a material constituting the protective layer 70, an insulating material can be used, and examples thereof include a solder resist material containing an epoxy resin as a main agent. The protective layer 70 can be formed by electrostatic deposition, for example. After the electrode layer 12 covered with the electroless plating layer 20 is exposed in the electroless plating layer removing step, the metal layer 72 may be formed on the surface of the electrode layer 12. After the insulating layer removing process, the metal layer 74 may be formed on the surface of the metal bump 50. The metal layers 72 and 74 can be formed by plating nickel-gold, for example. The laminate 60d can be obtained by such a protective layer forming process.
In the semiconductor element stacking step, the semiconductor element is stacked (for example, flip-chip mounted) on the stacked body 60d to obtain an electronic component.
According to the method for manufacturing a laminate according to the present embodiment, the electroless plating layer 20 can be used as a power supply layer for forming the metal bump 50. In addition, when it is necessary to remove the power supply layer from the viewpoint of suppressing the occurrence of disturbance or the like after the metal bump 50 is formed, the 2 nd portion 20b of the electroless plating layer 20 having a relatively thin layer can be easily removed, and thus the stacked bodies 60a to 60d on which the semiconductor element can be mounted can be easily obtained. Further, according to the method for manufacturing a laminate according to the present embodiment, it is not necessary to form the power supply layer after forming the insulating layer 32 on the base material 10, and it is possible to suppress the complexity of the manufacturing process of the laminates 60a to 60d on which the semiconductor element can be mounted. In the laminated bodies 60a to 60d obtained by the method for manufacturing a laminated body according to the present embodiment, the semiconductor element can be built in (three-dimensionally mounted) at a position on the base 10 different from the position where the metal bump 50 is formed, and the laminated bodies can be connected to another semiconductor element, a module board, or an electronic component via the metal bump 50, so that the electronic component including the semiconductor element can be reduced in size, thickness, or density.
However, as a method of forming a metal bump on a substrate, a method of removing an unnecessary portion of a metal layer by etching or the like in a state where a mask is disposed at a position where the metal bump should be formed after depositing the metal layer on the substrate is considered. However, in this method, the tapered portion is formed in the metal bump by over-etching the side portion of the metal bump, and thus the diameter of the metal bump may not be uniform along the length direction of the metal bump. On the other hand, according to the method for manufacturing a laminate according to the present embodiment, by forming the metal bump 50 in the opening 32a of the insulating layer 32, the metal bump 50 having the same shape as the shape of the opening 32a can be easily obtained, and the diameter of the metal bump 50 can be easily made uniform along the longitudinal direction of the metal bump 50.
Although the description has been given above of examples of the embodiments of the laminate, the electronic component, and the method for manufacturing the same, the present invention is not limited to the above embodiments.
For example, although the electroless plating layer removing step is performed between the insulating layer removing step and the protective layer forming step in the above embodiment, the protective layer forming step may be performed after the insulating layer removing step without performing the electroless plating layer removing step. As shown in fig. 5, in the laminate 60e obtained at this time, the protective layer 70 is disposed on the electrode layer 12 and the electroless plating layer 20, unlike the laminate 60d of fig. 4 (b). The protective layer 70 indirectly covers the electrode layer 12 via the electroless-plating layer 20.
In the above embodiment, the protective layer forming step of forming the protective layer 70 is performed after the electroless plating layer forming step, but the protective layer forming step may be performed before the electroless plating layer forming step. In this case, first, after the substrate 10 is prepared in the substrate preparation step, as shown in fig. 6(a), the protective layer 70 covering at least a part of the electrode layer 12 is formed. The protective layer 70 covers, for example, an end portion of the electrode layer 12 (electrode layer on the right end in fig. 6 a) disposed at the formation position of the metal bump 50.
Next, as shown in fig. 6(b), in the electroless plating layer forming step, the electrode layer 12 and the protective layer 70 disposed on the main surface 10a of the substrate 10 are subjected to electroless plating to form the electroless plating layer 20. Thereby, the electroless plating layer 20 covering the electrode layer 12 and the protective layer 70 is formed. The electroless plating layer 20 has a 1 st portion 20a disposed at a position where the metal bump 50 is formed and a 2 nd portion 20b disposed at a position different from the position where the metal bump 50 is formed.
Next, as shown in fig. 7(a), in the insulating layer forming step, an opening is formed in the insulator disposed on the substrate 10 to obtain an insulating layer 32 having an opening 32 a. Thus, a base 40a is obtained, the base 40a including: a substrate 10 having an electrode layer 12 on a main surface 10 a; an electroless plating layer 20 disposed at least on the electrode layer 12; and an insulating layer 32 which is disposed on the base 10 and has an opening 32a through which the electroless-plated layer 20 (the plated layer formed of the electroless-plated layer 20) is exposed.
Next, in the bump forming step, electrolytic plating is performed in the opening 32a of the insulating layer 32 in the base 40a to form the metal bump 50 in contact with the electroless-plated layer 20 in the opening 32a, and then, as shown in fig. 7(b), the insulating layer 32 is removed in the insulating layer removing step to obtain a laminate 60 f. In the case where the laminate 60f is an electronic component obtained by laminating semiconductor elements, the 2 nd portion 20b of the electroless plating layer 20 may be removed in the electroless plating layer removing step, or the 2 nd portion 20b may not be removed.
Further, in the above embodiment, the electrode layer 12 and the electroless plating layer 20 are not adjacent to each other in the direction orthogonal to the lamination direction of the electrode layer 12 and the electroless plating layer 20 between the metal bump 50 and the substrate 10, but the electrode layer 12 and the electroless plating layer 20 may be adjacent to each other in the direction orthogonal to the lamination direction of the electrode layer 12 and the electroless plating layer 20 between the metal bump 50 and the substrate 10 as in a laminate 60g shown in fig. 8 which is an enlarged view of the metal bump 50 and its periphery, for example. In the laminate 60g, the electrode layer 12 is disposed in the opening 32a of the insulating layer 32, and the insulating layer 32 having the opening 32a larger in diameter than the electrode layer 12 is formed on the substrate 10. At this time, the electrode layer 12 and the electroless-plated layer 20 are adjacent to each other in the direction orthogonal to the lamination direction of the electrode layer 12 and the electroless-plated layer 20 in the main surface 10a of the substrate 10 at the position where the metal bump 50 is formed. In the laminate 60g, the 1 st portion 20a disposed at the position where the metal bump 50 is formed in the electroless plating layer 20 and the 2 nd portion 20b disposed at the position different from the position where the metal bump 50 is formed in the electroless plating layer 20 are not adjacent to each other in the direction orthogonal to the stacking direction of the electrode layer 12 and the electroless plating layer 20 on the electrode layer 12.
Further, in the above embodiment, the metal bump 50 in contact with the electroless-plated layer 20 exposed from the opening 32a of the insulating layer 32 is formed using the plated layer composed of the electroless-plated layer 20, but a metal bump in contact with the electrolytic-plated layer exposed from the opening of the insulating layer (the outermost layer of the plated layer) may be formed, the plated layer having an electroless-plated layer and an electrolytic-plated layer disposed on the electroless-plated layer.
Also, the metal bumps may be formed on both surfaces of the stacked body. The laminate may have a plurality of metal bumps on one or both main surfaces. The electronic component may include a plurality of semiconductor elements.
Description of the symbols
10-substrate, 10 a-main face (surface), 12-electrode layer, 20-electroless plating layer, 32-insulating layer, 32 a-opening, 40 a-base, 50-metal bump, 60a, 60b, 60c, 60d, 60e, 60f, 60 g-laminate, 70-protective layer.
Claims (20)
1. A method for producing a laminate, wherein,
the base body is provided with: a substrate having an electrode layer on a surface thereof; an electroless plating layer at least disposed on the electrode layer; and an insulating layer disposed on the base material and having an opening through which a plating layer including the electroless plating layer is exposed,
the method for manufacturing the laminated body comprises the following steps: and a bump forming step of forming a metal bump in contact with the plating layer in the opening by performing electrolytic plating on the base.
2. The method for producing a laminate according to claim 1,
the method further includes a step of forming an opening in the insulator disposed on the substrate to obtain the insulating layer, prior to the bump forming step.
3. The method for producing a laminate according to claim 1 or 2, wherein,
the bump forming method further includes an electroless plating layer forming step of forming the electroless plating layer by performing electroless plating on the electrode layer, prior to the bump forming step.
4. The method for producing a laminate according to claim 3, wherein,
the method further includes, before the step of forming the electroless plating layer, a step of forming a protective layer having an opening through which the electrode layer is exposed on the base material.
5. The method for producing a laminate according to any one of claims 1 to 4, wherein,
the method further includes an insulating layer removing step of removing the insulating layer after the bump forming step.
6. The method for producing a laminate according to claim 5, wherein,
the method further includes a step of removing a portion of the electroless plating layer, which is disposed at a position different from a position where the metal bump is formed, after the insulating layer removing step.
7. The method for producing a laminate according to claim 5 or 6,
the method further includes a step of forming a protective layer covering the electrode layer after the insulating layer removing step.
8. The method for producing a laminate according to any one of claims 1 to 7,
the electroless-plated layer is exposed from the opening of the insulating layer.
9. The method for producing a laminate according to any one of claims 1 to 8, wherein,
the electrode layer is a circuit pattern.
10. The method for producing a laminate according to any one of claims 1 to 9,
the length of the metal bump in the stacking direction of the electrode layer and the electroless plating layer is 10 [ mu ] m or more.
11. The method for producing a laminate according to any one of claims 1 to 9,
the length of the metal bump in the stacking direction of the electrode layer and the electroless plating layer exceeds 150 [ mu ] m.
12. The method for producing a laminate according to any one of claims 1 to 11,
the electrode layer and the electroless-plated layer are not adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material.
13. The method for producing a laminate according to any one of claims 1 to 11,
the electrode layer and the electroless-plated layer are adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material.
14. A laminate provided with:
a substrate having an electrode layer on a surface thereof;
an electroless plating layer at least disposed on the electrode layer; and
a metal bump which is in contact with a plating layer including the electroless plating layer on the electroless plating layer.
15. The laminate according to claim 14, wherein,
the metal bump is in contact with the electroless plating layer.
16. The laminate according to claim 14 or 15,
the electrode layer is a circuit pattern.
17. The laminate according to any one of claims 14 to 16,
the length of the metal bump in the stacking direction of the electrode layer and the electroless plating layer is 10 [ mu ] m or more.
18. The laminate according to any one of claims 14 to 16,
the length of the metal bump in the stacking direction of the electrode layer and the electroless plating layer exceeds 150 [ mu ] m.
19. The laminate according to any one of claims 14 to 18,
the electrode layer and the electroless-plated layer are not adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material.
20. The laminate according to any one of claims 14 to 18,
the electrode layer and the electroless-plated layer are adjacent to each other in a direction orthogonal to a lamination direction of the electrode layer and the electroless-plated layer between the metal bump and the base material.
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| JP2005135985A (en) * | 2003-10-28 | 2005-05-26 | Kaneka Corp | Manufacturing method for printed wiring board |
| JP4705972B2 (en) * | 2008-05-16 | 2011-06-22 | 株式会社三興 | Printed wiring board and manufacturing method thereof |
| JP2014072306A (en) * | 2012-09-28 | 2014-04-21 | Sanken Electric Co Ltd | Semiconductor device and semiconductor device manufacturing method |
| JP2014072326A (en) * | 2012-09-28 | 2014-04-21 | Hitachi Chemical Co Ltd | Semiconductor element mounting package substrate and manufacturing method therefor |
| JP2015015302A (en) * | 2013-07-03 | 2015-01-22 | イビデン株式会社 | Printed wiring board and method for manufacturing printed wiring board |
| JP2015162660A (en) | 2014-02-28 | 2015-09-07 | イビデン株式会社 | Printed wiring board, manufacturing method of the same, and package-on-package |
| JP2017034059A (en) * | 2015-07-31 | 2017-02-09 | イビデン株式会社 | Printed wiring board, semiconductor package and manufacturing method for printed wiring board |
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| JP2008294357A (en) * | 2007-05-28 | 2008-12-04 | Nitto Denko Corp | Method of manufacturing wiring circuit board, and plating apparatus |
| TW201328447A (en) * | 2011-12-22 | 2013-07-01 | Samsung Electro Mech | Printed circuit board and method for manufacturing the same |
| JP2014192203A (en) * | 2013-03-26 | 2014-10-06 | Ibiden Co Ltd | Method of manufacturing wiring board |
| CN106165554A (en) * | 2014-02-06 | 2016-11-23 | Lg伊诺特有限公司 | Printed circuit board (PCB), base plate for packaging and manufacture method thereof |
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