CN112490243B - 三维半导体结构及其制作方法 - Google Patents

三维半导体结构及其制作方法 Download PDF

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CN112490243B
CN112490243B CN201910862593.5A CN201910862593A CN112490243B CN 112490243 B CN112490243 B CN 112490243B CN 201910862593 A CN201910862593 A CN 201910862593A CN 112490243 B CN112490243 B CN 112490243B
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layer
doped
gallium nitride
barrier layer
drain
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CN112490243A (zh
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邱永振
薛胜元
李国兴
吴建良
康智凯
黄冠凯
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United Microelectronics Corp
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Abstract

本发明公开一种三维半导体结构及其制作方法，其中该三维半导体装置包含一缓冲层、一n型高电子移动率晶体管设置在该缓冲层的第一表面上、以及一p型高空穴移动率晶体管设置在该缓冲层与该第一表面相对的第二表面上。

Description

三维半导体结构及其制作方法
技术领域
本发明涉及一种三维半导体结构，更具体言之，其涉及一种同时具有高电子移动率晶体管(high electron mobility transistor,HEMT)与高空穴移动率晶体管(highhole mobility transistor,HHMT)的三维半导体结构。
背景技术
随着近年来无线通讯市场的火热以及功率元件应用的稳定进展，微波晶体管在人类活动的许多层面上都扮演了重要的角色，对于其效能的需求也越来越迫切。在个人行动通讯的应用方面，下一世代的手机会有更高的频宽与效能需求，而因为不断增快的速度与资料传输率，宽频无线网路同样也有此需求。由于这类需求，现今业界大量投资在开发以硅/硅锗(Si/SiGe)、砷化镓(GaAs)、碳化硅(SiC)等半导体材料为主的高效能微波晶体管与放大器，其兼具大的击穿电压与高电子速度特点。
其中，形成异质结(接面)的能力使得氮化镓成为了用来制作高电子移动率晶体管(high electron mobility transistor,HEMT)或是高空穴移动率晶体管(high holemobility transistor,HHMT)的优异材料。这种晶体管的优点包含其高载流子浓度以及因为游离杂质散射较少所导致的高载流子移动率。高载流子浓度与高载流子移动率的结合也导致了其具备高电流密度与低通道电阻的特性，这两者在高频运作与电源切换的应用方面都十分重要。
在空乏模式的高电子移动率晶体管场合，栅极所产生的电场会用来耗尽半导体宽带隙与窄带隙界面处的二维电子气(two-dimension electron gas,2DEG)通道，如氮化铝/氮化镓(AlN/GaN)或氮化铝镓/氮化镓(AlGaN/GaN)之间的界面，在栅极施加控制电压可直接影响与控制流经该通道的电流量。空乏型晶体管在作为开关时是以正常开启(normally-on)元件的型态运作的。在增强模式下的高电子移动率晶体管，其晶体管在被施加偏压运作之前不会有通道与电流存在，其特别之处在于晶体管会被施加偏压来使其二维电子气通道移动到费米能阶以下，此时一旦源极与漏极之间有施加电压，二维电子气通道中的电子就会从源极移动到漏极。增强型晶体管一般用在数字与模拟集成电路中作为正常关闭(normally-off)元件。增强型晶体管在模拟电路应用方面也很有用处，例如作为射频/微波功率放大器或开关。
现今氮化铝镓/氮化镓高载流子移动率晶体管在高功率、高温应用方面的研究有所展望。故此，相关领域与业界仍然持续在高功率、高电压、高速、以及/高温应用方面改善这类元件的制作方法与结构。
发明内容
本发明即提出了一种同时具有高电子移动率晶体管(HEMT)与高空穴移动率晶体管(HHMT)的三维半导体结构，其可在三维空间垂直整合互补性的n型与p型的场效应晶体管。
本发明的其一面向在于提出一种三维半导体装置，其包含一缓冲层，具有第一表面以及与该第一表面相对的第二表面、一n型高电子移动率晶体管，设置在该缓冲层的该第一表面上、以及一p型高空穴移动率晶体管，设置在该缓冲层的该第二表面上。
本发明的另一面向在于提出一种三维半导体装置的制作方法，其步骤包含：提供一基底。在该基底上依序形成一掺杂氮化铝镓阻障层、一掺杂氮化镓通道层、一缓冲层、一未掺杂氮化镓通道层以及一未掺杂氮化铝镓阻障层，其中该掺杂氮化镓通道层中形成二维空穴气(2DHG)，该未掺杂氮化镓通道层中形成二维电子气(2DEG)。在该未掺杂氮化铝镓阻障层上形成第一栅极、第一源极以及第一漏极，其中该未掺杂氮化镓通道层、该未掺杂氮化铝镓阻障层、该第一栅极、该第一源极以及该第一漏极构成一n型高电子移动率晶体管。在该未掺杂氮化铝镓阻障层、该第一栅极、该第一源极以及该第一漏极上覆盖一第一钝化层。将该基底翻转并移除该基底，以裸露出该掺杂氮化铝镓阻障层，以及在该掺杂氮化铝镓阻障层上形成第二栅极、第二源极以及第二漏极，其中该掺杂氮化镓通道层、该掺杂氮化铝镓阻障层、该第二栅极、该第二源极以及该第二漏极构成一p型高空穴移动率晶体管。
本发明的这类目的与其他目的在阅者读过下文中以多种附图与绘图来描述的优选实施例的细节说明后应可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些附图描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些附图中：
图1～图6为本发明实施例中三维半导体结构的制作方法的截面示意图；
图7为使用本发明三维半导体结构所构成的反向器的电路图；以及
图8～图10为根据本发明实施例中三种不同性质的缓冲层的能带图。
需注意本说明书中的所有附图都为图例性质，为了清楚与方便附图说明之故，附图中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 三维半导体结构
102 基底
102a 背面
104 掺杂氮化铝镓阻障层
106 掺杂氮化镓通道层
108 缓冲层
108a 第一表面
108b 第二表面
110 未掺杂氮化镓通道层
112 未掺杂氮化铝镓阻障层
113 源极/漏极凹槽
114,116 钝化层
118 接垫开口
120 高电子移动率晶体管
130 高空穴移动率晶体管
2DEG 二维电子气
2DHG 二维空穴气
D1 第一漏极
D2 第二漏极
EC 导电带
EF 费米能阶
EV 价电带
G1 第一栅极
G2 第一栅极
In 输入端
Out 输出端
S1 第一源极
S2 第一源极
VDD 工作电压
VSS 接地电压
具体实施方式
现在下文将详细谈述本发明的实施范例，其绘示在随附的附图中让阅者得以了解与施作本发明揭露，并知晓其技术功效。需注意下文仅是以范例的方式来进行说明，其并未要限定本发明的揭露内容。本发明的多种实施例以及该些实施例中的各种特征在不互相冲突抵触的情况下可以多种不同的方式来加以组合与重设。在不悖离本发明的精神与范畴的原则下，各种对于本发明揭露内容的修改、对应物、或是改良手段等应都能为本技术领域的相关技术人士所理解，且意欲含括在本发明揭露的范畴内。
应该容易理解的是，本文中的「在...上面」、「在...之上」及「在...上方」的含义应该以最宽义的方式来解释，使得「在...上面」不仅意味着「直接在某物上」，而且还包括在某物上且两者之间具有中间特征或中间层，并且「在...之上」或「在...上方」不仅意味着在某物之上或在某物上方的含义，而且还可以包括两者之间没有中间特征或中间层(即直接在某物上)的含义。
此外，为了便于描述，可以在说明书使用诸如「在...下面」、「在...之下」、「较低」、「在...之上」、「较高」等空间相对术语来描述一个元件或特征与另一个或多个元件或特征的关系，如附图中所表示者。除了附图中描绘的方向之外，这些空间相对术语旨在涵盖使用或操作中的装置的不同方位或方向。该装置可以其他方式定向(例如以旋转90度或以其它方向来定向)，并且同样能相应地以说明书中所使用的空间相关描述来解释。
如本文所使用的，术语「层」是指一材料部分，其一区域具有一厚度。一层的范围可以在整个下层或上层结构上延伸，或者其范围可以小于下层或上层结构的范围。此外，一层可以为均匀或不均匀连续结构的一区域，其厚度可小于该连续结构的厚度。例如，一层可以位于该连续结构的顶表面及底表面之间或在该连续结构的顶表面及底表面之间的任何一对水平平面之间。一层可以水平地、垂直地及/或沿着渐缩表面延伸。一基底可以为一层，其可以包括一层或多层，及/或可以在其上面及/或下面具有一层或多层。一层可以包含多层。例如，互连层可以包括一个或多个导体及接触层(其中形成有接点、互连线及/或通孔)以及一个或多个介电层。
现在下文将说明根据本发明实施例一三维半导体结构的制作方法。图1～图6依序绘示出该三维半导体结构在不同制作阶段时的截面示意图。本发明的三维半导体结构同时包含了高电子移动率晶体管(high electron mobility transistor,HEMT)与高空穴移动率晶体管(high hole mobility transistor,HHMT)两种晶体管，此两种场效晶体管结合了不同带隙的材料之间的结(即异质结)来作为通道，而非使用一般如金属氧化物半导体场效晶体管(MOSFET)的掺杂区。
请参照图1，首先提供一基底102。基底102可以硅或是其他半导体材料制成。在一些实施例中，基底102是蓝宝石基底，其上具有半导体层，如〈111〉晶格结构的硅层。硅〈111〉层可对上层结构提供理想的晶格匹配，如对上层的氮化镓(GaN)层或是氮化铝镓(GaN)层。在一些实施例中，该半导体层可以半导体化合物来制成，如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)、或是磷化铟(InP)。在一些实施例中，半导体层可以半导体合金来制成，如硅锗、碳化硅锗、磷化砷镓、或是磷化铟镓。为了附图简明之故，图中将不示出该半导体层。
此外，在形成后续的上层结构之前，可先在基底102上形成一缓冲层(未示出)，用来补偿与缓冲基底102与上层结构之间晶格结构与/或热膨胀系数不匹配情况。在一些实施例中，缓冲层的材料可为氮化镓(GaN)。为了附图简明之故，图中将不示出该缓冲层。
接下来，复参照图1，在基底102上依序形成一掺杂氮化铝镓(doped AlGaN)阻障层104以及一掺杂氮化镓(doped GaN)通道层106。在本发明实施例中，掺杂氮化铝镓阻障层104与掺杂氮化镓通道层106中掺有p型掺质。这类p型掺质的例子包括但不限定是碳(C)、铁(Fe)、镁(Mg)、或锌(Zn)等。掺有p型掺质的掺杂氮化铝镓阻障层104以及一掺杂氮化镓通道层106之间会形成一异质结，其间存在着带隙不连续性。在一些实施例中，掺杂氮化铝镓阻障层104的带隙会大于掺杂氮化镓通道层106的带隙，阻障层104中因异质结处的压电极化效应生成的空穴会落入通道层106中，从而产生出一高移动传导性的空穴薄层，此即掺杂氮化镓通道层106中的二维空穴气(two dimension hole gas,2DHG)，其邻近与掺杂氮化铝镓阻障层104的界面处。二维空穴气2DHG中的空穴会是高空穴移动率晶体管的电荷载体。在一些实施例中，掺杂氮化铝镓阻障层104与掺杂氮化镓通道层106可以外延生长制作工艺来形成，其例子包含但不限定是金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)制作工艺、以及氢化物气相外延(HVPE)制作工艺等。掺杂氮化铝镓阻障层104可具有成分梯度转变(AlyGa1-yN)的特征，其中y是氮化铝镓中的铝成分比例，y介于0至1之间，或是两者的组合。
复参照图1，接下来掺杂氮化镓通道层106上形成一缓冲层108。在本发明实施例中，缓冲层108设置在高空穴移动率晶体管(HHMT)与高电子移动率晶体管(HEMT)之间，其作为两者的层结构以及能带之间的过渡层。缓冲层108可以多种不同的材料制成。例如在一实施例中，缓冲层108的材料可以是氮化镓且具有与掺杂氮化镓通道层106以及掺杂氮化铝镓阻障层104中同样的掺质，如碳、铁、镁、或锌，且缓冲层108中该掺质的浓度会从其第一表面108a的零掺杂浓度往相对的第二表面108b(与掺杂氮化镓通道层106相接的那一面)逐渐增加为与掺杂氮化镓通道层106中相同的掺杂浓度。在一些实施例中，缓冲层108可以是宽带隙层，亦即其材料的带隙大于与该掺杂氮化镓通道层106相接的界面处的带隙或是大于与其他相邻层结构的结处的带隙。而在一些实施例中，缓冲层108可以是一超晶格(superlattice)叠层，例如氮化铝镓/氮化镓的交互叠层结构(AlGaN/GaN)或是氮化铝镓/氮化铟镓的交互叠层结构(AlGaN/InGaN)。关于缓冲层的材料组成与功能在后文实施例中将有更详尽的说明。在实施例中，缓冲层108可以外延生长制作工艺来形成，例如在掺质为镁的场合中，其可以双环戊二烯镁((C5H5)2Mg)为前驱物而使用金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)制作工艺、或是氢化物气相外延(HVPE)等制作工艺来形成。
复参照图1，在形成缓冲层108后，接下来在缓冲层108上依序形成一未掺杂氮化镓(undoped GaN)通道层110以及一未掺杂氮化铝镓(undoped AlGaN)阻障层112。未掺杂氮化铝镓阻障层112以及未掺杂氮化镓通道层110之间会形成一异质结，其间存在着带隙不连续性。在一些实施例中，未掺杂氮化铝镓阻障层112的带隙会大于未掺杂氮化镓通道层110的带隙，阻障层112中因异质结处的压电极化效应生成的电子会落入通道层110中，从而产生出一高移动传导性的电子薄层，此即未掺杂氮化镓通道层110中的二维电子气(twodimension electron gas,2DEG)，其邻近与未掺杂氮化铝镓阻障层112的界面处。二维电子气2DEG中的电子会是高电子移动率晶体管的电荷载体。在一些实施例中，未掺杂氮化镓通道层110与未掺杂氮化铝镓阻障层112可以外延生长制作工艺来形成，其例子包含但不限定是金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)制作工艺、以及氢化物气相外延(HVPE)制作工艺等。未掺杂氮化铝镓阻障层112可具有成分梯度转变(AlyGa1-yN)的特征，其中y是氮化铝镓中的铝成分比例，y介于0至1之间，或是两者的组合。
上述实施例中所说明的形成掺杂氮化铝镓阻障层104、掺杂氮化镓通道层106、缓冲层108、未掺杂氮化镓通道层110、以及未掺杂氮化铝镓阻障层112的动作都可以在相同的制作工艺腔体中临场(in-situ)进行，不需换腔体，以节省成本与时间并降低污染。再者，在其他实施例中，上述各层也可以相反的顺序来形成，亦即在基底102上依序形成未掺杂氮化铝镓阻障层112、未掺杂氮化镓通道层110、缓冲层108、掺杂氮化镓通道层106、以及掺杂氮化铝镓阻障层104。
由于二维电子气2DEG与二维空穴气2DHG是在没有栅极结构的情况下自然产生的，其所构成的晶体管(例如HEMT与HHMT)不用对栅极施加电压即为导通态，亦即其在负临限电压的场合下会是正常开启(normally-on)元件。这样的正常开启状态在功率元件应用的设计考虑下是不利的，因为其要避免或是在很大的程度上抑止电流流经或流入晶体管。在一些实施例中，为了要将正常开启态的晶体管元件转变成正常关闭(normally-off)态，晶体管的阻障层上方会设置栅极来耗尽其下方的二维电子气2DEG与二维空穴气2DHG，其细节将于后续实施例中说明。
现在请参照图2。在形成未掺杂氮化铝镓阻障层112后，接下来进行光刻制作工艺在未掺杂氮化铝镓阻障层112中形成源极/漏极凹槽113。如图所示，该源极/漏极凹槽113会延伸穿过整个未掺杂氮化铝镓阻障层112并深入部分的未掺杂氮化镓通道层110而切断其中的二维电子气2DEG。形成源极/漏极凹槽113后，接下来在源极/漏极凹槽113上形成第一源极S1与第一漏极D1。第一源极S1与第一漏极D1可以以下方式来形成：首先通过沉积制作工艺在源极/漏极凹槽113中以及未掺杂氮化镓通道层112上形成一金属层。在一些实施例中，该金属层包含一或多种导电材料，例如钛(Ti)、钴(Co)、镍(Ni)、钨(W)、铂(Pt)、钽(Ta)、钯(Pd)、钼(Mo)、氮化钛(TiN)、铝铜合金(AlCu)、以及以上材料的合金。该沉积制作工艺包括化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)、金属有机物化学气相沉积(MOCVD)、等离子体辅助化学气相沉积(PECVD)、或其他可应用的沉积制作工艺。之后，通过光刻制作工艺将该金属层图案化为第一源极S1与第一漏极D1。
复参照图2，在形成第一源极S1与第一漏极D1后，接下来在第一源极S1与第一漏极D1之间的未掺杂氮化铝镓阻障层112上形成第一栅极G1。在一些实施例中，第一栅极G1包含难熔金属或相关化合物的导电材料层，如钛(Ti)、氮化钛(TiN)、钨钛合金(TiW)、以及钨(W)等。或者，第一栅极G1可包含镍(Ni)、金(Au)、铜(Cu)、或其合金。第一栅极G1与第一源极S1/第一漏极D1一样可通过沉积制作工艺与光刻制作工艺来形成。第一栅极G1与未掺杂氮化铝镓阻障层112之间可能形成有栅极介电层来增加高电子移动率晶体管120的临限电压。为了附图简明之故，图中将不示出该栅极介电层相关制作工艺。
复参照图2，在第一栅极G1与第一源极S1/第一漏极D1都形成后，接下来形成一钝化层114盖住整个未掺杂氮化铝镓阻障层112、第一栅极G1与第一源极S1/第一漏极D1来提供元件保护效果。钝化层114的材料可为聚酰亚胺。在一些实施例中，在形成钝化层114前可在未掺杂氮化铝镓阻障层112上制作接触结构与/或金属绕线等线路结构。由于该些部位并非本发明重点，图中将不会示出。在本发明实施例中，未掺杂氮化镓通道层110、未掺杂氮化铝镓阻障层112、二维电子气2DEG、第一栅极G1、以及第一源极S1/第一漏极D1即构成了一n型高电子移动率晶体管120，其建构在缓冲层108的第一表面108a上。在第一栅极G1施加电压即可调控元件的电流。
请参照图3，在完成n型高电子移动率晶体管120的制作后，接下来将整个基底102(包含其上面的层结构)翻转，使得基底102的背面102a朝上作为制作工艺表面。
接着，如图4所示，对基底102背面102a进行一晶背研磨制作工艺将基底102移除，裸露出下方的掺杂氮化铝镓阻障层104，如此即可开始进行高空穴移动率晶体管的制作。
请参照图5。在裸露出掺杂氮化铝镓阻障层104后，接下来在掺杂氮化铝镓阻障层104上形成第二栅极G2、第二源极S2、以及第二漏极D2。第二栅极G2、第二源极S2、以及第二漏极D2的材料与制作方式与第一栅极G1、第一源极S1、以及第一漏极D1的相同，此处不再多予赘述。第二源极S2与第二漏极D2会延伸穿过整个掺杂氮化铝镓阻障层104并深入部分的掺杂氮化镓通道层106而切断其中的二维空穴气2DHG。一钝化层116会形成来盖住整个掺杂氮化铝镓阻障层104、第二栅极G2与第二源极S2/第二漏极D2来提供元件保护效果。在本发明实施例中，掺杂氮化镓通道层106、掺杂氮化铝镓阻障层104、二维空穴气2DHG、第二栅极G2与第二源极S2/第二漏极D2即构成了一p型高空穴移动率晶体管130，其建构在缓冲层108的第二表面108b上，相对于建构在缓冲层108第一表面108a上的n型高电子移动率晶体管120。
请参照图6。在完成n型高电子移动率晶体管120与p型高空穴移动率晶体管130的制作后，可进行光刻制作工艺在第一栅极G1、第一源极S1/第一漏极D1、第二栅极G2、以及第二源极S2/第二漏极D2上的钝化层114,116中形成接垫开口118。接垫开口118可让n型高电子移动率晶体管120与p型高空穴移动率晶体管130的栅极与源极/漏极连接到外部线路。
根据前述图1～图6所描述的制作方法实施例，本发明于此提出了一种三维半导体装置。如图6所示，本发明的三维半导体装置100包括一缓冲层108，其具有第一表面108a以及与该第一表面108a相对的第二表面108b、一n型高电子移动率晶体管120，设置在缓冲层108的第一表面108a上、以及一p型高空穴移动率晶体管130，设置在缓冲层108的第二表面108b上。需注意本发明的n型高电子移动率晶体管120与p型高空穴移动率晶体管130可以设计成是空乏模式的正常开启(normally-on)元件，也可以是设计成是增强模式的正常关闭(normally-off)元件，端视实际的产品需求而定。采用图1～图6所描述的制作工艺，本发明的三维半导体装置100在三维空间中垂直整合了互补性的n型高电子移动率晶体管120与p型高空穴移动率晶体管130，其大幅减少所需的布局面积，可应用在需要高频、高功率、高电压、高速的元件领域，如反向器或是静态随机存取存储器(SRAM)、微处理器或是其他数字逻辑电路系统等。
例如，请参照图7的实施例，其绘示出了使用本发明三维半导体结构100所构成的反向器的电路图。在此实施例中，n型高电子移动率晶体管120的栅极与p型高空穴移动率晶体管130的栅极连接到一共同的输入端In，该n型高电子移动率晶体管的漏极与该p型高空穴移动率晶体管的漏极连接到一共同的输出端Out，n型高电子移动率晶体管120的源极连接到一接地电压VSS，p型高空穴移动率晶体管130的源极连接到一工作电压VDD。如此，本发明的三维半导体结构即构成了一反向器结构。从上述的实施例可知，本发明的三维半导体结构可在单一元件的面积下通过3D堆叠方式来含括两个以上晶体管，特别是互补性的晶体管，从而构成互补式金属氧化物半导体(CMOS)类型的元件。
在说明完了本发明的三维半导体结构及其形成方法之后，现在将具体说明本发明三维半导体结构中多种缓冲层组成的细节，其中将以能带图的方式来说明不同的缓冲层组成对整个三维半导体结构的能阶带来的影响。
首先请参照图8，其左半部部位是n型高电子移动率晶体管120的能带，可以看到其导电带EC在阻障层和通道层之间的异质结处因为压电极化的关系掉落到费米能阶EF以下，形成了二维电子气2DEG通道。右半部部位是p型高空穴移动率晶体管130的能带，可以看到其价电带EV在阻障层和通道层之间的异质结处上升到费米能阶EF以上，形成了二维空穴气2DHG通道。掺有杂质的p型高空穴移动率晶体管130的能带是高于未掺杂的n型高电子移动率晶体管120的能带。
在晶体管的通道层是氮化镓的情况下，缓冲层108的材料同样可以是氮化镓，且其中掺有与掺杂氮化镓通道层106中同样的掺质，例如镁。更特别的是，缓冲层108中该掺质的浓度会从其第一表面108a(与n型高电子移动率晶体管120相接的那一面)的零掺杂浓度往相对的第二表面108b(与p型高空穴移动率晶体管130相接的那一面)逐渐增加为与掺杂氮化镓通道层106中相同的掺杂浓度。如此相同掺质的浓度梯度变化使得缓冲层108可作为n型高电子移动率晶体管120与p型高空穴移动率晶体管130之间晶格与能带的过渡层，其在生成缓冲层108以上的层结构(如未掺杂氮化镓通道层110与未掺杂氮化铝镓阻障层112)时较不会产生错位等缺陷，影响到层结构的品质。
接着请参照图9。考虑到要避免n型高电子移动率晶体管120与p型高空穴移动率晶体管130之间互相干扰，两者之间的缓冲层108也可设计成是一宽带隙层，亦即如图所示，其材料的带隙大于相邻的未掺杂氮化镓通道层110以及掺杂氮化镓通道层106，如此因为量子限制效应的缘故，n型高电子移动率晶体管120与p型高空穴移动率晶体管130中的高能电荷载体无法游离到另一晶体管。在本发明实施例中，缓冲层108的材料可以是氮化铝镓或氮化铝，其带隙显著大于相邻的两个氮化镓通道层。
最后请参照图10，在本发明实施例中，缓冲层108也可以是一超晶格叠层，例如氮化铝镓/氮化镓的交互叠层或是氮化铝镓/氮化铟镓的交互叠层。使用超晶格叠层结构的优点在于可通过超晶格叠层在水平方向的应变消除三维半导体结构的层结构在生长时垂直方向上的应力，如此较不会产生错位等缺陷，影响到层结构的品质。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种三维半导体装置，其特征在于，该三维半导体装置包含：
缓冲层，具有第一表面以及与该第一表面相对的第二表面；
n型高电子移动率晶体管，设置在该缓冲层的该第一表面上；以及
p型高空穴移动率晶体管，设置在该缓冲层的该第二表面上，
其中该n型高电子移动率晶体管包含：
未掺杂氮化镓通道层，位于该缓冲层的该第一表面上；
未掺杂氮化铝镓阻障层，位于该未掺杂氮化镓通道层上；以及
栅极、源极与漏极，位于该未掺杂氮化铝镓阻障层上，
其中该p型高空穴移动率晶体管包含：
掺杂氮化镓通道层，位于该缓冲层的该第二表面上；
掺杂氮化铝镓阻障层，位于该掺杂氮化镓通道层上；以及
栅极、源极与漏极，位于该掺杂氮化铝镓阻障层上。
2.根据权利要求1所述的三维半导体装置，还包含钝化层，覆盖在该未掺杂氮化铝镓阻障层以及该栅极、该源极与该漏极上。
3.根据权利要求1所述的三维半导体装置，其中该掺杂氮化镓通道层以及该掺杂氮化铝镓阻障层中的掺质包括碳(C)、铁(Fe)、镁(Mg)、或锌(Zn)。
4.根据权利要求1所述的三维半导体装置，其中该缓冲层的材料为氮化镓且具有与该掺杂氮化镓通道层以及该掺杂氮化铝镓阻障层中同样的掺质，且该缓冲层中的该掺质的浓度从该第一表面的零掺杂浓度往该第二表面逐渐增加为与该掺杂氮化镓通道层中相同的掺杂浓度。
5.根据权利要求1所述的三维半导体装置，还包含钝化层，覆盖在该掺杂氮化铝镓阻障层以及该栅极、该源极与该漏极上。
6.根据权利要求1所述的三维半导体装置，其中该缓冲层为宽带隙层，该宽带隙层的带隙大于与该未掺杂氮化镓通道层相接的界面处的带隙以及大于与该掺杂氮化镓通道层相接的界面处的带隙。
7.根据权利要求6所述的三维半导体装置，其中该宽带隙层的材料为氮化铝镓或氮化铝。
8.根据权利要求1所述的三维半导体装置，其中该缓冲层为超晶格叠层。
9.根据权利要求8所述的三维半导体装置，其中该超晶格叠层为氮化铝镓/氮化镓的交互叠层或是氮化铝镓/氮化铟镓的交互叠层。
10.根据权利要求1所述的三维半导体装置，其中该n型高电子移动率晶体管的栅极与该p型高空穴移动率晶体管的栅极连接到共同的输入电压，该n型高电子移动率晶体管的漏极与该p型高空穴移动率晶体管的漏极连接到共同的输出电压，构成反向器。
11.一种三维半导体装置的制作方法，包含：
提供基底；
在该基底上依序形成掺杂氮化铝镓阻障层、掺杂氮化镓通道层、缓冲层、未掺杂氮化镓通道层以及未掺杂氮化铝镓阻障层，其中该掺杂氮化镓通道层中形成二维空穴气，该未掺杂氮化镓通道层中形成二维电子气；
在该未掺杂氮化铝镓阻障层上形成第一栅极、第一源极以及第一漏极，其中该未掺杂氮化镓通道层、该未掺杂氮化铝镓阻障层、该第一栅极、该第一源极以及该第一漏极构成n型高电子移动率晶体管；
在该未掺杂氮化铝镓阻障层、该第一栅极、该第一源极以及该第一漏极上覆盖第一钝化层；
将该基底翻转并移除该基底，以裸露出该掺杂氮化铝镓阻障层；以及
在该掺杂氮化铝镓阻障层上形成第二栅极、第二源极以及第二漏极，其中该掺杂氮化镓通道层、该掺杂氮化铝镓阻障层、该第二栅极、该第二源极以及该第二漏极构成p型高空穴移动率晶体管。
12.根据权利要求11所述的三维半导体装置的制作方法，还包含在该掺杂氮化铝镓阻障层、该第二栅极、该第二源极以及该第二漏极上覆盖第二钝化层。
13.根据权利要求11所述的三维半导体装置的制作方法，其中在该未掺杂氮化铝镓阻障层上形成该第一栅极、该第一源极以及该第一漏极的步骤还包含：
在该未掺杂氮化铝镓阻障层中形成源极凹槽与漏极凹槽，其中该源极凹槽与该漏极凹槽深入部分的该未掺杂氮化镓通道层而切断该二维电子气；
在该源极凹槽与漏极凹槽中以及该未掺杂氮化铝镓阻障层上形成金属层；以及
图案化该金属层以形成该第一源极与该第一漏极。
14.根据权利要求11所述的三维半导体装置的制作方法，其中在该掺杂氮化铝镓阻障层上形成该第二栅极、该第二源极以及该第二漏极的步骤还包含：
在该掺杂氮化铝镓阻障层中形成源极凹槽与漏极凹槽，其中该源极凹槽与该漏极凹槽深入部分的该掺杂氮化镓通道层而切断该二维空穴气；
在该源极凹槽与漏极凹槽中以及该掺杂氮化铝镓阻障层上形成金属层；以及
图案化该金属层以形成该第二源极与该第二漏极。
15.根据权利要求11所述的三维半导体装置的制作方法，其中该掺杂氮化铝镓阻障层、该掺杂氮化镓通道层、该缓冲层、该未掺杂氮化镓通道层以及该未掺杂氮化铝镓阻障层以金属有机物化学气相沉积(MOCVD)方法形成。
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