CN112447837A - 一种高耐压的高电子迁移率晶体管 - Google Patents

一种高耐压的高电子迁移率晶体管 Download PDF

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CN112447837A
CN112447837A CN201910826836.XA CN201910826836A CN112447837A CN 112447837 A CN112447837 A CN 112447837A CN 201910826836 A CN201910826836 A CN 201910826836A CN 112447837 A CN112447837 A CN 112447837A
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semiconductor layer
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黎子兰
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Guangdong Zhineng Technology Co Ltd
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Guangdong Zhineng Technology Co Ltd
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Priority to EP19943513.2A priority patent/EP4006991A4/en
Priority to PCT/CN2019/115426 priority patent/WO2021035946A1/zh
Priority to US17/638,283 priority patent/US20220302292A1/en
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Abstract

本申请涉及半导体功率器件，具体而言，涉及一种高耐压高电子迁移率晶体管。高耐压高电子迁移率晶体管，其包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底；沟道层位于势垒层和基底之间，沟道层包括P‑型Ⅲ‑Ⅴ族半导体层，其中形核层与漏电极在基底上的投影至少部分区域重合，漏电极与沟道层的二维电子气电接触，源电极与P‑型Ⅲ‑Ⅴ族半导体层电接触，栅电极位于势垒层之上。

Description

一种高耐压的高电子迁移率晶体管
技术领域
本申请涉及半导体功率器件，具体而言，涉及一种高耐压高电子迁移率晶体管。
背景技术
Ⅲ-Ⅴ族化合物半导体包括至少一个III族元素和至少一种V族元素，包括但不局限于氮化镓(GaN)，氮化铝镓(AlGaN)，砷化镓(GaAs)，氮化铟铝镓(InAlGaN)，氮化铟镓(InGaN)等，III族氮化物半导体包括氮和至少一个III族元素，包括但不局限于GaN，AlGaN，InN，AlN，InGaN，InAlGaN等。
高电子迁移率晶体管(HEMT)利用Ⅲ-Ⅴ族异质结结构，如III族氮化物异质结，在III族氮化物材料形成异质结界面处产生二维电子气(2DEG)，其允许通过高的电流密度并具备相对较低的电阻损耗，并逐步实现了耐压能力提升至600V，甚至达到1200V。常规III族氮化物高电子迁移率晶体管通常为耗尽型器件，由于高击穿电压，高电流密度，和低导通电阻等优点，III族氮化物高电子迁移率晶体管需要避免高电子迁移率晶体管在没有栅压控制的情况下器件关闭以保护电路和负载。因此，希望提供III族氮化物高电子迁移率晶体管是常断的，或是增强模式晶体管。
这样，有需要克服在现有技术中的缺点和不足，制造高耐压高电子迁移率晶体管，增强型III-V族高电子迁移率晶体管。
在相关专利申请中我们已经提出通过P-型掩埋层等结构实现常关型器件和或更高的耐压能力进行了描述，对于相关的器件结构也有了详尽的描述。但在具体的实施过程中，选区外延时，形核区域位于源的位置。这主要时因为高电子迁移率晶体管对于源来说是对称结构，从源到两侧都各有栅电极和漏电极。同时，从源电极到栅电极的距离比从栅电极到漏电极的距离通常要小很多，从源到栅做侧向外延比从漏到栅要距离短很多，这有利于通过外延实现源和栅处的复杂结构的制作精度。同时，源区域的电压很低，而形核区的晶体质量相对较差，所以在源位于低质量区域的时候由于电压低而影响最小。
相比较的，如果从栅或其他区域形核并侧向外延，那么侧向外延的两侧结构是基本对称的，不利于形成很多非对称结构。并且如果是从栅电极区域开始侧向外延，那么由于栅源与栅漏的距离相差较大，不利于利用好芯片面积。
但是，从漏区在基底的投影对应区域形核并侧向外延也是可以实现的。这个时候也有利于在漏区形成一些特殊结构来改进某方面的性能。同时在形成源处和栅处的复杂结构之前，可以先优化外延层的晶体质量。这样源处与栅处的复杂结构也可以获得更好的晶体质量、并取得良好的电学特性。不管是从源还是从漏区域形核，都可以依次从源到栅到漏或从漏到栅到源形成所需的堆成布局结构。
发明内容
本申请的基本原理是通过引入P-型Ⅲ-Ⅴ族半导体层，通过掺杂调制技术来调节高电子迁移率晶体管器件电场分布并提高其耐压能力以及实现增强型器件。
本申请提供的高电子迁移率晶体管基本结构是从漏极对应区域开始选区外延生长Ⅲ-Ⅴ族半导体层，通过调制掺杂技术，形成掺杂浓度不同的半导体层区域，并最终形成高电子迁移率晶体管结构。降低了沟道层局部的高电场，改善了电场分布，提高了器件性能和可靠性。
本申请提供的高耐压高电子迁移率晶体管，包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底等器件结构；沟道层位于势垒层和基底之间，沟道层包括P-型Ⅲ-Ⅴ族半导体层，P-型Ⅲ-Ⅴ族半导体层至少部分地位于漏电极和栅电极之间，其不足以显著耗尽除栅电极堆垛外的沟道中的二维电子气，其中形核层对应漏电极区域，漏电极与形核层上方的沟道层电接触，源电极与P-型Ⅲ-Ⅴ族半导体层电接触。
另一方面，上述的器件电极结构可以如下设置：源电极和漏电极均与二维电子气电接触，栅电极位于势垒层之上，独立的体电极在源电极附近与P-型Ⅲ-Ⅴ族半导体层电接触。
另一方面，势垒层和P-型Ⅲ-Ⅴ族半导体层之间还可以插入低掺杂或非故意掺杂Ⅲ-Ⅴ族半导体层。
另一方面，势垒层上可原位生长SiNx钝化层。
另一方面，势垒层上可形成栅介质层。
另一方面，基底上设置一层绝缘层，绝缘层经掩膜、刻蚀等工艺形成开口后，在开口处形成形核层，然后通过侧向外延的方式生长包含P-型Ⅲ-Ⅴ族半导体层在内的外延层结构；或在基底上生长一层形核层，形核层上形成一层绝缘层，绝缘层经掩膜、刻蚀等工艺形成开口暴露出形核层，再通过侧向外延的方式生长包含P-型Ⅲ-Ⅴ族半导体层在内的外延层结构。
另一方面，基底上侧向外延的方式生长外延层结构，以漏电极所在区域为中心，往外扩展，形成以漏电极区域为中心的对称高电子迁移率晶体管结构。
另一方面，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
另一方面，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极和/或体电极。
另一方面，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极和/或体电极。
另一方面，调制P-型Ⅲ-Ⅴ族半导体层上方可以插入低掺杂或非故意掺杂Ⅲ-Ⅴ族半导体层。
另一方面，P-型Ⅲ-Ⅴ族半导体层上方的势垒层可以进一步的覆盖钝化层。
另一方面，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域轻掺杂或不掺杂。
本申请的P-型Ⅲ-Ⅴ族半导体层采用从漏电极对应区域开始进行侧向外延生长，P-型掺杂浓度可以根据需要在生长过程中对掺杂的载气气氛占比进行调节，通过P-型掺杂调节电场分布，可以获得高质量的P-型掺杂及其对AlGaN/GaN异质结界面处二维电子气2DEG的空间调节；并通过调制漏电极、栅电极、源电极下方半导体层的掺杂浓度，利用源电极或体电极控制调制P-型Ⅲ-Ⅴ族半导体层的电位，可以提高高电子迁移率晶体管的耐压能力，实现常关型操作等功能。
附图说明
为了更清楚地说明本申请实施方式的技术方案，下面将对本申请实施方式中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施方式，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施方式提供的一种高耐压高电子迁移率晶体管的基本结构；
图2-图4为本申请实施方式提供的高电子迁移率晶体管形成过程示例图；
图5为本申请实施方式提供的另一种高电子迁移率晶体管形成过程示例图；
图6-图13为本申请实施方式提供的另外几种复杂高电子迁移率晶体管及形成过程图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行描述。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。“上下”等表示相对位置关系，并不表明二者直接紧邻。
本发明的高耐压高电子迁移率晶体管的基本构思是从漏极对应区域开始侧向外延生长，由于选区外延可以实现较高的晶体质量，这比现有的平面式生长具有一定的优势。
在上述基本结构的基础上，通过在侧向外延掺杂并调制掺杂浓度，可以形成下列结构和他们的组合：栅电极堆垛处形成强P-型区域并耗尽该处的二维电子气，实现器件的常关增强型；除了在栅电极堆垛处形成强P-型区域以外，还在源电极附件形成P-型层，该P-型层不会显著耗尽源栅电极间的二维电子气，但可以连接栅电极堆垛处的强P-型区域并且与电极相连接。该电极可以是源电极也可以是独立的体电极。在栅电极与漏电极间形成P-型区域，该P-型区域不会显著耗尽二维电子气但可以改善电场分布、降低最高电场强度。
在本申请的高电子迁移率晶体管高电子迁移率晶体管中，强掺杂的掺杂浓度通常为5E18/cm3以上，轻掺杂的掺杂浓度一般在5E18/cm3以下。在高电子迁移率晶体管中，强掺杂或轻掺杂是相对的，与沟道层/势垒层界面处二维电子气浓度有关。一般的，沟道层/势垒层界面处本征(指不存在掺杂时的情况)二维电子气浓度越高，强掺杂所对应的掺杂浓度越高，轻掺杂也可以具有相对更高的掺杂浓度。反之，本征二维电子气浓度越低，强掺杂所对应的掺杂浓度越低，轻掺杂也因此具有相对更低的掺杂浓度。
请参看图1，图1为本申请实施方式提供的一种高耐压高电子迁移率晶体管的基本结构。其基本结构为在基底101上的绝缘层102和形核层103，绝缘层102和形核层103上的沟道层104，沟道层104可以是P-型半导体层，更具体的可以为P-型Ⅲ-Ⅴ族半导体层，在P-型Ⅲ-Ⅴ族半导体层上的势垒层105，沟道层104和势垒层105异质结的界面处形成二维电子气2DEG，源电极107和漏电极106与二维电子气相连并形成欧姆接触，栅电108极位于势垒层105之上；其中形核层103与漏电极106在基底101上的投影至少部分区域重合，形成以漏电极向外扩展的高电子迁移率晶体管结构。P-型Ⅲ-Ⅴ族半导体层的掺杂浓度较低，P-型Ⅲ-Ⅴ族半导体层不会严重耗尽位于势垒层和P-型Ⅲ-Ⅴ族半导体层界面处的二维电子气，在异质结界面处依然存在较高浓度的二维电子气。Ⅲ-Ⅴ族半导体层一般为氮化物半导体层，P-型Ⅲ-Ⅴ族半导体层至少部分位于栅电极与漏电极和栅电极与源电极之间的二维电子气区域下方，除栅电极堆垛区域以外，P-型Ⅲ-Ⅴ族半导体层耗尽沟道2DEG浓度小于不含P-型Ⅲ-Ⅴ族半导体层时沟道2DEG浓度的80％，也就是至少有20％的二维电子气被保留。位于栅、漏电极之间区域的P-型Ⅲ-Ⅴ族半导体层也会在电场的作用下被部分耗尽，露出本底的负电荷。这些负电荷可以有效地抵消沟道处正电荷与漏极正电荷的影响，调节电场的分布，降低局部电场峰值的强度，提高器件的耐压能力。
图1实施方式提供的高耐压高电子迁移率晶体管可经由图2-4等所示步骤形成。如图2所示，在基底201上形成一层绝缘层202，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层203，再通过侧向外延的方式生长P-型Ⅲ-Ⅴ族半导体层；或如图3中所示，在基底上301外延生长一层形核层302，然后再形成一层绝缘层303，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域304暴露出形核层302，再通过侧向外延的方式在绝缘层的开口区域处的形核层上外延生长P-型Ⅲ-Ⅴ族半导体层。
在某些基底(如Al2O3基底)与工艺条件下，形核层可以在暴露的基底上选择性生长，而在绝缘层上不生长。但在采用硅基底时，通常需要采用AlN作为形核层，但是AlN作为形核层时生长的选择性较差。这时，可以在生长完形核层后刻蚀/去除在绝缘层上的AlN，但在某些生长条件下，AlN在绝缘层上的沉积很少，在绝缘层上无法形成后续氮化物外延层的形核生长基质。除了在形核区生长外，其他区域没有明显的后续P-型Ⅲ-Ⅴ族半导体层的生长，则可以省略去除绝缘层上的AlN的步骤而直接进行后续的生长。
在绝缘层上的AlN由于是多晶或非晶的，在适当的工艺条件下，可以仅在开口区域的单晶AlN上形核生长，而不在绝缘层上的多晶AlN上生长。这时，多晶结构的AlN层在很大程度上起到绝缘作用。
如图4所示，在基底401上形成一层绝缘层402，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层403，先形成缓冲层404，再形成高晶体质量的P-型Ⅲ-Ⅴ族半导体层405作为沟道层。
如图5所示，在基底501上形成一层绝缘层502，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层503，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层504后，再形成一层势垒层505，再在同一沉积设备中原位沉积SiNx钝化层(未图示)，获得低界面缺陷态密度的势垒层/SiNx层。原位SiNx层可以经过掩膜刻蚀工序后仅保留栅电极508下方的SiNx层作为栅介质层509使用，如图5所示，即在同一生长设备中依次生长沟道层、势垒层、原位SiNx层，提高设备使用率并提高生长质量，在势垒层中形成漏电极506和源电极507，漏电极506和源电极507与二维电子气欧姆接触。最终可形成如图5所示的高电子迁移率晶体管结构。
图1和图5以及本申请在后实施方式中所示的高电子迁移率晶体管结构为实现漏电极对应区域侧向外延调制掺杂浓度形成的P-型Ⅲ-Ⅴ族半导体层的基本器件结构，还可以包括在P-型Ⅲ-Ⅴ族半导体层与势垒层之间的插入P-GaN层等低掺杂或非掺杂的Ⅲ-Ⅴ族半导体层、帽层、以及场板、背势垒层、控制沟道电场的附加电极等；栅电极下可存在栅介质层和或p-GaN层等，以上所述结构或现有技术中已公开的其他结构，并不排除在本发明申请的实施方式之外。
如图6-9所示，在基底601-901上形成一层绝缘层602-902，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层603-903，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层604-904。
如图7所示，在侧向外延生长P-型Ⅲ-Ⅴ族半导体层时利用掺杂调制技术，在形核层上先通过侧向外延先形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(704-1)；再形成P-型层-1(704-2)，P型层-1(704-2)为强P-型Ⅲ-Ⅴ族半导体层，利于耗尽对应沟道层中的二维电子气，实现常关型器件；再侧向外延生长Ⅲ-Ⅴ族半导体层第二掺杂区域(704-3)；然后通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(704-1)、强P-型Ⅲ-Ⅴ族半导体层(704-2)、Ⅲ-Ⅴ族半导体层第二掺杂区域(704-3)的调制P-型Ⅲ-Ⅴ族半导体层；再形成沟道层705、势垒层706、原位SiNx层707的叠层结构；形成源电极709、漏电极708和栅电极710，其中栅电极710对应强P-型Ⅲ-Ⅴ族半导体层区域、源电极709大体位于Ⅲ-Ⅴ族半导体层第二掺杂区域(704-3)上方与二维电子气欧姆接触、漏电极在轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(704-1)上方与二维电子气欧姆接触，最终形成如图7所示的高耐压常关型高电子迁移率晶体管结构。
栅电极下方设置的强P-型Ⅲ-Ⅴ族半导体层，可以使得在0栅压下可耗尽95％以上的栅电极堆垛下方的二维电子气，或使得在0栅压下栅电极堆垛下方的二维电子气浓度小于5E11/cm2。
另外，为了加强源电极对Ⅲ-Ⅴ族半导体层第二掺杂区域的控制，进而通过该层控制强P-型Ⅲ-Ⅴ族半导体层的电位，以获得高电子迁移率晶体管稳定的阈值电压。可以如图8所示，在侧向外延生长Ⅲ-Ⅴ族半导体层第二掺杂区域(804-3)时，进行P-型掺杂生长形成P-型Ⅲ-Ⅴ族半导体层，最终形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(804-1)、强P-型Ⅲ-Ⅴ族半导体层(804-2)、P-型Ⅲ-Ⅴ族半导体层(804-3)的调制P-型Ⅲ-Ⅴ族半导体层804结构层，漏电极808在轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(804-1)上方与二维电子气欧姆接触；经由掩膜、刻蚀等工艺以阶梯型的方式暴露出P-型Ⅲ-Ⅴ族半导体层(804-3)和势垒层806，再沉积形成源电极809，这样源电极809的部分区域与二维电子气接触，源电极809的部分区域穿过沟道层805与P-型Ⅲ-Ⅴ族半导体层804-3直接接触，通过源电极与P-型Ⅲ-Ⅴ族半导体层的良好电接触，能更好地控制强P-型Ⅲ-Ⅴ族半导体层804-2的电位，以获得高电子迁移率晶体管稳定的阈值电压。可选地，源电极809与P-型Ⅲ-Ⅴ族半导体层804-3接触的部分，与源电极809与二维电子气接触的部分为物理连接(即共同组成源电极)；或者源电极809与二维电子气接触，与P-型Ⅲ-Ⅴ族半导体层804-3接触的金属材料与源电极809电连接，便于与源电极电位一体控制。
也可以设置栅介质层807，栅介质层可以是原位SiNx，也可以是其他介质如SiO2、high-k等材料，设置在栅电极810下方完全覆盖势垒层806。
与图8所示实施方式不同之处在于，在图9所示实施方式中，与P-型Ⅲ-Ⅴ族半导体层904-3接触的电极是一个不与源电极909连接的独立的体电极911，体电极穿过钝化层、势垒层、沟道层与P-型Ⅲ-Ⅴ族半导体层904-3电连接，源电极909位于沟道层之上，利于源电极电位和P-型Ⅲ-Ⅴ族半导体层904-3的工作电位独立控制，特别是源极电位固定在0电位点时，可以根据关断沟道所需的工作电压或稳定工作电压来独立控制体电极的电位，有利于增强型器件稳定、高效工作。
再如图10所示，在基底1001上形成一层绝缘层1002，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层1003，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层1004，在侧向外延生长P-型Ⅲ-Ⅴ族半导体层时利用掺杂调制技术，在形核层上先通过侧向外延先形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-1)；再形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-2)，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-2)的外延生长时间比图6所示P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(604-2)的外延生长时间短，图10所示形成的P-型Ⅲ-Ⅴ族半导体层第一掺杂区域较窄；再侧向外延生长P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1004-3)；然后通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-1)、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-2)、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1004-3)的调制P-型Ⅲ-Ⅴ族半导体层；再如图11所示形成沟道层1105、势垒层1106、原位SiNx层1107的叠层结构；形成源电极1109、漏电极1108和栅电极1110，其中栅电极1110在横向方向上偏离P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1104-2)、漏电极1108大体位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1104-1)上方的沟道层1105上、源电极1109与轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域接触(与图8所示实施方式采用相同的方式形成源电极)，最终形成如图11所示的高耐压高电子迁移率晶体管结构。
图11所示的高耐压高电子迁移率晶体管，其漏电极对应形核区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于栅电极与漏电极之间的区域，可以改善栅电极下方靠近漏电极侧区域附近的高电场分布，避免局部的电场强度过大导致器件失效。沟道层、原位SiN钝化层、与栅绝缘层等都是可选而非必须的。
如图12所示，与P-型Ⅲ-Ⅴ族半导体层第二掺杂区域接触的电极是独立的体电极，以利于源极电位和P-型Ⅲ-Ⅴ族半导体层的工作电位独立控制，特别是源极电位固定在0电位点时，可以根据关断沟道所需的工作电压或稳定工作电压来独立控制。
与图11所示实施方式不同之处在于，在图12所示实施方式中，与P-型Ⅲ-Ⅴ族半导体层1204-3接触的电极是一个不与源电极1209连接的独立的体电极1211，体电极穿过钝化层、势垒层、沟道层与P-型Ⅲ-Ⅴ族半导体层1204-3电连接，源电极1209位于沟道层之上，利于源电极电位和P-型Ⅲ-Ⅴ族半导体层1204-3的工作电位独立控制，特别是源极电位固定在0电位点时，可以根据关断沟道所需的工作电压或稳定工作电压来独立控制体电极的电位，有利于增强型高电子迁移率晶体管稳定、高效工作。
在降低栅电极下方漏测电场强度，增强高电子迁移率晶体管耐压能力的同时，图11-12所示的高耐压高电子迁移率晶体管可以通过掺杂调制技术与图7-图9所示增强型高电子迁移率晶体管结构相结合，形成如图13所示的具有更高耐压的增强型高电子迁移率晶体管。如图13所示的高电子迁移率晶体管，在基底1301上形成一层绝缘层1302，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层1303，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层1304.在侧向外延生长P-型Ⅲ-Ⅴ族半导体层时利用掺杂调制技术，在侧向外延生长过程中，依次生长轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1304-1)、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1304-2)、强P-型Ⅲ-Ⅴ族半导体层(1304-3)、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1304-4)，强P-型Ⅲ-Ⅴ族半导体层(1304-3)位于栅电极堆垛处，并通过耗尽栅电极堆垛处的局部或全部二维电子气而获得常关型器件。
经由掩膜、刻蚀等工艺以阶梯型的方式暴露出P-型Ⅲ-Ⅴ族半导体层(1304-4)和势垒层1306，再沉积形成源电极1309，这样源电极1309的部分区域与二维电子气接触，源电极1309的部分区域穿过沟道层1305与P-型Ⅲ-Ⅴ族半导体层804-3直接接触，通过源电极1309与P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1304-4)形成良好电接触，并通过P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1304-4)控制强P-型Ⅲ-Ⅴ族半导体层(1304-3)的电位，以获得稳定的阈值电压。P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1304-2)位于栅电极1310与漏电极1308之间的区域，可以改善栅电极下方靠近漏电极侧区域附近的高电场分布，避免局部的电场强度过大导致器件失效。沟道层、原位SiN钝化层、与栅绝缘层等都是可选而非必须的。
另外，与图13所示实施方式有着不同电位控制方式的另一实施方式中，与P-型Ⅲ-Ⅴ族半导体层第二掺杂区域接触的电极是独立的体电极(源电极、体电极连接生长连接方式与图12所示连接方式相同)，以利于源极电位和P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的工作电位独立控制，有利于增强型器件稳定、高效的在高压条件下工作。
以上所述仅为本申请的实施方式而已，并不用于限制本申请的保护范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (18)

1.一种高耐压高电子迁移率晶体管，其包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底；包含P-型Ⅲ-Ⅴ族半导体层的沟道层位于势垒层和基底之间，其中形核层与漏电极在基底上的投影至少部分区域重合，漏电极与沟道层的二维电子气电接触，源电极与P-型Ⅲ-Ⅴ族半导体层电接触，栅电极位于势垒层之上。
2.一种高耐压高电子迁移率晶体管，其包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底；其中形核层与漏电极在基底上的投影至少部分区域重合，包含P-型Ⅲ-Ⅴ族半导体层的沟道层位于势垒层和基底之间，其不足以显著耗尽除栅堆垛外的沟道中的二维电子气，且源电极和漏电极均与二维电子气电接触，栅电极位于势垒层之上，独立的体电极在源电极附近与P-型Ⅲ-Ⅴ族半导体层电接触。
3.根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，势垒层和P-型Ⅲ-Ⅴ族半导体层之间还有一层低掺杂或非故意掺杂Ⅲ-Ⅴ族半导体层。
4.根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，势垒层上原位生长形成SiNx钝化层，栅电极下方设置栅介质层。
5.根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
6.根据权利要求5所述的高电子迁移率晶体管，其特征在于，栅电极下方的强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，使得在0栅压下可耗尽95％以上的栅电极堆垛下方的二维电子气，或使得在0栅压下栅电极堆垛下方的二维电子气浓度小于5E11/cm2。
7.根据权利要求5所述的高电子迁移率晶体管，其特征在于，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度小于5E17/cm3。
8.根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
9.根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方设置漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
10.根据权利要求1所述的高电子迁移率晶体管，其特征在于，源电极与P-型Ⅲ-Ⅴ族半导体层电接触时，源电极的部分区域与二维电子气接触且源电极的部分区域穿过沟道层与P-型Ⅲ-Ⅴ族半导体层直接接触。
11.根据权利要求1所述的高电子迁移率晶体管，其特征在于，源电极与二维电子气电接触时，与P-型Ⅲ-Ⅴ族半导体层接触的金属材料与源电极电连接，便于与源电极电位一体控制。
12.一种制备如权利要求1或权利要求2所述的高电子迁移率晶体管的方法，其特征在于：在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层，P-型Ⅲ-Ⅴ族半导体层在侧向外延生长时按照不同区域掺杂浓度不同形成调制掺杂P-型Ⅲ-Ⅴ族半导体层，侧向外延生长P-型Ⅲ-Ⅴ族半导体层时采用含有氢和/或氯的前驱体混合气氛。
13.根据权利要求12所述的方法，其特征在于，在基底上形成形核层开口的方式为在基底上生长一层形核层，形核层上形成一层绝缘层，绝缘层经掩膜、刻蚀等工艺形成开口暴露出形核层；再通过侧向外延的方式生长包含P-型Ⅲ-Ⅴ族半导体层在内的外延层结构。
14.根据权利要求12所述的方法，其特征在于，从基底上开口处的形核层，以侧向外延的方式生长外延层，以漏电极在基底上的投影区域为中心，往外扩展，形成以漏电极区域为中心的对称高电子迁移率晶体管结构。
15.根据权利要求12所述的方法，其特征在于，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
16.根据权利要求12所述的方法，其特征在于，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
17.根据权利要求12所述的方法，其特征在于，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
18.根据权利要求15-17任一项所述的方法，其特征在于，侧向外延生长含P-型Ⅲ-Ⅴ族半导体层结构时采用含有氢和/或氯的前驱体混合气氛。
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US20150021665A1 (en) * 2013-07-17 2015-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having back-barrier layer and method of making the same
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