WO2021035946A1 - 高耐压高电子迁移率晶体管及其制备方法 - Google Patents

高耐压高电子迁移率晶体管及其制备方法 Download PDF

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WO2021035946A1
WO2021035946A1 PCT/CN2019/115426 CN2019115426W WO2021035946A1 WO 2021035946 A1 WO2021035946 A1 WO 2021035946A1 CN 2019115426 W CN2019115426 W CN 2019115426W WO 2021035946 A1 WO2021035946 A1 WO 2021035946A1
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semiconductor layer
type iii
layer
doped region
group semiconductor
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PCT/CN2019/115426
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English (en)
French (fr)
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黎子兰
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广东致能科技有限公司
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Priority to EP19943513.2A priority Critical patent/EP4006991A4/en
Priority to US17/638,283 priority patent/US20220302292A1/en
Publication of WO2021035946A1 publication Critical patent/WO2021035946A1/zh

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Definitions

  • This application relates to a semiconductor power device, and in particular to a transistor with high withstand voltage and high electron mobility and a preparation method thereof.
  • Group III-V compound semiconductors include at least one group III element and at least one group V element, including but not limited to gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), and indium nitride Aluminum gallium (InAlGaN) and indium gallium nitride (InGaN), etc.; when the V group element is nitrogen (N), group III-V compound semiconductors are also called group III nitride semiconductors, that is, group III nitride semiconductors include Nitrogen and at least one Group III element.
  • Group III nitride semiconductors include but are not limited to GaN, AlGaN, InN, AlN, InGaN, InAlGaN, and the like.
  • High electron mobility transistors use III-V group heterojunction structures, such as group III nitride heterojunctions, to generate two-dimensional electron gas (2DEG) at the interface where group III nitride materials are formed. Allows high current density to pass and has relatively low resistance loss, and gradually realizes that the withstand voltage can be increased to 600V, or even to 1200V.
  • Conventional III-nitride high-electron mobility transistors are usually depletion-type devices. Due to the advantages of high breakdown voltage, high current density and low on-resistance, III-nitride high-electron mobility transistors need to avoid high-electron mobility transistors. In the absence of gate voltage control, the device is turned off to protect the circuit and the load. Therefore, it is desirable to provide III-nitride high electron mobility transistors that are normally-off or enhancement mode transistors.
  • the selection area is delayed outside, and the nucleation area is located at the source.
  • the high electron mobility transistor has a symmetrical structure for the source, with a gate electrode and a drain electrode from the source to both sides.
  • the distance from the source electrode to the gate electrode is usually much smaller than the distance from the gate electrode to the drain electrode.
  • the lateral extension from the source to the gate is much shorter than the distance from the drain to the gate. This is conducive to the realization of the source and the drain by epitaxy.
  • the manufacturing precision of the complex structure at the gate At the same time, the voltage of the source area is very low, and the crystal quality of the nucleation area is relatively poor, so when the source is located in the low-quality area, the influence of the low voltage is minimal.
  • the structure on both sides of the lateral extension is basically symmetrical, which is not conducive to the formation of many asymmetric structures. And if it extends from the gate electrode area to the outside, the distance between the gate source and the gate drain is quite different, which is not conducive to making good use of the chip area.
  • the required stacking layout structure can be formed sequentially from the source to the gate to the drain or from the drain to the gate to the source.
  • the basic principle of this application is to adjust the electric field distribution of the high electron mobility transistor device by introducing a P-type III-V group semiconductor layer and through the doping modulation technology to improve its voltage resistance and realize an enhanced device.
  • the basic structure of the high electron mobility transistor provided by this application is to epitaxially grow the III-V group semiconductor layer from the area corresponding to the drain electrode, and through the modulation doping technology, the semiconductor layer area with different doping concentration is formed, and finally high electron mobility is formed Rate transistor structure. This reduces the local high electric field of the channel layer, improves the electric field distribution, and improves the performance and reliability of the device.
  • the high voltage and high electron mobility transistor includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, a substrate and other device structures; the channel layer is located in the barrier Between the layer and the substrate, the channel layer includes a P-type III-V group semiconductor layer.
  • the P-type III-V group semiconductor layer is at least partially located between the drain electrode and the gate electrode, which is not sufficient to significantly deplete the gate electrode
  • the nucleation layer corresponds to the drain electrode area
  • the drain electrode is in electrical contact with the channel layer above the nucleation layer
  • the source electrode is in electrical contact with the P-type III-V group semiconductor layer.
  • a low-doped or unintentionally doped group III-V semiconductor layer may be inserted between the barrier layer and the P-type III-V group semiconductor layer.
  • a SiNx passivation layer can be grown in situ on the barrier layer, and a gate dielectric layer is provided under the gate electrode.
  • a gate dielectric layer may be formed on the barrier layer.
  • a low-doped or unintentionally doped III-V group semiconductor layer can be inserted above the modulated P-type III-V group semiconductor layer.
  • the barrier layer above the P-type III-V group semiconductor layer may further cover the passivation layer.
  • the first doped region of the lightly doped III-V group semiconductor layer is lightly doped or undoped.
  • the P-type III-V group semiconductor layer includes modulation regions with different doping concentrations, with the nucleation layer region as the center, and the lightly doped III-V group semiconductor layer first doped regions and the strong The first doped region of the P-type III-V group semiconductor layer and the first doped region of the P-type III-V group semiconductor layer.
  • the lightly doped III-V group semiconductor layer forms a drain electrode above the first doped region, which is strong
  • a gate stack structure is correspondingly formed above the first doped region of the P-type III-V group semiconductor layer, and a source electrode is formed above the first doped region of the P-type III-V group semiconductor layer.
  • the first doped region of the strong P-type III-V group semiconductor layer under the gate electrode can deplete more than 95% of the two-dimensional electron gas under the gate electrode stack at 0 gate voltage, or make The two-dimensional electron gas concentration under the gate electrode stack at zero grid pressure is less than 5E11/cm 2 .
  • the doping concentration of the first doped region of the lightly doped III-V group semiconductor layer is less than 5E17/cm 3 .
  • the P-type III-V group semiconductor layer includes modulation regions with different doping concentrations, with the nucleation layer region as the center, and the lightly doped III-V group semiconductor layer first doped regions, P -Type III-V group semiconductor layer first doped region and P-type III-V group semiconductor layer second doped region, lightly doped III-V group semiconductor layer first doped region to form a drain electrode, in the P
  • the second doped region of the -type III-V semiconductor layer is close to the first doped region of the P-type III-V semiconductor layer to form a gate stack structure, that is, the first doped region of the P-type III-V semiconductor layer
  • the doped region is located between the drain electrode and the gate electrode.
  • the doping concentration of the first doped region of the P-type III-V group semiconductor layer is adjustable, which can improve the electric field distribution near the drain side under the gate electrode, and the P-type III- A source electrode is formed above the second doped region of the group V semiconductor layer.
  • the P-type III-V group semiconductor layer includes modulation regions with different doping concentrations, with the nucleation layer region as the center, and the lightly doped III-V group semiconductor layer first doped regions, P -Type III-V group semiconductor layer first doped region, strong P-type III-V group semiconductor layer first doped region, and P-type III-V group semiconductor layer second doped region; lightly doped III- The drain electrode is arranged above the first doped region of the group V semiconductor layer, and the gate stack structure is formed above the first doped region of the strong P-type III-V group semiconductor layer. The first doped region of the P-type III-V group semiconductor layer is formed.
  • the doped region is located between the first doped region of the lightly doped III-V group semiconductor layer and the first doped region of the strong P-type III-V group semiconductor layer, and the first doped region of the P-type III-V group semiconductor layer
  • the doping concentration is adjustable to improve the electric field distribution near the drain side under the gate electrode, and the source electrode is formed above the second doped region of the P-type III-V group semiconductor layer.
  • the source electrode when the source electrode is in electrical contact with the P-type III-V group semiconductor layer, a part of the source electrode is in contact with the two-dimensional electron gas and a part of the source electrode passes through the channel layer and the P-type III-V group semiconductor layer.
  • the semiconductor layer is in direct contact.
  • the metal material in contact with the P-type III-V group semiconductor layer is electrically connected to the source electrode, which facilitates integrated control of the potential of the source electrode.
  • the high withstand voltage and high electron mobility transistor includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer, and a substrate; wherein the nucleation layer and the drain electrode are on the substrate
  • the channel layer containing the P-type III-V group semiconductor layer is located between the barrier layer and the substrate, which is not enough to significantly deplete the two-dimensional electron gas in the channel except for the gate stack
  • the source electrode and the drain electrode are in electrical contact with the two-dimensional electron gas
  • the gate electrode is located on the barrier layer, and the independent body electrode is in electrical contact with the P-type III-V group semiconductor layer near the source electrode.
  • the method for preparing the above-mentioned high electron mobility transistor includes: forming and growing a P-type III-V group semiconductor layer and a P-type III-V group semiconductor layer by lateral epitaxy on the nucleation layer When the layer is epitaxially grown on the side, a modulated doped P-type III-V group semiconductor layer is formed according to different doping concentrations in different regions, and a P-type III-V group semiconductor layer is used for side epitaxial growth with hydrogen and/or chlorine Precursor mixed atmosphere.
  • an insulating layer is provided on the substrate. After the insulating layer has been masked and etched to form an opening, a nucleation layer is formed at the opening, and then the P-type III-V group is grown by lateral epitaxy.
  • the insulating layer is masked, etched and other processes are formed to form an opening to expose the nucleation layer, and then pass
  • the epitaxial layer structure including the P-type III-V group semiconductor layer is grown in a lateral epitaxial manner.
  • the epitaxial layer structure is grown epitaxially on the upper side of the substrate, with the area where the drain electrode is located as the center, and expand outward to form a symmetrical high electron mobility transistor structure with the drain electrode area as the center.
  • the epitaxial layer structure when the epitaxial layer structure is grown epitaxially on the upper side of the substrate, the first doped region of the lightly doped III-V group semiconductor layer and the strong P-type III-V group semiconductor layer are epitaxially formed on the nucleation layer.
  • the first doped region, the first doped region of the P-type III-V group semiconductor layer removes part of the region in the height direction of the III-V group semiconductor layer through a planarization or etching process, exposing the lightly doped III-V group
  • a drain electrode is formed above the first doped region of the lightly doped III-V semiconductor layer, and a gate stack structure is formed above the first doped region of the strong P-type III-V semiconductor layer, and the P-type III-V semiconductor layer is formed above the first doped region.
  • a source electrode is formed above the first doped region of the semiconductor layer.
  • the first doped region of the lightly doped III-V group semiconductor layer is epitaxially formed on the nucleation layer, and then the P-type III-V group is epitaxially formed
  • the first doped region of the semiconductor layer and the second doped region of the P-type III-V semiconductor layer are planarized or etched to remove part of the region in the height direction of the III-V semiconductor layer, exposing lightly doped III- Modulation of the first doped region of the V group semiconductor layer, the first doped region of the P-type III-V group semiconductor layer, and the second doped region of the P-type III-V group semiconductor layer.
  • the P-type III-V group semiconductor layer A drain electrode is formed above the first doped region of the lightly doped III-V group semiconductor layer, and the second doped region of the P-type III-V group semiconductor layer is close to the first doped region of the P-type III-V group semiconductor layer
  • the first doped region of the P-type III-V semiconductor layer is located between the drain electrode and the gate electrode, and the first doped region of the P-type III-V semiconductor layer is doped
  • the concentration can be adjusted to improve the electric field distribution near the drain side under the gate electrode, and the source electrode and/or the body electrode are formed above the second doped region of the P-type III-V group semiconductor layer.
  • the first doped region of the lightly doped III-V group semiconductor layer is epitaxially formed on the nucleation layer, and then the P-type III-V group is epitaxially formed
  • the first doped region of the semiconductor layer, the first doped region of the strong P-type III-V semiconductor layer, the second doped region of the P-type III-V semiconductor layer, the III-V is removed by planarization or etching process Part of the area in the height direction of the group semiconductor layer exposes the first doped area of the lightly doped group III-V semiconductor layer, the first doped area of the P-type group III-V semiconductor layer, and the strong P-type group III-V semiconductor layer Layer first doped area, P-type III-V group semiconductor layer second doped area modulation P-type III-V group semiconductor layer; lightly doped III-V group semiconductor layer above the first doped area to form leakage Extremely, the first doped region of the strong P-type III-
  • a precursor mixed atmosphere containing hydrogen and/or chlorine is used when the P-type III-V group semiconductor layer structure is grown laterally epitaxially.
  • the P-type III-V group semiconductor layer of the present application adopts lateral epitaxial growth starting from the region corresponding to the drain electrode, and the P-type doping concentration can be adjusted according to the need in the growth process of the doped carrier gas atmosphere.
  • the electric field distribution by P-type doping high-quality P-type doping and its spatial adjustment on the two-dimensional electron gas 2DEG at the AlGaN/GaN heterojunction interface can be obtained; and by modulating the drain electrode, gate electrode, and source
  • the doping concentration of the semiconductor layer under the electrode is controlled by the source electrode or the body electrode to modulate the potential of the P-type III-V group semiconductor layer, which can improve the voltage resistance of the high electron mobility transistor and realize functions such as normally-off operation.
  • FIG. 1 is a basic structure of a high withstand voltage and high electron mobility transistor provided by an embodiment of the application;
  • FIGS. 2 to 4 are exemplary diagrams of the formation process of the high electron mobility transistor provided by the embodiments of the present application.
  • FIG. 5 is an example diagram of another formation process of a high electron mobility transistor according to an embodiment of the application.
  • 6 to 13 are diagrams of other types of complex high electron mobility transistors and the formation process provided by the embodiments of the present application.
  • the basic idea of the high withstand voltage and high electron mobility transistor of the present invention is to grow epitaxially from the side corresponding to the drain electrode. Due to the selected area epitaxy, higher crystal quality can be achieved, which has certain advantages over the existing planar growth.
  • a strong P-type region is formed at the gate electrode stack and the two-dimensional electrons there are depleted
  • a P-type layer is also formed near the source electrode, and the P-type layer will not significantly deplete the gap between the source and gate electrodes.
  • the two-dimensional electron gas but it can connect to the strong P-type area at the gate electrode stack and connect with the electrode.
  • the electrode can be a source electrode or an independent body electrode.
  • a P-type region is formed between the gate electrode and the drain electrode. The P-type region does not significantly deplete the two-dimensional electron gas but can improve the electric field distribution and reduce the maximum electric field intensity.
  • the doping concentration of strong doping is generally above 5E18/cm 3 and the doping concentration of light doping is generally below 5E18/cm 3 .
  • strong doping or light doping is relative, and it is related to the two-dimensional electron gas concentration at the channel layer/barrier layer interface.
  • the higher the intrinsic concentration of the two-dimensional electron gas at the channel layer/barrier layer interface (when there is no doping) the higher the doping concentration corresponding to the strong doping, and the light doping can also have Relatively higher doping concentration.
  • the lower the intrinsic two-dimensional electron gas concentration the lower the doping concentration corresponding to the strong doping, and therefore the light doping has a relatively lower doping concentration.
  • FIG. 1 is a basic structure of a high voltage high electron mobility transistor provided by an embodiment of the present application. Its basic structure is an insulating layer 102 and a nucleation layer 103 on a substrate 101, and a channel layer 104 on the insulating layer 102 and the nucleation layer 103.
  • the channel layer 104 can be a P-type semiconductor layer, and more specifically can be
  • the P-type III-V group semiconductor layer forms a two-dimensional electron gas 2DEG at the interface of the barrier layer 105 on the P-type III-V group semiconductor layer, the channel layer 104 and the barrier layer 105 heterojunction, the source
  • the electrode 107 and the drain electrode 106 are connected to the two-dimensional electron gas and form an ohmic contact.
  • the gate electrode 108 is located on the barrier layer 105; wherein the projection of the nucleation layer 103 and the drain electrode 106 on the substrate 101 overlaps at least part of the area to form High electron mobility transistor structure in which the drain electrode expands outward.
  • the doping concentration of the P-type III-V semiconductor layer is relatively low, and the P-type III-V semiconductor layer will not seriously deplete the two-dimensional electrons located at the interface between the barrier layer and the P-type III-V semiconductor layer There is still a relatively high concentration of two-dimensional electron gas at the interface of the heterojunction.
  • the III-V group semiconductor layer is generally a nitride semiconductor layer, and the P-type III-V group semiconductor layer is at least partially located under the two-dimensional electron gas region between the gate electrode and the drain electrode and the gate electrode and the source electrode, Except for the gate electrode stacking area, the P-type III-V group semiconductor layer depletion channel 2DEG concentration is less than 80% of the channel 2DEG concentration without the P-type III-V group semiconductor layer, that is, at least 20% The two-dimensional electron gas is retained.
  • the P-type III-V group semiconductor layer located in the region between the gate and drain electrodes will also be partially depleted under the action of the electric field, exposing the background negative charges. These negative charges can effectively offset the influence of the positive charges at the channel and the positive charges on the drain electrode, adjust the distribution of the electric field, reduce the intensity of the local electric field peaks, and improve the voltage resistance of the device.
  • the high withstand voltage and high electron mobility transistor provided in the embodiment of FIG. 1 can be formed through the steps shown in FIGS. 2 to 4 and so on.
  • an insulating layer 202 is formed on the substrate 201, an opening area is formed on the insulating layer through processes such as masking and etching, and the opening area of the insulating layer is epitaxially
  • the nucleation layer 203 is grown, and then the P-type III-V group semiconductor layer is grown by lateral epitaxy; or in a possible implementation, as shown in FIG.
  • a layer 301 is epitaxially grown on the substrate The core layer 302, and then an insulating layer 303 is formed, an opening area 304 is formed on the insulating layer through masking, etching and other processes to expose the nucleation layer 302, and then the opening area of the insulating layer is formed by lateral extension.
  • a P-type III-V group semiconductor layer is epitaxially grown on the nucleation layer.
  • the nucleation layer can be selectively grown on the exposed substrate, but not on the insulating layer.
  • AlN is usually used as the nucleation layer, but the growth selectivity is poor when AlN is used as the nucleation layer.
  • the AlN on the insulating layer can be etched/removed after the nucleation layer has been grown.
  • the deposition of AlN on the insulating layer is very small, and subsequent nitride epitaxy cannot be formed on the insulating layer Layer of nucleation growth substrate. Except for the growth in the nucleation region, there is no obvious subsequent growth of the P-type III-V group semiconductor layer in other regions, so the step of removing the AlN on the insulating layer can be omitted and the subsequent growth can be directly performed.
  • the AlN on the insulating layer is polycrystalline or amorphous, under appropriate process conditions, it can only nucleate and grow on the single crystal AlN in the open area, and not on the polycrystalline AlN on the insulating layer. Grow. At this time, the polycrystalline AlN layer plays an insulating role to a large extent.
  • an insulating layer 402 is formed on the substrate 401, and an opening area is formed on the insulating layer through processes such as masking and etching.
  • the nucleation layer 403 is epitaxially grown, the buffer layer 404 is formed first, and then the P-type III-V group semiconductor layer 405 with high crystal quality is formed as the channel layer.
  • an insulating layer 502 is formed on the substrate 501, and an opening area is formed on the insulating layer through processes such as masking and etching.
  • the nucleation layer 503 is epitaxially grown.
  • a barrier layer 505 is formed, and then SiNx passivation is deposited in situ in the same deposition equipment Layer (not shown) to obtain a barrier layer/SiNx layer with a low interface defect state density.
  • the in-situ SiNx layer can be used as the gate dielectric layer 509 by leaving only the SiNx layer under the gate electrode 508 after the mask etching process, as shown in FIG. 5, that is, the channel layer, the barrier layer, and the barrier layer are sequentially grown in the same growth device.
  • the in-situ SiNx layer can improve the utilization rate of the device and the growth quality, and then the drain electrode 506 and the source electrode 507 are formed in the barrier layer, and the drain electrode 506 and the source electrode 507 are in ohmic contact with the two-dimensional electron gas.
  • a high electron mobility transistor structure as shown in FIG. 5 can be formed.
  • the structure of the high electron mobility transistor shown in FIGS. 1 and 5 and the subsequent embodiments of the present application is the basic device structure of the P-type III-V group semiconductor layer formed by epitaxially modulating the doping concentration on the side of the drain electrode corresponding to the region
  • the high electron mobility transistor may also include a low-doped or non-doped P-GaN layer inserted between the P-type III-V group semiconductor layer and the barrier layer.
  • Group III-V semiconductor layer cap layer, field plate, back barrier layer, additional electrode for controlling the channel electric field, etc.; under the gate electrode, there may be a gate dielectric layer and/or p-GaN layer, etc., the above-mentioned structure or Other structures disclosed in the prior art are not excluded from the embodiments of the present application.
  • an insulating layer 602-902 is formed on the substrate 601-901, and an opening area is formed on the insulating layer through processes such as masking and etching.
  • Nucleation layers 603-903 are epitaxially grown at the opening area of the insulating layer, and P-type III-V group semiconductor layers 604-904 are grown on the nucleation layer by lateral epitaxy.
  • the doping modulation technology is used when the P-type III-V group semiconductor layer is grown on the side epitaxial layer, and the lightly doped III-V layer is first formed on the nucleation layer through the side epitaxy.
  • the upper part is in ohmic contact with the two-dimensional electron gas
  • the drain electrode is in ohmic contact with the two-dimensional electron gas above the first doped region (704-1) of the lightly doped group III-V semiconductor layer, and finally forms as shown in FIG. 7 High-voltage normally-off transistor structure with high electron mobility.
  • the strong P-type III-V group semiconductor layer disposed under the gate electrode can deplete more than 95% of the two-dimensional electron gas under the gate electrode stack at 0 gate voltage, or make it
  • the two-dimensional electron gas concentration under the depressed gate electrode stack is less than 5E11/cm 2 .
  • the P-type doping growth is performed to form the P-type III-V group semiconductor layer, and finally form Lightly doped III-V group semiconductor layer first doped region (804-1), strong P-type III-V group semiconductor layer (804-2), P-type III-V group semiconductor layer (804-3)
  • the modulated P-type III-V group semiconductor layer 804 structure layer, the drain electrode 808 is in ohmic contact with the two-dimensional electron gas above the first doped region (804-1) of the lightly doped group III-V semiconductor layer;
  • the P-type III-V group semiconductor layer (804-3) and the barrier layer 806 are exposed in a stepwise manner by processes such as etching, etching, etc., and then deposited to form the source electrode 809, so that a part of the source electrode 809 is connected to the two-dimensional electron Gas contact, a part of the source electrode 809 passes through the channel layer 805 and directly contacts the P
  • the potential of the strong P-type III-V group semiconductor layer 804-2 is better controlled to obtain a stable threshold voltage of the high electron mobility transistor.
  • the part where the source electrode 809 is in contact with the P-type III-V group semiconductor layer 804-3, and the part where the source electrode 809 is in contact with the two-dimensional electron gas are physically connected (that is, the source electrode is formed together); or 809 is in contact with the two-dimensional electron gas, and the metal material in contact with the P-type III-V group semiconductor layer 804-3 is electrically connected to the source electrode 809, which facilitates integrated control of the source electrode potential.
  • a gate dielectric layer 807 may also be provided.
  • the gate dielectric layer may be in-situ SiNx, or other dielectric materials such as SiO 2 , high-k, etc., which are provided under the gate electrode 810 to completely cover the barrier layer 806.
  • the electrode in contact with the P-type III-V group semiconductor layer 904-3 is an independent body electrode that is not connected to the source electrode 909
  • the body electrode passes through the passivation layer, the barrier layer, and the channel layer to be electrically connected to the P-type III-V group semiconductor layer 904-3.
  • the source electrode 909 is located on the channel layer, which facilitates the source electrode potential and P-
  • the working potential of the type III-V group semiconductor layer 904-3 is independently controlled, especially when the source potential is fixed at 0 potential point, the potential of the body electrode can be independently controlled according to the working voltage required to turn off the channel or the stable working voltage , Which is conducive to the stable and efficient operation of enhanced devices.
  • an insulating layer 1002 is formed on the substrate 1001, and an opening area is formed on the insulating layer through processes such as masking and etching.
  • a nucleation layer 1003 is epitaxially grown, and a P-type III-V group semiconductor layer 1004 is epitaxially grown on the nucleation layer, and a doping modulation technique is used when the P-type III-V group semiconductor layer is epitaxially grown on the side ,
  • the first doped region (1004-1) of the lightly doped III-V group semiconductor layer is formed on the nucleation layer by side epitaxy; and then the first doped region (1004-1) of the P-type III-V group semiconductor layer is formed 1004-2), the epitaxial growth time of the first doped region (1004-2) of the P-type III-V semiconductor layer is longer than that of the first doped region (604- 2)
  • the epitaxial growth time is short.
  • the first doped region of the P-type III-V semiconductor layer formed as shown in FIG. 10 is narrow; the second doped region of the P-type III-V semiconductor layer is then epitaxially grown. (1004-3); then remove part of the region in the height direction of the III-V group semiconductor layer through a planarization or etching process, exposing the lightly doped III-V group semiconductor layer first doped region (1004-1), P -Modulated P-type III-V semiconductor layer in the first doped region (1004-2) of the type III-V semiconductor layer and the second doped region (1004-3) of the P-type III-V semiconductor layer; Then, as shown in FIG.
  • a stacked structure of the channel layer 1105, the barrier layer 1106, and the in-situ SiNx layer 1107 is formed; the source electrode 1109, the drain electrode 1108 and the gate electrode 1110 are formed, wherein the gate electrode 1110 deviates from P in the lateral direction.
  • the first doped region (1104-2) of the -type III-V semiconductor layer and the drain electrode 1108 are generally located on the channel layer 1105 above the first doped region (1104-1) of the lightly doped III-V semiconductor layer
  • the source electrode 1109 is in contact with the first doped region of the lightly doped III-V group semiconductor layer (the source electrode is formed in the same manner as the embodiment shown in FIG. 8), and finally the high withstand voltage and high electron as shown in FIG. 11 are formed. Mobility transistor structure.
  • the drain electrode corresponds to the nucleation region
  • the first doped region of the P-type III-V group semiconductor layer is located in the region between the gate electrode and the drain electrode, which can improve the gate
  • the high electric field distribution near the drain electrode side area under the electrode avoids the local electric field intensity from being too large and causing the device to fail.
  • the channel layer, the in-situ SiN passivation layer, and the gate insulating layer are all optional but not necessary.
  • the electrode contacting the second doped region of the P-type III-V semiconductor layer is an independent body electrode to facilitate the source potential and the P-type III-V semiconductor layer.
  • Independent control of the working potential especially when the source potential is fixed at the 0 potential point, can be independently controlled according to the working voltage or stable working voltage required to turn off the channel.
  • the electrode in contact with the P-type III-V group semiconductor layer 1204-3 is an independent body electrode that is not connected to the source electrode 1209. 1211.
  • the body electrode passes through the passivation layer, the barrier layer, and the channel layer and is electrically connected to the P-type III-V group semiconductor layer 1204-3.
  • the source electrode 1209 is located on the channel layer, which is beneficial to the source electrode potential and P-
  • the working potential of the type III-V group semiconductor layer 1204-3 is independently controlled, especially when the source potential is fixed at 0 potential point, the potential of the body electrode can be independently controlled according to the working voltage required to turn off the channel or the stable working voltage , which is conducive to the stable and efficient operation of enhanced high electron mobility transistors.
  • the high voltage and high electron mobility transistor shown in Figure 11-12 can be compared with Figure 7-9 through the doping modulation technique.
  • the structure of the shown enhancement type high electron mobility transistors is combined to form an enhancement type high electron mobility transistor having a higher withstand voltage as shown in FIG. 13.
  • an insulating layer 1302 is formed on a substrate 1301, an opening area is formed on the insulating layer through processes such as masking and etching, and nucleation is epitaxially grown at the opening area of the insulating layer
  • a P-type III-V group semiconductor layer 1304 is formed and grown on the nucleation layer by lateral epitaxy.
  • the doping modulation technology is used when the P-type III-V group semiconductor layer is grown on the side epitaxial growth process, and the first doped region (1304-1) of the lightly doped group III-V semiconductor layer is sequentially grown during the side epitaxial growth process.
  • P-type III-V group semiconductor layer first doping region (1304-2), strong P-type III-V group semiconductor layer (1304-3), P-type III-V group semiconductor layer second doping Area (1304-4), the strong P-type III-V group semiconductor layer (1304-3) is located at the gate electrode stack, and is normally closed by depleting part or all of the two-dimensional electron gas at the gate electrode stack Type device.
  • the P-type III-V group semiconductor layer (1304-4) and the barrier layer 1306 are exposed in a stepwise manner through masking, etching and other processes, and then deposited to form the source electrode 1309, so that part of the source electrode 1309 is in contact with Two-dimensional electron gas contact. Part of the source electrode 1309 passes through the channel layer 1305 to directly contact the P-type III-V group semiconductor layer 804-3, and the source electrode 1309 is in direct contact with the P-type III-V group semiconductor layer.
  • the doped region (1304-4) forms a good electrical contact, and the strong P-type III-V semiconductor layer (1304-3) is controlled by the second doped region (1304-4) of the P-type III-V semiconductor layer The potential to obtain a stable threshold voltage.
  • the first doped region (1304-2) of the P-type III-V semiconductor layer is located in the region between the gate electrode 1310 and the drain electrode 1308, which can improve the high electric field distribution near the drain electrode side under the gate electrode and avoid localization Excessive electric field strength causes the device to fail.
  • the channel layer, the in-situ SiN passivation layer, and the gate insulating layer are all optional but not necessary.
  • the electrode in contact with the second doped region of the P-type III-V semiconductor layer is an independent body electrode (source electrode, body electrode).
  • the connection growth connection method is the same as that shown in Fig. 12), in order to facilitate independent control of the source potential and the working potential of the second doped region of the P-type III-V group semiconductor layer, which is conducive to the stable and efficient operation of the enhanced device. Work under high pressure conditions.

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Abstract

一种高耐压高电子迁移率晶体管及其制备方法。高耐压高电子迁移率晶体管，其包含栅电极（108）、源电极（107）、漏电极（106）、势垒层（105）、沟道层（104）、形核层（103）、基底（101）；沟道层（104）位于势垒层（105）和基底（101）之间，沟道层（104）包括P-型Ⅲ-Ⅴ族半导体层，其中形核层（103）与漏电极（106）在基底（101）上的投影至少部分区域重合，漏电极（106）与沟道层（104）的二维电子气电接触，源电极（107）与P-型Ⅲ-Ⅴ族半导体层电接触，栅电极（108）位于势垒层（105）之上。

Description

高耐压高电子迁移率晶体管及其制备方法
相关申请的交叉引用
本申请要求于2019年08月30日提交中国专利局的申请号为201910826836X，名称为“一种高耐压的高电子迁移率晶体管”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体功率器件，具体而言，涉及一种高耐压高电子迁移率晶体管及其制备方法。
背景技术
Ⅲ-Ⅴ族化合物半导体包括至少一个III族元素和至少一种V族元素，包括但不局限于氮化镓(GaN)、氮化铝镓(AlGaN)、砷化镓(GaAs)、氮化铟铝镓(InAlGaN)和氮化铟镓(InGaN)等；当V族元素为氮元素(N)时，Ⅲ-Ⅴ族化合物半导体又称为III族氮化物半导体，也即III族氮化物半导体包括氮和至少一个III族元素，III族氮化物半导体包括但不局限于GaN、AlGaN、InN、AlN、InGaN和InAlGaN等。
高电子迁移率晶体管(HEMT)利用Ⅲ-Ⅴ族异质结结构，如III族氮化物异质结，在III族氮化物材料的形成异质结界面处产生二维电子气(2DEG)，其允许通过高的电流密度并具备相对较低的电阻损耗，并逐步实现了耐压能力提升至600V，甚至达到1200V。常规III族氮化物高电子迁移率晶体管通常为耗尽型器件，由于高击穿电压、高电流密度和低导通电阻等优点，III族氮化物高电子迁移率晶体管需要避免高电子迁移率晶体管在没有栅压控制的情况 下器件关闭以保护电路和负载。因此，希望提供III族氮化物高电子迁移率晶体管是常断的，或是增强模式晶体管。
这样，有需要克服在现有技术中的缺点和不足，制造高耐压高电子迁移率晶体管、增强型III-V族高电子迁移率晶体管。
在相关专利申请中我们已经提出通过P-型掩埋层等结构实现常关型器件和对更高的耐压能力进行了描述，对于相关的器件结构也有了详尽的描述。但在具体的实施过程中，选区外延时，形核区域位于源的位置。这主要时因为高电子迁移率晶体管对于源来说是对称结构，从源到两侧都各有栅电极和漏电极。同时，从源电极到栅电极的距离比从栅电极到漏电极的距离通常要小很多，从源到栅做侧向外延比从漏到栅要距离短很多，这有利于通过外延实现源和栅处的复杂结构的制作精度。同时，源区域的电压很低，而形核区的晶体质量相对较差，所以在源位于低质量区域的时候由于电压低而影响最小。
相比较的，如果从栅或其他区域形核并侧向外延，那么侧向外延的两侧结构是基本对称的，不利于形成很多非对称结构。并且如果是从栅电极区域开始侧向外延，那么由于栅源与栅漏的距离相差较大，不利于利用好芯片面积。
但是，从漏区在基底的投影对应区域形核并侧向外延也是可以实现的。这个时候也有利于在漏区形成一些特殊结构来改进某方面的性能。同时在形成源处和栅处的复杂结构之前，可以先优化外延层的晶体质量。这样源处与栅处的复杂结构也可以获得更好的晶体质量、并取得良好的电学特性。不管是从源还是从漏区域形核，都可以依次从源到栅到漏或从漏到栅到源形成所需的堆成布局结构。
发明内容
本申请的基本原理是通过引入P-型Ⅲ-Ⅴ族半导体层，通过掺杂调制技术来调节高电子迁移率晶体管器件的电场分布并提高其耐压能力以及实现增强型器件。
本申请提供的高电子迁移率晶体管基本结构是从漏电极对应区域开始选区外延生长Ⅲ-Ⅴ族半导体层，通过调制掺杂技术，形成掺杂浓度不同的半导体层区域，并最终形成高电子迁移率晶体管结构。这样降低了沟道层局部的高电场，改善了电场分布，提高了器件性能和可靠性。
第一方面，本申请提供的高耐压高电子迁移率晶体管，包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底等器件结构；沟道层位于势垒层和基底之间，沟道层包括P-型Ⅲ-Ⅴ族半导体层，P-型Ⅲ-Ⅴ族半导体层至少部分地位于漏电极和栅电极之间，其不足以显著耗尽除栅电极堆垛外的沟道中的二维电子气，其中形核层对应漏电极区域，漏电极与形核层上方的沟道层电接触，源电极与P-型Ⅲ-Ⅴ族半导体层电接触。
可选地，势垒层和P-型Ⅲ-Ⅴ族半导体层之间还可以插入低掺杂或非故意掺杂Ⅲ-Ⅴ族半导体层。
可选地，势垒层上可原位生长SiNx钝化层，栅电极下方设置栅介质层。
可选地，势垒层上可形成栅介质层。
可选地，调制P-型Ⅲ-Ⅴ族半导体层上方可以插入低掺杂或非故意掺杂Ⅲ-Ⅴ族半导体层。
可选地，P-型Ⅲ-Ⅴ族半导体层上方的势垒层可以进一步的覆盖钝化层。
可选地，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域轻掺杂或不掺杂。
可选地，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ- Ⅴ族半导体层第一掺杂区域和P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
可选地，栅电极下方的强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，使得在0栅压下可耗尽95％以上的栅电极堆垛下方的二维电子气，或使得在0栅压下栅电极堆垛下方的二维电子气浓度小于5E11/cm 2。
可选地，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度小于5E17/cm 3。
可选地，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域和P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
可选地，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域和P-型Ⅲ-Ⅴ族半导体层第二掺杂区域；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方设置漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂 区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
可选地，源电极与P-型Ⅲ-Ⅴ族半导体层电接触时，源电极的部分区域与二维电子气接触且源电极的部分区域穿过沟道层与P-型Ⅲ-Ⅴ族半导体层直接接触。
可选地，源电极与二维电子气电接触时，与P-型Ⅲ-Ⅴ族半导体层接触的金属材料与源电极电连接，便于与源电极电位一体控制。
第二方面，本申请提供的高耐压高电子迁移率晶体管，包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底；其中形核层与漏电极在基底上的投影至少部分区域重合，包含P-型Ⅲ-Ⅴ族半导体层的沟道层位于势垒层和基底之间，其不足以显著耗尽除栅堆垛外的沟道中的二维电子气，且源电极和漏电极均与二维电子气电接触，栅电极位于势垒层之上，独立的体电极在源电极附近与P-型Ⅲ-Ⅴ族半导体层电接触。
第三方面，本申请提供的制备上述的高电子迁移率晶体管的方法，包括：在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层，P-型Ⅲ-Ⅴ族半导体层在侧向外延生长时按照不同区域掺杂浓度不同形成调制掺杂P-型Ⅲ-Ⅴ族半导体层，侧向外延生长P-型Ⅲ-Ⅴ族半导体层时采用含有氢和/或氯的前驱体混合气氛。
可选地，基底上设置一层绝缘层，绝缘层经掩膜、刻蚀等工艺形成开口后，在开口处形成形核层，然后通过侧向外延的方式生长包含P-型Ⅲ-Ⅴ族半导体层在内的外延层结构；或在基底上生长一层形核层，形核层上形成一层绝缘层，绝缘层经掩膜、刻蚀等工艺形成开口暴露出形核层，再通过侧向外延的方式生长包含P-型Ⅲ-Ⅴ族半导体层在内的外延层结构。
可选地，基底上侧向外延的方式生长外延层结构，以漏电极所在区域为中心，往外扩展，形成以漏电极区域为中心的对称高电子迁移率晶体管结构。
可选地，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
可选地，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极和/或体电极。
可选地，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第 一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极和/或体电极。
可选地，侧向外延生长含P-型Ⅲ-Ⅴ族半导体层结构时采用含有氢和/或氯的前驱体混合气氛。
本申请的P-型Ⅲ-Ⅴ族半导体层采用从漏电极对应区域开始进行侧向外延生长，P-型掺杂浓度可以根据需要在生长过程中对掺杂的载气气氛占比进行调节，通过P-型掺杂调节电场分布，可以获得高质量的P-型掺杂及其对AlGaN/GaN异质结界面处二维电子气2DEG的空间调节；并通过调制漏电极、栅电极、源电极下方半导体层的掺杂浓度，利用源电极或体电极控制调制P-型Ⅲ-Ⅴ族半导体层的电位，可以提高高电子迁移率晶体管的耐压能力，实现常关型操作等功能。
附图说明
为了更清楚地说明本申请实施方式的技术方案，下面将对本申请实施方式中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某 些实施方式，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施方式提供的一种高耐压高电子迁移率晶体管的基本结构；
图2-图4为本申请实施方式提供的高电子迁移率晶体管形成过程示例图；
图5为本申请实施方式提供的另一种高电子迁移率晶体管形成过程示例图；
图6-图13为本申请实施方式提供的另外几种复杂高电子迁移率晶体管及形成过程图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行描述。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。“上下”等表示相对位置关系，并不表明二者直接紧邻。
本发明的高耐压高电子迁移率晶体管的基本构思是从漏电极对应区域开始侧向外延生长，由于选区外延可以实现较高的晶体质量，这比现有的平面式生长具有一定的优势。
在上述基本结构的基础上，通过在侧向外延掺杂并调制掺杂浓度，可以形成下列结构和他们的组合：栅电极堆垛处形成强P-型区域并耗尽该处的二维电子气，实现器件的常关增强型；除了在栅电极堆垛处形成强P-型区域以外， 还在源电极附件形成P-型层，该P-型层不会显著耗尽源栅电极间的二维电子气，但可以连接栅电极堆垛处的强P-型区域并且与电极相连接。该电极可以是源电极也可以是独立的体电极。在栅电极与漏电极间形成P-型区域，该P-型区域不会显著耗尽二维电子气但可以改善电场分布、降低最高电场强度。
在本申请的高电子迁移率晶体管高电子迁移率晶体管中，强掺杂的掺杂浓度通常为5E18/cm 3以上，轻掺杂的掺杂浓度一般在5E18/cm 3以下。在高电子迁移率晶体管中，强掺杂或轻掺杂是相对的，与沟道层/势垒层界面处二维电子气浓度有关。一般的，沟道层/势垒层界面处本征(指不存在掺杂时的情况)二维电子气浓度越高，强掺杂所对应的掺杂浓度越高，轻掺杂也可以具有相对更高的掺杂浓度。反之，本征二维电子气浓度越低，强掺杂所对应的掺杂浓度越低，轻掺杂也因此具有相对更低的掺杂浓度。
请参看图1，图1为本申请实施方式提供的一种高耐压高电子迁移率晶体管的基本结构。其基本结构为在基底101上的绝缘层102和形核层103，绝缘层102和形核层103上的沟道层104，沟道层104可以是P-型半导体层，更具体的可以为P-型Ⅲ-Ⅴ族半导体层，在P-型Ⅲ-Ⅴ族半导体层上的势垒层105，沟道层104和势垒层105异质结的界面处形成二维电子气2DEG，源电极107和漏电极106与二维电子气相连并形成欧姆接触，栅电极108位于势垒层105之上；其中形核层103与漏电极106在基底101上的投影至少部分区域重合，形成以漏电极向外扩展的高电子迁移率晶体管结构。P-型Ⅲ-Ⅴ族半导体层的掺杂浓度较低，P-型Ⅲ-Ⅴ族半导体层不会严重耗尽位于势垒层和P-型Ⅲ-Ⅴ族半导体层界面处的二维电子气，在异质结界面处依然存在较高浓度的二维电子气。可选地，Ⅲ-Ⅴ族半导体层一般为氮化物半导体层，P-型Ⅲ-Ⅴ族半导体层至少部分位于栅电极与漏电极和栅电极与源电极之间的二维电子气区域下方， 除栅电极堆垛区域以外，P-型Ⅲ-Ⅴ族半导体层耗尽沟道2DEG浓度小于不含P-型Ⅲ-Ⅴ族半导体层时沟道2DEG浓度的80％，也就是至少有20％的二维电子气被保留。位于栅、漏电极之间区域的P-型Ⅲ-Ⅴ族半导体层也会在电场的作用下被部分耗尽，露出本底的负电荷。这些负电荷可以有效地抵消沟道处正电荷与漏电极正电荷的影响，调节电场的分布，降低局部电场峰值的强度，以及提高器件的耐压能力。
在一些可能的实施例中，图1实施方式提供的高耐压高电子迁移率晶体管可经由图2-图4等所示步骤形成。在一种可能的实现方式中，如图2所示，在基底201上形成一层绝缘层202，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层203，再通过侧向外延的方式生长P-型Ⅲ-Ⅴ族半导体层；或在一种可能的实现方式中，如图3中所示，在基底上301外延生长一层形核层302，然后再形成一层绝缘层303，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域304暴露出形核层302，再通过侧向外延的方式在绝缘层的开口区域处的形核层上外延生长P-型Ⅲ-Ⅴ族半导体层。
需要说明的是，在某些基底(如Al 2O 3基底)与工艺条件下，形核层可以在暴露的基底上选择性生长，而在绝缘层上不生长。但在采用硅基底时，通常需要采用AlN作为形核层，但是AlN作为形核层时生长的选择性较差。这时，可以在生长完形核层后刻蚀/去除在绝缘层上的AlN，但在某些生长条件下，AlN在绝缘层上的沉积很少，在绝缘层上无法形成后续氮化物外延层的形核生长基质。除了在形核区生长外，其他区域没有明显的后续P-型Ⅲ-Ⅴ族半导体层的生长，则可以省略去除绝缘层上的AlN的步骤而直接进行后续的生长。
可选地，在绝缘层上的AlN由于是多晶或非晶的，在适当的工艺条件下，可以仅在开口区域的单晶AlN上形核生长，而不在绝缘层上的多晶AlN上生 长。这时，多晶结构的AlN层在很大程度上起到绝缘作用。
在又一种可能的实现方式中，如图4所示，在基底401上形成一层绝缘层402，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层403，先形成缓冲层404，再形成高晶体质量的P-型Ⅲ-Ⅴ族半导体层405作为沟道层。
在又一种可能的实现方式中，如图5所示，在基底501上形成一层绝缘层502，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层503，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层504后，再形成一层势垒层505，再在同一沉积设备中原位沉积SiNx钝化层(未图示)，获得低界面缺陷态密度的势垒层/SiNx层。原位SiNx层可以经过掩膜刻蚀工序后仅保留栅电极508下方的SiNx层作为栅介质层509使用，如图5所示，即在同一生长设备中依次生长沟道层、势垒层、原位SiNx层，可以提高设备使用率并提高生长质量，然后在势垒层中形成漏电极506和源电极507，漏电极506和源电极507与二维电子气欧姆接触。最终可形成如图5所示的高电子迁移率晶体管结构。
图1和图5以及本申请在后实施方式中所示的高电子迁移率晶体管结构为实现漏电极对应区域侧向外延调制掺杂浓度形成的P-型Ⅲ-Ⅴ族半导体层的基本器件结构，可选地，在其他实施例中，高电子迁移率晶体管还可以包括在P-型Ⅲ-Ⅴ族半导体层与势垒层之间的插入P-GaN层等低掺杂或非掺杂的Ⅲ-Ⅴ族半导体层、帽层、以及场板、背势垒层、控制沟道电场的附加电极等；栅电极下可存在栅介质层和/或p-GaN层等，以上所述结构或现有技术中已公开的其他结构，并不排除在本发明申请的实施方式之外。
在又一种可能的实现方式中，如图6-图9所示，在基底601-901上形成一 层绝缘层602-902，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层603-903，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层604-904。
在具体实现时，如图7所示，在侧向外延生长P-型Ⅲ-Ⅴ族半导体层时利用掺杂调制技术，在形核层上先通过侧向外延先形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(704-1)；再形成P-型层-1(704-2)，P型层-1(704-2)为强P-型Ⅲ-Ⅴ族半导体层，利于耗尽对应沟道层中的二维电子气，实现常关型器件；再侧向外延生长Ⅲ-Ⅴ族半导体层第二掺杂区域(704-3)；然后通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(704-1)、强P-型Ⅲ-Ⅴ族半导体层(704-2)、Ⅲ-Ⅴ族半导体层第二掺杂区域(704-3)的调制P-型Ⅲ-Ⅴ族半导体层；再形成沟道层705、势垒层706、原位SiNx层707的叠层结构；形成源电极709、漏电极708和栅电极710，其中栅电极710对应强P-型Ⅲ-Ⅴ族半导体层区域、源电极709大体位于Ⅲ-Ⅴ族半导体层第二掺杂区域(704-3)上方与二维电子气欧姆接触、漏电极在轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(704-1)上方与二维电子气欧姆接触，最终形成如图7所示的高耐压常关型高电子迁移率晶体管结构。
可选地，栅电极下方设置的强P-型Ⅲ-Ⅴ族半导体层，可以使得在0栅压下可耗尽95％以上的栅电极堆垛下方的二维电子气，或使得在0栅压下栅电极堆垛下方的二维电子气浓度小于5E11/cm 2。
另外，为了加强源电极对Ⅲ-Ⅴ族半导体层第二掺杂区域的控制，进而通过该层控制强P-型Ⅲ-Ⅴ族半导体层的电位，以获得高电子迁移率晶体管稳定的阈值电压。可以如图8所示，在侧向外延生长Ⅲ-Ⅴ族半导体层第二掺杂区域(804-3)时，进行P-型掺杂生长形成P-型Ⅲ-Ⅴ族半导体层，最终形成轻掺 杂Ⅲ-Ⅴ族半导体层第一掺杂区域(804-1)、强P-型Ⅲ-Ⅴ族半导体层(804-2)、P-型Ⅲ-Ⅴ族半导体层(804-3)的调制P-型Ⅲ-Ⅴ族半导体层804结构层，漏电极808在轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(804-1)上方与二维电子气欧姆接触；经由掩膜、刻蚀等工艺以阶梯型的方式暴露出P-型Ⅲ-Ⅴ族半导体层(804-3)和势垒层806，再沉积形成源电极809，这样源电极809的部分区域与二维电子气接触，源电极809的部分区域穿过沟道层805与P-型Ⅲ-Ⅴ族半导体层804-3直接接触，通过源电极与P-型Ⅲ-Ⅴ族半导体层的良好电接触，能更好地控制强P-型Ⅲ-Ⅴ族半导体层804-2的电位，以获得高电子迁移率晶体管稳定的阈值电压。可选地，源电极809与P-型Ⅲ-Ⅴ族半导体层804-3接触的部分，与源电极809与二维电子气接触的部分为物理连接(即共同组成源电极)；或者源电极809与二维电子气接触，与P-型Ⅲ-Ⅴ族半导体层804-3接触的金属材料与源电极809电连接，便于与源电极电位一体控制。
此外，也可以设置栅介质层807，栅介质层可以是原位SiNx，也可以是其他介质如SiO 2、high-k等材料，设置在栅电极810下方完全覆盖势垒层806。
与图8所示实施方式不同之处在于，在图9所示实施方式中，与P-型Ⅲ-Ⅴ族半导体层904-3接触的电极是一个不与源电极909连接的独立的体电极911，体电极穿过钝化层、势垒层、沟道层与P-型Ⅲ-Ⅴ族半导体层904-3电连接，源电极909位于沟道层之上，利于源电极电位和P-型Ⅲ-Ⅴ族半导体层904-3的工作电位独立控制，特别是源极电位固定在0电位点时，可以根据关断沟道所需的工作电压或稳定工作电压来独立控制体电极的电位，有利于增强型器件稳定、高效工作。
在又一种可能的实现方式中，再如图10所示，在基底1001上形成一层绝缘层1002，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开 口区域处外延生长形核层1003，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层1004，在侧向外延生长P-型Ⅲ-Ⅴ族半导体层时利用掺杂调制技术，在形核层上先通过侧向外延先形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-1)；再形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-2)，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-2)的外延生长时间比图6所示P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(604-2)的外延生长时间短，图10所示形成的P-型Ⅲ-Ⅴ族半导体层第一掺杂区域较窄；再侧向外延生长P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1004-3)；然后通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-1)、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1004-2)、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1004-3)的调制P-型Ⅲ-Ⅴ族半导体层；再如图11所示形成沟道层1105、势垒层1106、原位SiNx层1107的叠层结构；形成源电极1109、漏电极1108和栅电极1110，其中栅电极1110在横向方向上偏离P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1104-2)、漏电极1108大体位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1104-1)上方的沟道层1105上、源电极1109与轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域接触(与图8所示实施方式采用相同的方式形成源电极)，最终形成如图11所示的高耐压高电子迁移率晶体管结构。
图11所示的高耐压高电子迁移率晶体管，其漏电极对应形核区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于栅电极与漏电极之间的区域，可以改善栅电极下方靠近漏电极侧区域附近的高电场分布，避免局部的电场强度过大导致器件失效。需要说明的是，沟道层、原位SiN钝化层、与栅绝缘层等都是可选而非必须的。
可选地，如图12所示，与P-型Ⅲ-Ⅴ族半导体层第二掺杂区域接触的电极 是独立的体电极，以利于源极电位和P-型Ⅲ-Ⅴ族半导体层的工作电位独立控制，特别是源极电位固定在0电位点时，可以根据关断沟道所需的工作电压或稳定工作电压来独立控制。
与图11所示实施方式不同之处在于，在图12所示实施方式中，与P-型Ⅲ-Ⅴ族半导体层1204-3接触的电极是一个不与源电极1209连接的独立的体电极1211，体电极穿过钝化层、势垒层、沟道层与P-型Ⅲ-Ⅴ族半导体层1204-3电连接，源电极1209位于沟道层之上，利于源电极电位和P-型Ⅲ-Ⅴ族半导体层1204-3的工作电位独立控制，特别是源极电位固定在0电位点时，可以根据关断沟道所需的工作电压或稳定工作电压来独立控制体电极的电位，有利于增强型高电子迁移率晶体管稳定、高效工作。
在降低栅电极下方漏测电场强度，增强高电子迁移率晶体管耐压能力的同时，图11-图12所示的高耐压高电子迁移率晶体管可以通过掺杂调制技术与图7-图9所示增强型高电子迁移率晶体管结构相结合，形成如图13所示的具有更高耐压的增强型高电子迁移率晶体管。如图13所示的高电子迁移率晶体管，在基底1301上形成一层绝缘层1302，经过掩膜、刻蚀等工艺在绝缘层上形成开口区域，在绝缘层的开口区域处外延生长形核层1303，在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层1304。在侧向外延生长P-型Ⅲ-Ⅴ族半导体层时利用掺杂调制技术，在侧向外延生长过程中，依次生长轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域(1304-1)、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1304-2)、强P-型Ⅲ-Ⅴ族半导体层(1304-3)、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1304-4)，强P-型Ⅲ-Ⅴ族半导体层(1304-3)位于栅电极堆垛处，并通过耗尽栅电极堆垛处的局部或全部二维电子气而获得常关型器件。
经由掩膜、刻蚀等工艺以阶梯型的方式暴露出P-型Ⅲ-Ⅴ族半导体层 (1304-4)和势垒层1306，再沉积形成源电极1309，这样源电极1309的部分区域与二维电子气接触，源电极1309的部分区域穿过沟道层1305与P-型Ⅲ-Ⅴ族半导体层804-3直接接触，通过源电极1309与P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1304-4)形成良好电接触，并通过P-型Ⅲ-Ⅴ族半导体层第二掺杂区域(1304-4)控制强P-型Ⅲ-Ⅴ族半导体层(1304-3)的电位，以获得稳定的阈值电压。P-型Ⅲ-Ⅴ族半导体层第一掺杂区域(1304-2)位于栅电极1310与漏电极1308之间的区域，可以改善栅电极下方靠近漏电极侧区域附近的高电场分布，避免局部的电场强度过大导致器件失效。需要说明的是，沟道层、原位SiN钝化层、与栅绝缘层等都是可选而非必须的。
另外，与图13所示实施方式有着不同电位控制方式的另一实施方式中，与P-型Ⅲ-Ⅴ族半导体层第二掺杂区域接触的电极是独立的体电极(源电极、体电极连接生长连接方式与图12所示连接方式相同)，以利于源极电位和P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的工作电位独立控制，有利于增强型器件稳定、高效的在高压条件下工作。
以上所述仅为本申请的实施方式而已，并不用于限制本申请的保护范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
工业实用性：
通过应用本申请的技术方案，可以获得高质量的P-型掺杂及其对AlGaN/GaN异质结界面处二维电子气2DEG的空间调节，还可以提高高电子迁移率晶体管的耐压能力，实现常关型操作等功能。

Claims (18)

  1. 一种高耐压高电子迁移率晶体管，其包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底；包含P-型Ⅲ-Ⅴ族半导体层的沟道层位于势垒层和基底之间，其中形核层与漏电极在基底上的投影至少部分区域重合，漏电极与沟道层的二维电子气电接触，源电极与P-型Ⅲ-Ⅴ族半导体层电接触，栅电极位于势垒层之上。
  2. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，势垒层和P-型Ⅲ-Ⅴ族半导体层之间还有一层低掺杂或非故意掺杂Ⅲ-Ⅴ族半导体层。
  3. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，势垒层上原位生长形成SiNx钝化层，栅电极下方设置栅介质层。
  4. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域和P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
  5. 根据权利要求4所述的高电子迁移率晶体管，其特征在于，栅电极下方的强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，使得在0栅压下可耗尽95％以上的栅电极堆垛下方的二维电子气，或使得在0栅压下栅电极堆垛下方的二维电子气浓度小于5E11/cm 2。
  6. 根据权利要求4所述的高电子迁移率晶体管，其特征在于，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度小于5E17/cm 3。
  7. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域和P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
  8. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，P-型Ⅲ-Ⅴ族半导体层包括不同掺杂浓度的调制区域，以形核层区域为中心，依次向外设置轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域和P-型Ⅲ-Ⅴ族半导体层第二掺杂区域；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方设置漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
  9. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，源电极与P-型Ⅲ-Ⅴ族半导体层电接触时，源电极的部分区域与二维电子气接触且源电极的部分区域穿过沟道层与P-型Ⅲ-Ⅴ族半导体层直接接触。
  10. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，源电极与 二维电子气电接触时，与P-型Ⅲ-Ⅴ族半导体层接触的金属材料与源电极电连接，便于与源电极电位一体控制。
  11. 一种高耐压高电子迁移率晶体管，其包含栅电极、源电极、漏电极、势垒层、沟道层、形核层、基底；其中形核层与漏电极在基底上的投影至少部分区域重合，包含P-型Ⅲ-Ⅴ族半导体层的沟道层位于势垒层和基底之间，其不足以显著耗尽除栅堆垛外的沟道中的二维电子气，且源电极和漏电极均与二维电子气电接触，栅电极位于势垒层之上，独立的体电极在源电极附近与P-型Ⅲ-Ⅴ族半导体层电接触。
  12. 一种制备如权利要求1或权利要求11所述的高电子迁移率晶体管的方法，其特征在于：在形核层上通过侧向外延形成生长P-型Ⅲ-Ⅴ族半导体层，P-型Ⅲ-Ⅴ族半导体层在侧向外延生长时按照不同区域掺杂浓度不同形成调制掺杂P-型Ⅲ-Ⅴ族半导体层，侧向外延生长P-型Ⅲ-Ⅴ族半导体层时采用含有氢和/或氯的前驱体混合气氛。
  13. 根据权利要求12所述的方法，其特征在于，在基底上形成形核层开口的方式为在基底上生长一层形核层，形核层上形成一层绝缘层，绝缘层经掩膜、刻蚀等工艺形成开口暴露出形核层；再通过侧向外延的方式生长包含P-型Ⅲ-Ⅴ族半导体层在内的外延层结构。
  14. 根据权利要求12所述的方法，其特征在于，从基底上开口处的形核层，以侧向外延的方式生长外延层，以漏电极在基底上的投影区域为中心，往外扩展，形成以漏电极区域为中心的对称高电子迁移率晶体管结构。
  15. 根据权利要求12所述的方法，其特征在于，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第一掺杂 区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成源电极。
  16. 根据权利要求12所述的方法，其特征在于，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，在P-型Ⅲ-Ⅴ族半导体层第二掺杂区域靠近P-型Ⅲ-Ⅴ族半导体层第一掺杂区域的部分，形成栅极叠层结构，即P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于漏电极和栅电极之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
  17. 根据权利要求12所述的方法，其特征在于，基底上侧向外延的方式生长外延层结构时，先在形核层上外延形成轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域，再外延形成P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域，通过平坦化或刻蚀工艺去除Ⅲ-Ⅴ族半导体层高度方向上部分区域，暴露出轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第一掺杂区域、强P-型Ⅲ-Ⅴ族半导体层 第一掺杂区域、P-型Ⅲ-Ⅴ族半导体层第二掺杂区域的调制P-型Ⅲ-Ⅴ族半导体层；轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域上方形成漏电极，强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域上方对应形成栅极叠层结构，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域位于轻掺杂Ⅲ-Ⅴ族半导体层第一掺杂区域和强P-型Ⅲ-Ⅴ族半导体层第一掺杂区域之间，P-型Ⅲ-Ⅴ族半导体层第一掺杂区域掺杂浓度可调，可改善栅电极下方靠近漏侧边的电场分布，P-型Ⅲ-Ⅴ族半导体层第二掺杂区域上方形成源电极。
  18. 根据权利要求15-17任一项所述的方法，其特征在于，侧向外延生长含P-型Ⅲ-Ⅴ族半导体层结构时采用含有氢和/或氯的前驱体混合气氛。
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