CN112368829B - 电子模块 - Google Patents

电子模块 Download PDF

Info

Publication number
CN112368829B
CN112368829B CN201880094983.6A CN201880094983A CN112368829B CN 112368829 B CN112368829 B CN 112368829B CN 201880094983 A CN201880094983 A CN 201880094983A CN 112368829 B CN112368829 B CN 112368829B
Authority
CN
China
Prior art keywords
electronic component
connector
substrate
electronic
head
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880094983.6A
Other languages
English (en)
Other versions
CN112368829A (zh
Inventor
池田康亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Publication of CN112368829A publication Critical patent/CN112368829A/zh
Application granted granted Critical
Publication of CN112368829B publication Critical patent/CN112368829B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074Stacked arrangements of non-apertured devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/3701Shape
    • H01L2224/37012Cross-sectional shape
    • H01L2224/37013Cross-sectional shape being non uniform along the connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4009Loop shape
    • H01L2224/40095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101Structure
    • H01L2224/4103Connectors having different sizes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73263Layer and strap connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8412Aligning
    • H01L2224/84136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/84138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842Applying energy for connecting
    • H01L2224/84201Compression bonding
    • H01L2224/84205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842Applying energy for connecting
    • H01L2224/8421Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/84214Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8434Bonding interfaces of the connector
    • H01L2224/84345Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本发明的电子模块,包括:第一基板11;设置在所述第一基板11的一侧的第一电子元件13;设置在所述第一电子元件13的一侧的第一连接体60;设置在所述第一连接体60的一侧的第二电子元件23;以及设置在所述第二电子元件23的一侧的第二连接体70,其中,所述第一电子元件13与所述第二电子元件23在面方向上不重叠。

Description

电子模块
技术领域
本发明涉及一种具有连接体的电子模块。
背景技术
以往,在封装树脂内配置有多个电子元件的电子模块已被普遍认知。这种电子模块被要求实现小型化。作为实现小型化的手段之一,可以考虑采用将电子元件进行叠层的结构。在国际公开公报2016/067383中就公开了这样的结构。
然而,在该国际公开公报2016/067383中,仅仅只提出了将电子元件中包含的半导体元件设置在相向的两块基板上的方案。另外,由于设置两块基板的话会导增加价制造成本以及增大模块在面方向上的尺寸,因此有的顾客要求尽量只采用一块基板的结构。而另一形态,也有顾客考虑到散热的问题,要求采用设置两块基板的结构。
本发明提供了一种电子模块,其在只设置一块基板的情况下就能够实现高散热效果。
发明内容
【概念1】
本发明涉及的电子模块,包括:
第一基板;
第一电子元件,配置在所述第一基板的一侧;
第一连接体,配置在所述第一电子元件的一侧;
第二电子元件,配置在所述第一连接体的一侧;以及
第二连接体,配置在所述第二电子元件的一侧,
其中,所述第一电子元件与所述第二电子元件在面方向上不重叠。
【概念2】
在上述【概念1】所述的电子模块中,
所述电子元件的一侧的面位于比位于所述第二电子元件的另一侧的所述第一连接体的另一侧的面更靠一侧的位置上。
【概念3】
在上述【概念1】所述的电子模块中,
所述第一连接体具有:在其另一侧设置有所述第一电子元件的第一头区域、在其一侧设置有所述第二电子元件的第二头区域、以及在面方向上设置在第一头区域与第二头区域之间的弯曲部。
【概念4】
在上述【概念1】所述的电子模块中,
所述第一连接体具有:第一头部、以及从所述第一头部向另一侧延伸的多个第一柱部,
所述第二连接体具有:第二头部、以及从所述第二头部向另一侧延伸的第二柱部,
所述第二电子元件、一个第一柱部以及所述第二柱部在面方向上重叠,其他的一个或多个第一柱部与第二柱部在面方向上不重叠。
【概念5】
在上述【概念1】所述的电子模块中,进一步包括:
密封部,用于密封所述第一电子元件、所述第一连接体、所述第二电子元件以及所述第二连接体,
其中,所述第一电子元件的一侧仅设置有所述第一连接体以及所述密封部。
【概念6】
在上述【概念1】所述的电子模块中,进一步包括:
密封部,用于密封所述第一电子元件、所述第一连接体、所述第二电子元件以及所述第二连接体;以及
第二基板,设置在所述第二连接体的一侧,
其中,在厚度方向上,所述第二基板与所述第一电子元件之间设置有所述第一连接体以及密封部,或是仅设置有设置在所述第一连接体、所述密封部以及所述第二基板的另一侧的第二导体层。
【概念7】
在上述【概念1】所述的电子模块中,进一步包括:
第二基板,设置在所述第二连接体的一侧,
其中,所述第二基板与所述第一连接体之间设置有间隔件(Spacer)。
【概念8】
在上述【概念1】所述的电子模块中,
所述第一连接体具有:第一头部、以及从所述第一头部延伸的多个第一支撑部,
至少一个第一支撑部发挥电功能,并且至少一个第一支撑部不发挥电功能。
【概念9】
在上述【概念1】所述的电子模块中,
所述第二连接体具有:第二头部、以及从所述第二头部延伸的多个第二支撑部,
至少一个第二支撑部发挥电功能,并且至少一个第二支撑部不发挥电功能。
【概念10】
在上述【概念1】所述的电子模块中,
所述第一连接体具有:第一头部、以及从所述第一头部延伸的多个第一支撑部,
所述第二连接体具有:第二头部、以及从所述第二头部延伸的多个第二支撑部,
所述第一支撑部从所述第一头部在面方向上延伸的方向与所述第二支撑部从所述第二头部在面方向上延伸的方向之间的角度在0度~±45度范围内。
发明效果
在本发明的一种形态中,当采用第一电子元件与第二电子元件在面方向上不重叠的形态的情况下,就能够提高散热效果。另外,由于采用了这种形态,就能够将仅设置一块基板的结构实用化,这样一来,就能够根据实际需要来选择仅设置一块基板的结构和设置两块基板的结构。
附图说明
图1是展示可以在本发明第一实施例中使用的电子模块的密封部内的结构的侧视图。
图2是在本发明第一实施例中使用的电子模块的平面图。
图3是将在本发明第一实施例中使用的电子模块的密封部内的结构放大后的侧视图。
图4是在本发明第一实施例中使用的第一连接体的透视图。
图5是在本发明第一实施例中使用的第一连接体的侧视图。
图6是在本发明第一实施例中使用的第二连接体的平面图。
图7是从另一侧(背面侧)观察在本发明第一实施例中使用的第二连接体的立体图。
图8是展示在本发明第一实施方式中使用的电子模块的外观的立体图。
图9是展示可以在本发明的第一实施例中使用的第一电子元件和第二电子元件的侧视图。
图10(a)是展示在本发明的第二实施方式中使用的电子模块的侧视图,图10(b)是展示在图10(a)中没有设置第二基板的形态的侧视图。
图11(a)是展示在本发明的第三实施方式中可以使用的电子模块的侧视图,图11(b)是展示在图11(a)中没有设置第二基板和间隔件的形态的侧视图。
图12是展示在图1所示的形态中设置第二基板和间隔件后的形态的侧视图。
图13是展示在本发明第四实施例中使用的第一连接体和第二连接体之间的关系的平面图。
具体实施方式
第一实施方式
《构成》
在本实施方式中,“一侧”指的是图1中的上方侧,“另一侧”指的是图1中的下方侧。另外,将图1中的上下方向称为“第一方向”、左右方向称为“第二方向”、纸面的表里方向称为“第三方向”。将包含第二方向以及第三方向的面内方向称为“面方向”。
如图1所示,本实施方式的电子模块包括:第一基板11;设置在第一基板11的一侧的第一电子元件13;设置在第一电子元件13的一侧的第一连接体60;设置在第一连接体60的一侧的第二电子元件23;以及设置在第二电子元件23的一侧的第二连接体70。第一电子元件13与第二电子元件23可以在面方向上不重叠。不过,不限于这种形态,第一电子元件1与第二电子元件23也可以在面方向上重叠。第一电子元件13可以是其一部分或全部在面方向上与第二电子元件23重叠。第二电子元件23可以是其一部分或全部在面方向上与第一电子元件13重叠。另外,也可以不设置第二连接体70。
可以在第一基板11的一侧设置由铜等金属构成的第一导体层12。也可以通过焊锡等导电性粘接剂在该第一导体层12上设置第一电子元件13。
在第一电子元件13与第一连接体60之间、第一连接体60与第二电子元件23之间、以及第二电子元件23与第二连接体70之间,可以设置焊锡等导电性粘接剂(未图示)。
如图3所示,第一电子元件13的一侧的面(图3中的上端面)可以位于比位于第二电子元件23的另一侧的第一连接体60的另一侧的面(图3中的下端面)60b更靠一侧的位置上。在图3所示形态中,第一连接体60的另一侧的面60b即为后述的第一柱部62b的另一侧的面。但是,并不限定于这样的形态,第一电子元件13的一侧的面也可以位于比位于第二电子元件23的另一侧的第一连接体60的另一侧的面60b更靠另一侧(下方侧)的位置上。
第一连接体60可以具有弯曲部69,并在面方向上隔着弯曲部69设置第一电子元件13和第二电子元件23。具体来说,如图4和图5所示,第一连接体60包括:在其另一侧设置有第一电子元件13的第一头区域61a、在其一侧设置有第二电子元件23的第二头区域61b、以及在面方向上设置在第一头区域61a与第二头区域61b之间的弯曲部69。
如图8所示,也可以设置由密封第一电子元件13、第一连接体60、第二电子元件23以及第二连接体70的密封树脂等构成的密封部90。
在电子模块内,也可以是在第二连接体70的一侧以及第一连接体60中设置有第一电子元件13的区域的一侧(第一头区域61a中的一部分一侧)只设置密封部90,且不设置其他部件的形态(参照图3)。
第一电子元件13可以是开关元件,也可以是控制元件。当第一电子元件13为开关元件时,第一电子元件13可以是MOSFET、IGBT等。第二电子元件23可以是开关元件,也可以是控制元件。当第二电子元件23为开关元件时,第二电子元件23可以是MOSFET、IGBT等。第一电子元件13和第二电子元件23可以分别由半导体元件构成,作为半导体材料,可以是硅、碳化硅、氮化镓等。第一电子元件13的另一侧的面也可以通过焊锡等导电性粘接剂与第一导体层12连接。
如图3至图5所示,第一连接体60可以具有第一头部61以及从第一头部61向另一侧延伸的第一柱部62。第一连接体60也可以具有位于第一电子元件13一侧的第一头区域61a以及第一柱部62a、以及位于第二电子元件23的另一侧的第一头区域61b以及第一柱部62b。第一连接体60截面大致呈T字形状。
如图3所示,可以在第一头区域61a的另一侧设置第一电子元件13,并在第二头区域61b的一侧设置第二电子元件23。
如图6以及图7所示,第二连接体70也可以具有第二头部71以及从第二头部71向另一侧延伸的第二柱部72。第二连接体70的截面大致呈T字形状。
如上述第一柱部62以及第一柱部62b那样,第一连接体60可以具有多个第一柱部62(62a、62b)。可以是其中一个第一柱部62和第二柱部72在面方向上重叠,另外的一个或多个的第一柱部62和第二柱部72在面方向上不重叠。在图3所示形态中,第一柱部62b和第二柱部72在面方向上重叠,第一柱部62a和第二柱部72在面方向上不重叠。
如图4所示,第一连接体60也可以具有从第一头部61延伸的一个或多个第一支撑部63。在设置多个第一支撑部63的情况下,可以采用至少一个第一支撑部63发挥电功能,至少一个第一支撑部63不发挥电功能的形态。在图4所示形态中,采用只有一个第一支撑部63发挥点功能,其他五个第一支撑部63不发挥电功能的形态。
如图6所示,第二连接体70也可以具有从第二头部71延伸的一个或多个第二支撑部73。在设置有多个第二支撑部73的情况下,可以采用至少一个第二支撑部73发挥电功能,至少一个第二支撑部73不发挥电功能的形态。在图6所示形态中,采用只有一个第二支撑部73发挥电功能,其他三个第二支撑部73不发挥电功能的形态。
如图2所示,也可以在第一电子元件13一侧设置第三连接体80。也可以在第二电子元件23的一侧设置第四连接体85。作为第三连接体80以及第四连接体85,可以采用一般的连接端子。
如图9(a)所示,第一电子元件13可以在一侧的面具有第一元件第一电极(例如第一源电极)13s与第一元件第二电极(例如第一栅电极)13g,如图9(b)所示,第二电子元件23可以在一侧的面具有第二元件第一电极(例如第二源电极)23s与第二元件第二电极(例如第二栅电极)23g。在这种情况下,第二连接体70的例如第二柱部72可以经由导电性粘接剂与第二电子元件23的第二元件第一电极23s连接,第四连接体85可以经由导电性粘接剂与第二电子元件23的第二元件第二电极23g连接。另外,第一连接体60也可以通过导电性粘接剂连接第一电子元件13的第一元件第一电极13s与设置在第二电子元件23的另一侧的第二元件第三电极(例如第二漏电极)23d。另外,第一连接体60的第一柱部62也可以通过导电性粘接剂与位于另一侧的第一电子元件13的第一元件第一电极13s抵接,第一连接体60的第二头区域61b通过导电性粘接剂与位于一侧的第二元件第三电极23d抵接。
与这样的形态不同,第一电子元件13也可以在另一侧的面具有第一元件第一电极13s和第一元件第二电极13g,并且在一侧的面具有第一元件第三电极13d。另外,第二电子元件23也可以在另一侧的面具有第二元件第一电极23s和第二元件第二电极23g,并且在一侧的面具有第二元件第三电极23d。在这种情况下,第二连接体70也可以与第二元件第三电极23d连接。另外,第一连接体60也可以将设置在第一电子元件13的一侧的第一元件第三电极13d与设置在第二电子元件23的另一侧的第二元件第一电极23s电连接。
如图2所示,第一导体层12可以与端子部5连接,端子部5的前端侧可以从密封部90的外侧露出并与外部装置连接。
作为第一基板11,可以采用陶瓷基板、绝缘树脂层等。作为导电性粘接剂,除了焊锡以外,也可以使用以Ag和Cu为主要成分的材料。作为第一连接体60以及第二连接体70材料可以使用Cu等金属。另外,作为第一基板11,也可以使用例如实施了电路图案化的金属基板,在这种情况下,第一基板11兼作第一导体层12。
端子部5与第一导体层12的接合不仅可以利用焊锡等导电性粘接剂,也可以利用激光焊接,还可以利用超声波接合。
如图1所示,也可以在第一基板11的另一侧的面上设置由铜等构成的第一散热板19。该第一散热板19也可以与散热器等散热体抵接。
《效果》
接着,将对由上述结构构成的本实施方式的效果进行说明。另外,在后述“效果”中说明的所有形态均可在采用上述结构。
在本实施方式中,如图1所示,在采用了第一电子元件13与第二电子元件23在面方向上不重叠的形态的情况下,就能够保持一定程度的散热性。因此,即使在不设置后述的第二基板21的情况下也能够获得高散热效果。作为制造者,也可以容易地选择如后述的其他实施方式所示的设置第二基板21的形态和不设置第二基板21的形态。这样一来,就能够根据顾客要求,采用设置第二基板21的形态和不设置第二基板21的形态这两种方式。在设置第二基板21的形态中也采用图1所示的电子单元,因此能够提高生产效率,能够抑制制造成本。
通过采用第一电子元件13与第二电子元件23在面方向上不重叠的形态,就能够将用于设置第二电子元件23的一侧的区域(第二头区域61b)在与用于设置第一电子元件13的一侧的区域(第一头区域61a)进行比较后使用弯曲部69来设置在另一侧。这样一来,能够减小厚度方向(第一方向)上的大小(厚度)。
如图3右侧所示,在采用第二电子元件23、一个第一柱部62b以及第二柱部72在面方向上重叠的形态的情况下,就能够将来自第二电子元件23的热量经由第一柱部62b直接向第一基板11侧进行散热,并且且将来自第二电子元件23的热量经由第二柱部72、第二头部71以及第二支部73来进行散热。
如图3的左侧所示,当采用了在电子模块内,在第二连接体70的一侧只设置密封部90,在第一电子元件13的一侧只设置第一连接体60和密封部90,且不设置其他部件的形态的情况下,与后述的其他实施方式相比,就能够期待在减少部件数量的同时减小厚度方向上的大小。
如图4所示,当采用了第一连接体60具有从第一头部61延伸的多个第一支撑部63的形态的情况下,能够经由第一支撑部63将热量向第一基板11侧散发。另外,通过采用至少一个第一支撑部63发挥电功能且至少一个第一支撑部63不发挥电功能的形态,能够将第一支撑部63的一部分用于电形态,同时将其他第一支撑部63用于散热。
如图6所示,当采用第二连接体70具有从第二头部71延伸的多个第二支撑部73的形态的情况下,能够经由第二支撑部73将热量散发到第二基板21侧。另外,通过采用至少一个第二支撑部73发挥电功能且至少一个第二支撑部73不发挥电功能的形态,能够将第二支撑部73的一部分用于电形态,同时将其他第二支撑部73用于散热。
第二实施方式
接着,对本发明的第二实施方式进行说明。
在本实施方式中,如图10(a)所示,在第二连接体70的一侧设置有第二基板21。在该形态中,第二基板21或第二导体层22与第二连接体70之间通过导电性粘接剂抵接或不通过任何材料直接抵接,在第二基板21与第一电子元件13的厚度方向(即第一方向)之间,仅设置有第一连接体60和密封部90。另外,图10(b)中展示了在图10(a)的形态下未设置第二基板21的形态。在图10所示的形态中,没有设置第一实施方式中的第一柱部62a以及第二柱部72,也没有设置弯曲部69。除此以外的其他结构,与第一实施方式相同,可以采用第一实施方式中说明的任何形态,并使用第一实施方式中相同的符号。
也可以如图10(a)所示设置第二基板21。是否设置第二基板21也可以根据顾客的要求来决定。通过设置第二基板21,可以将来自第二电子元件23的热量经由第二连接体70释放到第二基板21,从而提高散热效果。
另外,如图10(b)所示,也可以采用不设置第二基板21的形态。在这种情况下,能够相应地降低制造成本,并且能够减小厚度方向(即第一方向)上的大小。在图10(b)所示形态中,在第一电子元件13的一侧仅设置有第一连接体60以及密封部90。
在图10所示形态中,虽然没有设置第一柱部62a及第二柱部72,但相应地,能够减小厚度方向上的大小。另一方面,从为了释放来自第一电子元件13及第二电子元件23热量的观点来看,如第一实施方式那样设置第一柱部62a及第二柱部72是有益的。
也可以在第二基板21的另一侧的面上设置第二导体层22(参照图12)。在这种情况下,在第二基板21和第一电子元件13的厚度方向(即第一方向)之间,仅设置有第一连接体60、密封部90及第二导体层22。
第二导体层22与第二基板21可以通过焊锡等导电性粘接剂连接。作为第二基板21,可以采用陶瓷基板、绝缘树脂层等。作为第二基板21,也可以使用例如实施了电路图案化的金属基板,在这种情况下,第二基板21兼作第二导体层。
第二基板21的一侧的面可以与散热器等散热体抵接来促进散热。
第三实施方式
接着,对本发明的第三实施方式进行说明。
在本实施方式中,与第二实施方式一样,在第二连接体70的一侧设置有第二基板21。但是,与第二实施方式不同,如图11(a)所示,在第二基板21与第一连接体60之间设置有与第二基板21或第二导体层22的一侧的面和第一连接体60的另一侧的面抵接的间隔件150。除此以外的其他结构,可以采用在上述各实施方式中说明过的所有方式。对上述各实施方式中说明过的部件使用相同的符号进行说明。另外,在图11(b)中,展示了在图11(a)所示的形态中没有设置第二基板21及间隔件150的形态。
如本实施方式所示,通过设置间隔件150,能够将第一电子元件13产生的热经由该间隔件150有效地释放到第二基板21,这样就能够提高散热效果。作为间隔件150,可以使用铜等金属,也可以是散热绝缘性部件。此外,通过设置这样的间隔件150,能够支撑第二基板21的另一侧的面,在用密封树脂形成密封部90时,能够降低第二基板21在厚度方向上发生位置偏移的可能性。
图12展示了在图1所示的形态中设置间隔件150和第二基板21的形态。如图12所示,也可以在第二基板21的一侧设置第二散热板29。另外,第二基板21在面方向上的大小也可以小于第一基板11在面方向上的大小。
第四实施方式
接着,对本发明的第四实施方式进行说明。
在本实施方式中,第一支撑部63从第一头部61在面方向上延伸的方向与第二支撑部73从第二头部71在面方向上延伸的方向之间的角度在0度到±45度的范围内。在图13所示形态中,所有的第一支撑部63以及所有的第二支撑部73的第一支撑部63从第一头部61在面方向上延伸的方向与第二支撑部73从第二头部71在面方向上延伸的方向为相同方向(第二方向),即这些方向之间的角度为0度。另外,支撑部63、73是指具有宽度比头部61、71小且在面方向上突出的部分,在图13所示的形态中,指的是其在第三方向上的宽度比头部61、71小,且沿第二方向在面方向上突出的部分。除此以外的其他结构,可以采用在上述各实施方式中说明过的所有方式。对上述各实施方式中说明过的部件使用相同的符号进行说明。
如本实施方式所示,通过采用第一支撑部63从第一头部61在面方向上延伸的方向与第二支撑部73从第二头部71在面方向上延伸的方向之间的角度为0度到±45度的形态,就能够减小第一连接体61及第二连接体71在宽度方向(在图13中为第三方向)上的大小,进而能够减小电子装置在宽度方向上的尺寸。从该观点来看,第一支撑部63从第一头部61在面方向上延伸的方向与第二支撑部73从第二头部71在面方向上延伸的方向之间的角度为0度是有益的,另外,所有第一支撑部63及所有第二支撑部73中的第一支撑部63从第一头部61在面方向上延伸的方向与第二支撑部73从第二头部71在面方向上延伸的方向之间的角度为0度也是有益的。
上述各实施方式、变形例中的记载以及附图中公开的图示仅为用于说明权利要求项中记载的发明的一例,因此权利要求项中记载的发明不受上述实施方式或附图中公开的内容所限定。本申请最初的权利要求项中的记载仅仅是一个示例,可以根据说明书、附图等的记载对权利要求项中的记载进行适宜的变更。
符号说明
11 第一基板
13 第一电子元件
21 第二基板
23 第二电子元件
60 第一连接体
60b 第一连接体的另一侧的面
61 第一头部
61a 第一头区域
61b 第二头区域
63 第一支撑部
69 弯曲部
70 第二连接体
71 第二头部
73 第二支撑部
90 密封部
150 间隔件

Claims (9)

1.一种电子模块,其特征在于,包括:
第一基板;
第一电子元件,配置在所述第一基板的一侧;
第一连接体,配置在所述第一电子元件的一侧;
第二电子元件,配置在所述第一连接体的一侧;以及
第二连接体,配置在所述第二电子元件的一侧,
其中,所述第一电子元件与所述第二电子元件在面方向上不重叠,
所述第一连接体具有:第一头部、以及从所述第一头部延伸的多个第一支撑部,
所述第二连接体具有:第二头部、以及从所述第二头部延伸的多个第二支撑部,
所述第一支撑部从所述第一头部在面方向上延伸的方向与所述第二支撑部从所述第二头部在面方向上延伸的方向之间的角度在0度~±45度范围内。
2.根据权利要求1所述的电子模块,其特征在于:
其中,所述电子元件的一侧的面位于比位于所述第二电子元件的另一侧的所述第一连接体的另一侧的面更靠一侧的位置上。
3.根据权利要求1所述的电子模块,其特征在于:
其中,所述第一连接体具有:在其另一侧设置有所述第一电子元件的第一头区域、在其一侧设置有所述第二电子元件的第二头区域、以及在面方向上设置在第一头区域与第二头区域之间的弯曲部。
4.根据权利要求1所述的电子模块,其特征在于:
其中,所述第二电子元件、一个第一柱部以及第二柱部在面方向上重叠,其他的一个或多个第一柱部与第二柱部在面方向上不重叠。
5.根据权利要求1所述的电子模块,其特征在于,进一步包括:
密封部,用于密封所述第一电子元件、所述第一连接体、所述第二电子元件以及所述第二连接体,
其中,所述第一电子元件的一侧仅设置有所述第一连接体以及所述密封部。
6.根据权利要求1所述的电子模块,其特征在于,进一步包括:
密封部,用于密封所述第一电子元件、所述第一连接体、所述第二电子元件以及所述第二连接体;以及
第二基板,设置在所述第二连接体的一侧,
其中,在厚度方向上,所述第二基板与所述第一电子元件之间设置有所述第一连接体以及密封部,或是仅设置有设置在所述第一连接体、所述密封部以及所述第二基板的另一侧的第二导体层。
7.根据权利要求1所述的电子模块,其特征在于,进一步包括:
第二基板,设置在所述第二连接体的一侧,
其中,所述第二基板与所述第一连接体之间设置有间隔件。
8.根据权利要求1所述的电子模块,其特征在于:
其中,至少一个第一支撑部发挥电功能,并且至少一个第一支撑部不发挥电功能。
9.根据权利要求1所述的电子模块,其特征在于:
其中,至少一个第二支撑部发挥电功能,并且至少一个第二支撑部不发挥电功能。
CN201880094983.6A 2018-07-04 2018-07-04 电子模块 Active CN112368829B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/025308 WO2020008545A1 (ja) 2018-07-04 2018-07-04 電子モジュール

Publications (2)

Publication Number Publication Date
CN112368829A CN112368829A (zh) 2021-02-12
CN112368829B true CN112368829B (zh) 2024-05-14

Family

ID=69059554

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880094983.6A Active CN112368829B (zh) 2018-07-04 2018-07-04 电子模块

Country Status (5)

Country Link
US (1) US11776937B2 (zh)
EP (1) EP3819934A4 (zh)
JP (1) JP7222998B2 (zh)
CN (1) CN112368829B (zh)
WO (1) WO2020008545A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142172A (ja) * 2010-01-06 2011-07-21 Mitsubishi Electric Corp 電力用半導体装置
CN105723508A (zh) * 2014-10-16 2016-06-29 新电元工业株式会社 半导体模块
KR20170014635A (ko) * 2015-07-30 2017-02-08 현대자동차주식회사 반도체 패키지 및 그 제조 방법
WO2018047485A1 (ja) * 2016-09-06 2018-03-15 ローム株式会社 パワーモジュールおよびインバータ装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2811475B1 (fr) 2000-07-07 2002-08-23 Alstom Procede de fabrication d'un composant electronique de puissance, et composant electronique de puissance ainsi obtenu
TW488045B (en) * 2001-04-12 2002-05-21 Siliconware Precision Industries Co Ltd Semiconductor package with dislocated multi-chips
JP2005217072A (ja) 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
US8642394B2 (en) 2008-01-28 2014-02-04 Infineon Technologies Ag Method of manufacturing electronic device on leadframe
JP5845634B2 (ja) * 2011-05-27 2016-01-20 アイシン精機株式会社 半導体装置
US8525309B2 (en) * 2011-06-30 2013-09-03 Tessera, Inc. Flip-chip QFN structure using etched lead frame
US9564389B2 (en) * 2014-03-18 2017-02-07 Infineon Technologies Americas Corp. Semiconductor package with integrated die paddles for power stage
WO2016067383A1 (ja) 2014-10-29 2016-05-06 新電元工業株式会社 放熱構造
US10128174B2 (en) 2015-07-24 2018-11-13 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142172A (ja) * 2010-01-06 2011-07-21 Mitsubishi Electric Corp 電力用半導体装置
CN105723508A (zh) * 2014-10-16 2016-06-29 新电元工业株式会社 半导体模块
KR20170014635A (ko) * 2015-07-30 2017-02-08 현대자동차주식회사 반도체 패키지 및 그 제조 방법
WO2018047485A1 (ja) * 2016-09-06 2018-03-15 ローム株式会社 パワーモジュールおよびインバータ装置

Also Published As

Publication number Publication date
EP3819934A4 (en) 2022-11-02
WO2020008545A1 (ja) 2020-01-09
US11776937B2 (en) 2023-10-03
US20210134763A1 (en) 2021-05-06
JP7222998B2 (ja) 2023-02-15
CN112368829A (zh) 2021-02-12
EP3819934A1 (en) 2021-05-12
JPWO2020008545A1 (ja) 2021-08-12

Similar Documents

Publication Publication Date Title
US9433075B2 (en) Electric power semiconductor device
CN109511279B (zh) 电子模块
JP2012212712A (ja) 半導体装置の実装構造及び半導体装置の実装方法
US11189591B2 (en) Electronic module
CN112368829B (zh) 电子模块
JP6511584B2 (ja) チップモジュールの製造方法
US11276663B2 (en) Electronic module
US11309273B2 (en) Electronic module
CN111587488B (zh) 电子模块
CN111602241B (zh) 电子模块
NL2021293B1 (en) Electronic module
JP7018459B2 (ja) 電子モジュール
JP6999707B2 (ja) 電子モジュール
JP2017005129A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant