CN112289857A - Novel SiC GTO device with double base regions and double emitting regions - Google Patents

Novel SiC GTO device with double base regions and double emitting regions Download PDF

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CN112289857A
CN112289857A CN202011203998.7A CN202011203998A CN112289857A CN 112289857 A CN112289857 A CN 112289857A CN 202011203998 A CN202011203998 A CN 202011203998A CN 112289857 A CN112289857 A CN 112289857A
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region
emitter
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base region
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王俊
梁世维
邓雯娟
刘航志
俞恒裕
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Hunan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7424—Thyristor-type devices, e.g. having four-zone regenerative action having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

The invention discloses a novel SiC GTO device with double base regions and double emitting regions, which sequentially comprises the following components from an anode to a cathode in the vertical direction: the device comprises a P + emitter region, an N-type base region, a P-type drift region, a P-type buffer region and an N + type substrate; the P + emitter region is connected with the anode of the device, the N-type base region is connected with the gate electrode of the device, and the N + substrate is connected with the cathode of the device; the N-type base region has at least a 1-layer structure in the longitudinal direction; the P + emitting region has at least 1 layer structure in the longitudinal direction. The invention has the advantages of high injection efficiency, large current gain, high stability of gate current, small required driving current, small driving power and the like, and is suitable for application occasions of high voltage and high pulse current.

Description

Novel SiC GTO device with double base regions and double emitting regions
Technical Field
The invention belongs to the technical field of power electronic devices, and particularly relates to a novel SiC GTO device with double base regions and double emitting regions.
Background
The high-speed development of modern power electronic technology realizes the efficient utilization of electric energy and plays a vital role in promoting the development of scientific technology and economy. Since the 21 st century, the power electronic technology plays a core role in smart power grids, new energy sources, direct current transmission, electric automobiles and high-speed railways, makes a great contribution to the goal of energy conservation and emission reduction, and permeates into various fields such as science and technology, production, life and the like. The power electronic device is an important foundation for the development of power electronic technology, and is a core element for performing electric energy conversion and control on the power electronic technology.
Power electronics have matured over decades, with the development of Si-based power electronics approaching their theoretical limits. In this context, wide bandgap semiconductor devices such as silicon carbide (SiC), gallium nitride (GaN), and the like, and new technologies and new applications related thereto are gradually coming into the field of people, and the application range thereof is also expanding.
The silicon carbide material has the advantages of large forbidden band width, high critical breakdown electric field, high thermal conductivity and high saturated electron drift rate, and becomes an ideal material for preparing high-temperature, high-frequency and high-power devices. The SiC GTO has the advantages of large capacity, strong current processing capability and high blocking voltage, and has larger application space in the field of pulse power of high voltage and large current. However, as a current drive type device, SiC GTO requires a higher drive current and thus higher drive power. The SiC GTO has defects on the surface of the base region, which concentrates the current on the surface, resulting in a loss of a portion of the drive current, thus requiring a larger drive current, further increasing the required drive power, presenting greater challenges to the drive circuit, and reducing the stability of the gate current. In addition, the injection efficiency of the emitter is low, so that the current gain of the device can be greatly reduced, the conduction characteristic of the device is reduced, and the requirement on the driving current is improved. Therefore, it is necessary to design a new structure of the SiC GTO device with improved performance in many aspects.
Disclosure of Invention
The invention aims to solve the problems, and provides a novel SiC GTO device with double base regions and double emitting regions, which reduces the current on the surface of the base region and improves the injection efficiency of an emitting electrode of the device on the premise of maintaining the original voltage-resistant level, thereby reducing the driving current and improving the conduction characteristic of the device, so that the device has lower requirement on the driving power and is more suitable for the application occasions of high voltage and high pulse current.
In order to realize the purpose, the invention adopts the technical scheme that:
a novel SiC GTO device with double base regions and double emitting regions comprises the following components in sequence from an anode to a cathode in a vertical direction: the device comprises a P + emitter region, an N-type base region, a P-type drift region, a P-type buffer region and an N + type substrate; the P + emitter region is connected with the anode of the device, the N-type base region is connected with the gate electrode of the device, and the N + substrate is connected with the cathode of the device; the N-type base region has at least a 1-layer structure in the longitudinal direction; the P + emitting region has at least 1 layer structure in the longitudinal direction.
Furthermore, the N-type base region is of a 2-layer structure in the longitudinal direction and comprises a low-concentration doped base region in contact with the P + emitter region and a high-concentration doped base region in contact with the P-type drift region.
Further, the concentration of the high-concentration doped base region is 1e16cm-3～5e17cm-3。
Further, the concentration of the low-concentration doping base region is 1e15cm-3～3e15cm-3。
Further, the P + emitter region has a 2-layer structure in the longitudinal direction, and includes a P + emitter region in contact with the N-type base region and a P + + emitter region in contact with the anode.
Further, the doping concentration of the P + emitting region is 1e19cm-3～3e19cm-3。
Further, the doping concentration of the P + + emitting region is 1e20cm-3～1e21cm-3。
The invention has the beneficial effects that:
1. the invention has the advantages of high injection efficiency, large current gain, high stability of gate current, small required driving current and small driving power, and is suitable for application occasions with high voltage and high pulse current.
2. According to the invention, a single base region is optimized into a double base region, wherein the low-concentration doped base region is beneficial to forming a wider space charge region on the surface of the base region when conducting forward, so that the base region surface composite current caused by device defects is reduced, and a current path is changed, thereby reducing the loss of driving current, improving the utilization rate of the driving current, effectively reducing the required driving power, and remarkably improving the stability of gate electrode current; the PN junction between the base region and the drift region of the high-concentration doped base region can ensure that an electric field is cut off when bearing pressure, so that the device is prevented from being punctured and broken down, and the pressure-resistant level of the device is not reduced.
3. According to the invention, a single emitter region is optimized into a double emitter region, and the emitter region on the surface of the emitter region is doped with high concentration, so that the emitter injection efficiency of the device is greatly improved, and thus the current gain of the device is remarkably improved.
Drawings
FIG. 1 is a schematic diagram of a half-cell structure of a SiC GTO device in the prior art;
FIG. 2 is a schematic diagram of a half-cell structure of a device in accordance with embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of a device half-cell structure according to embodiment 2 of the present invention;
fig. 4 is a schematic structural diagram of a device half cell in embodiment 3 of the present invention.
Detailed Description
The following detailed description of the present invention is given for the purpose of better understanding technical solutions of the present invention by those skilled in the art, and the present description is only exemplary and explanatory and should not be construed as limiting the scope of the present invention in any way.
Example 1
As shown in fig. 2, a novel SiC GTO device with dual base regions and dual emitter regions includes, in order from anode to cathode in the vertical direction: the device comprises a P + emitter region 1, an N-type base region 2, a P-type drift region 3, a P-type buffer region 4 and an N + type substrate 5; the P + emitter region 1 is connected with the anode of the device, the N-type base region 2 is connected with the gate electrode of the device, and the N + substrate 5 is connected with the cathode of the device; the P + emission region 1 is of a 1-layer structure in the longitudinal direction; the N-type base region 2 is of a 2-layer structure in the longitudinal direction and comprises a low-concentration doped base region 21 in contact with the P + emitter region 1 and a high-concentration doped base region 22 in contact with the P-type drift region 3.
In the present embodiment, the concentration of the high concentration doped base region 22 is 1e16cm-3。
In the present embodiment, the concentration of the low concentration doped base region 21 is 3e15cm-3。
For the SiC GTO device structure in the prior art, composite current can be formed on the surface of a base region, so that the loss of gate driving current is caused, and the gate driving current is unstable. According to the double-base-region SiC GTO structure, when the low-concentration doped base region 21 is conducted in the forward direction, a wider space charge region is formed on the surface of the base region, so that the surface recombination current is reduced, and the current path is changed, so that the loss of the driving current is reduced, the utilization rate of the driving current is improved, the required driving power is effectively reduced, and the stability of the gate driving current is improved; the high-concentration doped base region 22 can ensure that an electric field is cut off when a PN junction between the N-type base region 2 and the P-type drift region 3 bears pressure, and the device is prevented from being broken down in advance.
Example 2
As shown in fig. 2, a novel SiC GTO device with dual base regions and dual emitter regions includes, in order from anode to cathode in the vertical direction: the device comprises a P + emitter region 1, an N-type base region 2, a P-type drift region 3, a P-type buffer region 4 and an N + type substrate 5; the P + emitter region 1 is connected with the anode of the device, the N-type base region 2 is connected with the gate electrode of the device, and the N + substrate 5 is connected with the cathode of the device; the P + emission region 1 is of a 1-layer structure in the longitudinal direction; the N-type base region 2 is of a 2-layer structure in the longitudinal direction and comprises a low-concentration doped base region 21 in contact with the P + emitter region 1 and a high-concentration doped base region 22 in contact with the P-type drift region 3.
In the present embodiment, the concentration of the high concentration doped base region 22 is 5e17cm-3。
In the present embodiment, the concentration of the low concentration doped base region 21 is 1e15cm-3。
Example 3
As shown in fig. 3, a novel SiC GTO device with dual base regions and dual emitter regions includes, in order from anode to cathode in the vertical direction: the device comprises a P + emitter region 1, an N-type base region 2, a P-type drift region 3, a P-type buffer region 4 and an N + type substrate 5; the P + emitter region 1 is connected with the anode of the device, the N-type base region 2 is connected with the gate electrode of the device, and the N + substrate 5 is connected with the cathode of the device; the N-type base region 2 has a 1-layer structure in the longitudinal direction; the P + emitter region 1 has a 2-layer structure in the longitudinal direction, and includes a P + emitter region 12 in contact with the N-type base region 3 and a P + + emitter region 11 in contact with the anode.
In the present embodiment, the doping concentration of the P + emitter region 12 is 1e19cm-3。
In the present embodiment, the doping concentration of the P + + emitter region 11 is 1e20cm-3。
The SiC GTO anode region acts as the emitter region of the PNP BJT, and the concentration of the SiC GTO anode region determines the injection efficiency of the emitter region to the base region. As shown in fig. 3, in the double emitter region SiC GTO device structure, the surface emitter region is the P + + emitter region 11, which is a high concentration emitter region, and this high concentration emitter region reduces the incomplete ionization degree, improves the injection efficiency into the base region, and thus helps to improve the current amplification factor of the device. Therefore, the structure can improve the current gain of the device, thereby reducing the required driving current, reducing the driving power consumption and greatly improving the forward conduction characteristic of the device.
Example 4
As shown in fig. 3, a novel SiC GTO device with dual base regions and dual emitter regions includes, in order from anode to cathode in the vertical direction: the device comprises a P + emitter region 1, an N-type base region 2, a P-type drift region 3, a P-type buffer region 4 and an N + type substrate 5; the P + emitter region 1 is connected with the anode of the device, the N-type base region 2 is connected with the gate electrode of the device, and the N + substrate 5 is connected with the cathode of the device; the N-type base region 2 has a 1-layer structure in the longitudinal direction; the P + emitter region 1 has a 2-layer structure in the longitudinal direction, and includes a P + emitter region 12 in contact with the N-type base region 3 and a P + + emitter region 11 in contact with the anode.
In the present embodiment, the doping concentration of the P + emitter region 12 is 3e19cm-3。
In the present embodiment, the doping concentration of the P + + emitter region 11 is 1e21cm-3。
Example 5
As shown in fig. 4, a novel SiC GTO device with dual base regions and dual emitter regions includes, in order from anode to cathode in the vertical direction: the device comprises a P + emitter region 1, an N-type base region 2, a P-type drift region 3, a P-type buffer region 4 and an N + type substrate 5; the P + emitter region 1 is connected with the anode of the device, the N-type base region 2 is connected with the gate electrode of the device, and the N + substrate 5 is connected with the cathode of the device; the N-type base region 2 is of a 2-layer structure in the longitudinal direction and comprises a low-concentration doped base region 21 in contact with the P + emitter region 1 and a high-concentration doped base region 22 in contact with the P-type drift region 3. The P + emitter region 1 has a 2-layer structure in the longitudinal direction, and includes a P + emitter region 12 in contact with the N-type base region 2 and a P + + emitter region 11 in contact with the anode.
In the present embodiment, the concentration of the high concentration doped base region 22 is 1e16cm-3。
In the present embodiment, the concentration of the low concentration doped base region 21 is 3e15cm-3。
In the present embodiment, the doping concentration of the P + emitter region 12 is 1e19cm-3。
In the present embodiment, the doping concentration of the P + + emitter region 11 is 1e20cm-3。
The structure combines the advantages of the double-base-region SiC GTO and the double-emission-region SiC GTO, so that on one hand, the composite current on the surface of the base region of the device is reduced on the premise of not losing the voltage-resistant level of the device, the utilization rate of the gate electrode driving current is improved, and the stability of the gate electrode current is improved; on one hand, the injection efficiency of the emitter of the device is improved, so that the current gain of the device is improved, the required driving current is reduced, and the forward conduction characteristic of the device is improved.
Example 6
A novel SiC GTO device with double base regions and double emitting regions comprises the following components in sequence from an anode to a cathode in a vertical direction: the device comprises a P + emitter region 1, an N-type base region 2, a P-type drift region 3, a P-type buffer region 4 and an N + type substrate 5; the P + emitter region 1 is connected with the anode of the device, the N-type base region 2 is connected with the gate electrode of the device, and the N + substrate 5 is connected with the cathode of the device; the N-type base region 2 is of a 2-layer structure in the longitudinal direction and comprises a low-concentration doped base region 21 in contact with the P + emitter region 1 and a high-concentration doped base region 22 in contact with the P-type drift region 3. The P + emitter region 1 has a 2-layer structure in the longitudinal direction, and includes a P + emitter region 12 in contact with the N-type base region 2 and a P + + emitter region 11 in contact with the anode.
In the present embodiment, the concentration of the high concentration doped base region 22 is 5e17cm-3。
In the present embodiment, the concentration of the low concentration doped base region 21 is 1e15cm-3。
In the present embodiment, the doping concentration of the P + emitter region 12 is 3e19cm-3。
In the present embodiment, the doping concentration of the P + + emitter region 11 is 1e21cm-3。
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.

Claims (7)

1. A novel SiC GTO device with double base regions and double emitting regions is characterized in that the vertical direction sequentially comprises from an anode to a cathode: the device comprises a P + emitter region (1), an N-type base region (2), a P-type drift region (3), a P-type buffer region (4) and an N + type substrate (5); the P + emitter region (1) is connected with an anode of a device, the N-type base region (2) is connected with a gate pole, and the N + type substrate (5) is connected with a cathode; the N-type base region (2) is at least of a 1-layer structure in the longitudinal direction; the P + emitting region (1) has at least a 1-layer structure in the longitudinal direction.
2. A novel SiC GTO device with a double base region, double emitter region, according to claim 1, characterized in that the N-type base region (2) is a 2-layer structure in the longitudinal direction, comprising a low-doped base region (21) in contact with the P + emitter region (1) and a high-doped base region (22) in contact with the P-type drift region (3).
3. A novel SiC GTO device with dual base and dual emitter as claimed in claim 2 wherein said heavily doped base region (22) has a concentration of 1e16cm-3～5e17cm-3。
4. A new SiC GTO device with a double base region, a double emitter region, according to claim 3, characterised in that the low-doped base region (21) has a concentration of 1e15cm-3～3e15cm-3。
5. A novel SiC GTO device with dual base regions and dual emitter regions according to any of claims 1 to 4, wherein said P + emitter region (1) has a 2-layer structure in the longitudinal direction, comprising a P + emitter region (12) in contact with the N-type base region (2) and a P + + emitter region (11) in contact with the anode.
6. A novel SiC GTO device with dual base and dual emitter as claimed in claim 5, wherein said P + emitter (12) has a doping concentration of 1e19cm-3～3e19cm-3。
7. A novel SiC GTO device with dual base regions and dual emitter regions according to claim 6 wherein said P + + emitter region (11) has a doping concentration of 1e20cm-3～1e21cm-3。
CN202011203998.7A 2020-11-02 2020-11-02 Novel SiC GTO device with double base regions and double emitting regions Pending CN112289857A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120018737A1 (en) * 2010-07-21 2012-01-26 Cree, Inc. Electronic device structure including a buffer layer on a base layer
CN107579115A (en) * 2017-08-18 2018-01-12 西安理工大学 A kind of carborundum light triggered thyristor and preparation method with double-deck thin n bases
CN110534567A (en) * 2019-09-06 2019-12-03 电子科技大学 A kind of silicon carbide gate level turn-off thyristor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120018737A1 (en) * 2010-07-21 2012-01-26 Cree, Inc. Electronic device structure including a buffer layer on a base layer
CN107579115A (en) * 2017-08-18 2018-01-12 西安理工大学 A kind of carborundum light triggered thyristor and preparation method with double-deck thin n bases
CN110534567A (en) * 2019-09-06 2019-12-03 电子科技大学 A kind of silicon carbide gate level turn-off thyristor

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Application publication date: 20210129

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