CN111490101B - GaN-based HEMT device - Google Patents
GaN-based HEMT device Download PDFInfo
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- CN111490101B CN111490101B CN202010325595.3A CN202010325595A CN111490101B CN 111490101 B CN111490101 B CN 111490101B CN 202010325595 A CN202010325595 A CN 202010325595A CN 111490101 B CN111490101 B CN 111490101B
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- 238000003860 storage Methods 0.000 claims abstract description 33
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000006911 nucleation Effects 0.000 claims description 9
- 238000010899 nucleation Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910002704 AlGaN Inorganic materials 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000011084 recovery Methods 0.000 abstract description 2
- 230000009467 reduction Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a GaN-based HEMT device. The main scheme of the invention is to introduce a charge storage layer with P-type doping connected with a source electrode into a buffer layer of a device. When the device is switched off, the net negative charge in the P-type doped charge storage layer can effectively accelerate the depletion of two-dimensional electron gas, so that the switching-off time is reduced to enable the device to have lower switching-off loss. When the device is started, the reduction of the net negative charge amount in the P-type doped charge storage layer is beneficial to the recovery of two-dimensional electron gas, and further the starting time is reduced to enable the device to have lower starting loss. Therefore, the invention has extremely low switching loss and can be used in low-power switch application.
Description
Technical Field
The invention belongs to the technical field of compound semiconductor manufacturing, and particularly relates to a GaN-based HEMT device.
Background
GaN-based HEMT devices are excellent solutions for high frequency and high power switching applications due to their excellent properties of high electron mobility, high critical breakdown field strength, high electron saturation velocity, etc. With the continuous development of the technology, the requirements of the power switch application on high-frequency high-power GaN-based HEMT devices are increasing day by day. Although GaN-based power HEMT devices have inherently lower power consumption, their switching losses still need to be reduced to meet the requirements of higher efficiency applications. Especially in high frequency operating environment, the switching loss of the device still has a large weight in the overall power consumption. Therefore, it is very valuable to design a high performance GaN-based power HEMT device with low switching losses to meet the requirements of high frequency and high efficiency applications.
Disclosure of Invention
The invention aims to solve the problems and provides a GaN-based HEMT device with a charge storage mechanism, so that the prepared device has low switching loss.
In order to achieve the purpose, the invention adopts the following technical scheme:
a GaN-based HEMT device is characterized by comprising a P-type doped charge storage layer 1, a buffer layer 2, a substrate layer 3, a nucleation layer 4, a channel layer 5, a barrier layer 6, a passivation layer 7, a P-type cap layer 8, a silicon dioxide layer 9, a grid 10, a source electrode 11 and a drain electrode 12; the P-type doped charge storage layer 1 is positioned in the buffer layer 2; the buffer layer 2 is positioned above the nucleation layer 4; the nucleation layer 4 is positioned above the substrate layer 3; the transverse heterojunction structure formed by the channel layer 5 and the barrier layer 6 is positioned on the buffer layer 2, and two-dimensional electron gas exists at a heterojunction interface; the P-type cap layer 8 is positioned on the upper surface of one side of the barrier layer 6, and the grid 10 is positioned on the upper surface of the P-type cap layer 8; the grid electrode 10 and the P-type cap layer 8 form ohmic contact or Schottky contact; the passivation layer 7 is positioned on the upper surface of the barrier layer 6 and completely covers the gate 10 and the P-type cap layer 8; the drain electrode 12 is positioned on the upper surface of one end of the passivation layer 7, which is far away from the P-type cap layer 8, sequentially penetrates through the passivation layer 7 and the barrier layer 6 along the vertical direction, and then extends into the channel layer 5, so that ohmic contact is formed between the drain electrode and the two-dimensional electron gas channel; the source electrode 11 covers the upper surface of the other end of the passivation layer 7, sequentially penetrates through the passivation layer 7, the barrier layer 6 and the channel layer 5 along the vertical direction, then extends into the P-type doped charge storage layer 1, and forms ohmic contact with the two-dimensional electron gas channel; between the source 11 and the drain 12 there is a silicon dioxide layer 9.
Further, the P-type doped charge storage layer 1 is made of GaN or AlGaN.
Further, the doping concentration range of the P-type doped charge storage layer 1 is 1 × 1016cm-3—1×1019cm-3。
Further, the thickness of the P-type doped charge storage layer 1 is smaller than that of the buffer layer (2).
Further, the length of the P-type doped charge storage layer 1 is less than or equal to the length of the buffer layer (2).
Further, an ohmic contact is formed between the P-type doped charge storage layer 1 and the source electrode 11.
The GaN-based HEMT device has the beneficial effects that the switching loss of the device is greatly reduced by providing the GaN-based HEMT device with the charge storage mechanism.
Drawings
FIG. 1 is a schematic diagram of a GaN-based HEMT device with a charge storage mechanism in an embodiment of the invention;
fig. 2 is a schematic view showing a GaN-based HEMT device of a conventional structure;
FIG. 3 is a schematic diagram showing the charge distribution in the P-type doped charge storage layer when the device is turned off;
FIG. 4 is a schematic diagram showing the charge distribution in the P-type doped charge storage layer when the device is turned on;
FIG. 5 is a graph showing the output characteristics of a device of an embodiment of the present invention in comparison with a device of a conventional structure;
FIG. 6 is a graph showing the blocking characteristics of a device of the present invention in comparison to a device of conventional construction;
FIG. 7 is a schematic diagram showing a comparison of waveforms of a device of an embodiment of the present invention and a device of a conventional structure when the device is turned off;
fig. 8 is a schematic diagram showing a comparison of waveforms of the device of the present invention and the device of the conventional structure when the device is turned on.
Detailed Description
The technical solution of the embodiments of the present invention is described in detail below with reference to the accompanying drawings.
The structure of the GaN-based HEMT device provided by the embodiment of the invention is shown in FIG. 1, and the GaN-based HEMT device comprises a P-type doped charge storage layer 1, a buffer layer 2, a substrate layer 3, a nucleation layer 4, a channel layer 5, a barrier layer 6, a passivation layer 7, a P-type cap layer 8, a silicon dioxide layer 9, a grid 10, a source electrode 11 and a drain electrode 12; the P-type doped charge storage layer 1 is positioned in the buffer layer 2; the buffer layer 2 is positioned above the nucleation layer 4; the nucleation layer 4 is positioned above the substrate layer 3; the transverse heterojunction structure formed by the channel layer 5 and the barrier layer 6 is positioned on the buffer layer 2, and two-dimensional electron gas (2DEG) exists at a heterojunction interface; the P-type cap layer 8 is positioned on the upper surface of one side of the barrier layer 6, and the grid 10 is positioned on the upper surface of the P-type cap layer 8; the grid electrode 10 and the P-type cap layer 8 form ohmic contact or Schottky contact; the passivation layer 7 is positioned on the upper surface of the barrier layer 6 and completely covers the gate 10 and the P-type cap layer 8; the drain electrode 12 is positioned on the upper surface of one end of the passivation layer 7, which is far away from the P-type cap layer 8, sequentially penetrates through the passivation layer 7 and the barrier layer 6 along the vertical direction, and then extends into the channel layer 5, so that ohmic contact is formed between the drain electrode and the two-dimensional electron gas channel; the source electrode 11 covers the upper surface of the other end of the passivation layer 7, sequentially penetrates through the passivation layer 7, the barrier layer 6 and the channel layer 5 along the vertical direction, then extends into the P-type doped charge storage layer 1, and forms ohmic contact with the two-dimensional electron gas channel; between the source 11 and the drain 12 there is a silicon dioxide layer 9.
The working principle of the invention is as follows: when the device is turned off, a higher potential difference between the source electrode 11 and the drain electrode 12 causes a decrease in the energy band of the portion of the P-type doped charge storage layer 1 near the drain electrode 12. In this process, negatively charged ionized acceptors are stored in the P-doped charge storage layer 1 as the free holes are depleted (as shown in fig. 3). This increase in the amount of negative charge will additionally contribute to the depletion of the two-dimensional electron gas, depending on the electrically neutral condition. Thereby, the turn-off time of the device is significantly reduced, which results in a device with lower turn-off losses. When the device is turned on, the potential difference between the source electrode 11 and the drain electrode 12 is decreased, so that the energy band of the portion of the P-type doped charge storage layer 1 near the drain electrode 12 is raised. In this process, the amount of net negative charge in the P-type doped charge storage layer 1 decreases as free holes are injected (as shown in fig. 4). This reduction in the amount of negative charge accelerates the recovery of the two-dimensional electron gas according to the electrically neutral condition. Thus, the turn-on time of the device is greatly reduced, which results in a device with lower turn-on loss.
The advantages of the invention are further confirmed by comparing the simulation of the GaN-based HEMT device with the charge storage mechanism provided by the invention with the conventional device (the P-type doped charge storage layer 1, the structure diagram of which is shown in FIG. 2).
Fig. 5 and 6 show a comparison of the output and withstand voltage characteristics of the present invention and conventional devices, respectively. To ensure a fair comparison, it is necessary to ensure consistent turn-on voltage drop and blocking characteristics of the present invention and conventional devices.
Fig. 7 and 8 show a comparison of the turn-off and turn-on waveforms of the present invention and conventional devices, respectively. It can be seen from the figure that the switching time of the present invention is effectively reduced, and the turn-on and turn-off losses are both greatly reduced. The switching loss is defined as the sum of the turn-off loss and the turn-on loss. Through calculation, the switching loss of the invention is reduced by 63% compared with that of the conventional device, and the performance advantage of the invention on the application of a low-power-consumption power switching device compared with the conventional device is fully demonstrated.
Claims (4)
1. The GaN-based HEMT device is characterized by comprising a P-type doped charge storage layer (1), a buffer layer (2), a substrate layer (3), a nucleation layer (4), a channel layer (5), a barrier layer (6), a passivation layer (7), a P-type cap layer (8), a silicon dioxide layer (9), a grid (10), a source electrode (11) and a drain electrode (12); the P-type doped charge storage layer (1) is positioned in the buffer layer (2); the buffer layer (2) is positioned above the nucleation layer (4); the nucleation layer (4) is positioned above the substrate layer (3); a transverse heterojunction structure formed by the channel layer (5) and the barrier layer (6) is positioned on the buffer layer (2), and two-dimensional electron gas exists at a heterojunction interface; the P-type cap layer (8) is positioned on the upper surface of one side of the barrier layer (6), and the grid (10) is positioned on the upper surface of the P-type cap layer (8); the grid electrode (10) and the P-type cap layer (8) form ohmic contact or Schottky contact; the passivation layer (7) is positioned on the upper surface of the barrier layer (6) and completely covers the grid electrode (10) and the P-type cap layer (8); the drain electrode (12) is positioned on the upper surface of one end, away from the P-type cap layer (8), of the passivation layer (7), sequentially penetrates through the passivation layer (7) and the barrier layer (6) along the vertical direction, and then extends into the channel layer (5), so that ohmic contact is formed between the drain electrode and the two-dimensional electron gas channel; the source electrode (11) covers the upper surface of the other end of the passivation layer (7), sequentially penetrates through the passivation layer (7), the barrier layer (6) and the channel layer (5) along the vertical direction, then extends into the P-type doped charge storage layer (1), and forms ohmic contact with the two-dimensional electron gas channel; a silicon dioxide layer (9) is arranged between the source electrode (11) and the drain electrode (12); the length of the P-type doped charge storage layer (1) is equal to that of the buffer layer (2), and ohmic contact is formed between the P-type doped charge storage layer (1) and the source electrode (11).
2. The GaN-based HEMT device of claim 1, wherein: the P-type doped charge storage layer (1) is made of GaN or AlGaN.
3. The GaN-based HEMT device of claim 2, wherein: the doping concentration range of the P-type doped charge storage layer (1) is 1 multiplied by 1016cm-3—1×1019cm-3。
4. A GaN-based HEMT device according to claim 3, wherein: the thickness of the P-type doped charge storage layer (1) is smaller than that of the buffer layer (2).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010325595.3A CN111490101B (en) | 2020-04-23 | 2020-04-23 | GaN-based HEMT device |
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| CN202010325595.3A CN111490101B (en) | 2020-04-23 | 2020-04-23 | GaN-based HEMT device |
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| CN111490101A CN111490101A (en) | 2020-08-04 |
| CN111490101B true CN111490101B (en) | 2021-07-27 |
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| CN112086508A (en) * | 2020-10-23 | 2020-12-15 | 电子科技大学 | Low input capacitance GaN-based HEMT device |
| CN113540233A (en) * | 2021-07-29 | 2021-10-22 | 电子科技大学 | P-GaN HEMT device with low on-resistance and high transconductance |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024879A (en) * | 2015-03-31 | 2016-10-12 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| CN109004028A (en) * | 2018-06-22 | 2018-12-14 | 杭州电子科技大学 | It is a kind of with source electrode be connected P buried layer and leak field plate GaN field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7078743B2 (en) * | 2003-05-15 | 2006-07-18 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor semiconductor device |
| US9443938B2 (en) * | 2013-07-19 | 2016-09-13 | Transphorm Inc. | III-nitride transistor including a p-type depleting layer |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024879A (en) * | 2015-03-31 | 2016-10-12 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the semiconductor device |
| CN109004028A (en) * | 2018-06-22 | 2018-12-14 | 杭州电子科技大学 | It is a kind of with source electrode be connected P buried layer and leak field plate GaN field effect transistor |
Non-Patent Citations (1)
| Title |
|---|
| Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in p-GaN Gate HEMTs;Jin Wei et al;《IEEE ELECTRON DEVICE LETTERS》;20190430;第40卷(第4期);第526页第2段-528页最后1段，附图3 * |
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