CN114709260A - Mixed type carrier control device - Google Patents

Mixed type carrier control device Download PDF

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CN114709260A
CN114709260A CN202210451520.9A CN202210451520A CN114709260A CN 114709260 A CN114709260 A CN 114709260A CN 202210451520 A CN202210451520 A CN 202210451520A CN 114709260 A CN114709260 A CN 114709260A
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region
electrode
insulating material
depletion
transistor
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CN114709260B (en
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汪志刚
李雪
黄孝兵
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Qianghua Times Chengdu Technology Co ltd
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Qianghua Times Chengdu Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

The invention provides a mixed carrier control device, and belongs to the technical field of power semiconductors. Comprises a main working unit and at least one depletion type PMOS structure; the main working unit and the depletion type PMOS structure are respectively arranged at two ends of the MOS gate-controlled thyristor; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode. The invention solves the problems of poor compromise relationship between the conduction voltage drop and the turn-off loss of the existing grid-controlled thyristor, weak anti-electromagnetic interference capability and poor practicability.

Description

Mixed type carrier control device
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a hybrid carrier control device.
Background
Conventional MCTs are complex devices that simply combine MOSFET structures with thyristor structures to form composite devices. Because the resistance of the MOS gate insulating layer is very high, the input power of the device is very small, the gate driving circuit is simple, and the switching speed is high. And the thyristor device has extremely low conduction voltage drop and strong high current load capacity. Therefore, the MCT device combining the MOS tube and the thyristor effectively improves the controllability problem of the conventional thyristor and increases the current load capacity. But such a simple combination makes the loss when the device is turned off large. In order to reduce turn-off loss and improve device performance, an anode short-circuit MCT (AS-MCT) device and a cathode short-circuit MCT (CS-MCT) device are provided, the bottom of the AS-MCT structure is composed of alternating P + doped regions and N + doped regions to form an anode of the device, the formed structure is in short circuit with a PNP tube base region, and when the device is turned off, surplus current carriers in the device can directly enter the anode through the N + doped region at the bottom without passing through the P + doped region of the anode, so that the turn-off speed of the device is accelerated, and the turn-off time is shortened. The CS-MCT structure is formed by adding P + type doping in the cathode region of the device, so that the cathode of the device is in short circuit with the base region of the NPN tube to form a current carrier channel, a channel is provided for the cavity to be drawn away when the device is turned off, the gain of the NPN tube is inhibited, and the positive feedback mechanism of the thyristor is damaged.
With the subsequent development of the IGBT device, and because the main structure of the MCT device is similar to that of the IGBT device, the MCT device and the IGBT device are referred to each other, and thus, the MCT device has become one of the important means for optimizing the MCT device at present. At present, a more popular RC-IGBT device and a CIGBT device are researched, namely, a thyristor and an IGBT are combined together, the switching process is better controlled by utilizing respective excellent characteristics, the conduction voltage drop of the new device is small, and excessive carriers during turn-off can also quickly flow to a cathode region, the turn-off speed is accelerated, and the turn-off loss is reduced.
The grid-controlled thyristor device plays a crucial role in electric energy conversion, but in the process of converting electric energy, the grid-controlled thyristor device can consume a part of energy to generate energy loss, and meanwhile, the speed of the device when the device is turned off is too slow, the tail current is too long, and the working efficiency of the whole system can be reduced. On the other hand, in the electric energy conversion system, a capacitance or inductance element is inevitably used, which increases the parasitic effect in the system, and the working stability of the system cannot be guaranteed. Therefore, in order to solve the problems, the problems of large turn-off loss and weak anti-electromagnetic interference capability are solved by optimizing the conventional structure, which is of great significance to the actual life and production of people.
Disclosure of Invention
Aiming at the defects in the prior art, the mixed type current carrier controller provided by the invention solves the problems of poor compromise relationship between conduction voltage drop and turn-off loss, weak anti-electromagnetic interference capability and poor practicability of the existing thyristor.
In order to achieve the purpose, the invention adopts the technical scheme that: a hybrid current carrier control device comprises a main working unit and at least one depletion type PMOS structure;
the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
The invention has the beneficial effects that: on the basis of a conventional thyristor device, the invention utilizes two P-type regions with different doping concentrations and areas, and introduces a low-doped P-type region into the right region of the top of the device to form a depletion type PMOS structure, thereby realizing the purpose of controlling electron and hole carriers. The invention has small conduction voltage drop when being started, strong anti-electromagnetic interference capability, can quickly pump out the excessive current carriers in the device when being turned off, effectively solves the contradiction relationship between the conduction voltage drop and the turn-off loss, and improves the performance of the device when being turned on and turned off.
Furthermore, the gate control region comprises a first electrode, a first insulating material, a second insulating material, a fourth electrode heavily-doped ohmic contact region and a fourth electrode base region;
the first electrode is arranged in the first insulating material, the fourth electrode base region is arranged at the lower end of the fourth electrode, and the fourth electrode heavily-doped ohmic contact region is arranged in the fourth electrode base region and is positioned on the side edge of the first insulating material.
The beneficial effects of the further scheme are as follows: the fourth electrode is heavily doped with the ohmic contact region to form an NMOS tube structure together with the electrode. When the first electrode is applied with positive voltage, electrons are quickly injected into the device, so that the device can be quickly started; when the first electrode is applied with negative pressure, the injection of electrons is stopped, so that the device enters a turn-off state, the second insulating material plays an isolating role, and the gate control area can be effectively isolated from other areas.
Furthermore, the gate control region comprises a first electrode, a first insulating material, a second electrode, a second insulating material, a fourth electrode heavily-doped ohmic contact region and a fourth electrode base region;
the first electrode is arranged in the first insulating material, the second electrode is arranged in the second insulating material, the fourth electrode base region is arranged at the lower end of the fourth electrode, and the heavily doped ohmic contact region of the fourth electrode is arranged in the fourth electrode base region and is respectively positioned at the side edges of the first insulating material and the second insulating material.
The beneficial effects of the above further scheme are: and the heavily doped ohmic contact area of the fourth electrode positioned on the side edges of the first insulating material and the second insulating material and the first electrode and the second electrode respectively form two NMOS tube structures. When the device is started, positive voltage is applied to the first electrode and the second electrode, and the two NMOS tubes inject electrons into the device at the same time, so that the injection quantity of the electrons is increased, and the starting process of the device is further accelerated.
Still further, each depletion type PMOS region comprises a third electrode, a fifth electrode, a third insulating material, a fifth electrode heavily doped ohmic contact region, a first depletion region and a second conductivity type semiconductor; each depletion type PMOS region is arranged in parallel in a mode that the fifth electrode heavily-doped ohmic contact region and the first depletion region are in contact connection with a third insulating material;
the third electrode is arranged in the third insulating material, the fifth electrode is arranged between the third insulating material and the second insulating material, the fifth electrode heavily doped ohmic contact region is arranged at the lower end of the fifth electrode, the first depletion region is arranged at the lower end of the fifth electrode heavily doped ohmic contact region, the second conductive type semiconductor is arranged at the lower ends of the first depletion region and the third insulating material, the thyristor region is adjacent to the second conductive type semiconductor, and the first insulating material is arranged at one end far away from the second conductive type semiconductor.
The beneficial effects of the further scheme are as follows: the region forms a depletion type PMOS structure, a part of hole carriers are removed in the starting process, and the conductance modulation effect of the device is reduced. When the device is turned off, a carrier extraction channel is formed, and all surplus carriers in the device flow away from the channel, so that the carrier extraction speed is increased, and the turn-off loss is reduced.
Still further, each depletion type PMOS region comprises a third electrode, a fifth electrode, a third insulating material, a fifth electrode heavily doped ohmic contact region, a first depletion region and a second conductivity type semiconductor; each depletion type PMOS region is arranged in parallel in a mode that the fifth electrode heavily-doped ohmic contact region and the first depletion region are in contact connection with a third insulating material;
the third electrode is arranged in the third insulating material, the fifth electrode is arranged between the third insulating material and the second insulating material, the fifth electrode heavily doped ohmic contact region is arranged at the lower end of the fifth electrode, the first depletion region is arranged at the lower end of the fifth electrode heavily doped ohmic contact region, the second conduction type semiconductor is arranged at the lower ends of the second insulating material, the first depletion region and the third insulating material, the thyristor region is adjacent to the second conduction type semiconductor, and the first insulating material is arranged at one end far away from the second conduction type semiconductor.
The beneficial effects of the further scheme are as follows: the area of the second conduction type semiconductor is increased, so that the control effect of the device on carriers is enhanced, excessive carriers enter a depletion type PMOS channel from the area more quickly when the device is turned off, the current tailing effect is reduced, and the turn-off loss is reduced.
Still further, the thyristor region includes a first transistor emitter region, a first transistor base region, a first transistor collector region, a buffer region, an anode emitter region, and a seventh electrode;
the first transistor emitter region is arranged at the lower end of the fourth electrode base region, and the first transistor base region is arranged at the lower ends of the first transistor emitter region and the second insulating material; the first transistor collector region is arranged at the lower end of the first insulating material, the first transistor base region and the second conductive type semiconductor, the buffer region and the anode emitter region are sequentially arranged at the lower end of the first transistor collector region, the seventh electrode is arranged at the lower end of the anode emitter region, and the first transistor base region is adjacent to the second conductive type semiconductor.
The beneficial effects of the further scheme are as follows: the PNPN structures in the thyristor region are mutually coupled to form positive feedback when being conducted, so that the conduction voltage drop of the device is effectively reduced.
Still further, the thyristor region comprises a first transistor emitter region, a first transistor base region, a first transistor collector region, a buffer region, an anode emitter region and a seventh electrode;
the first transistor emitter region is arranged at the lower end of the fourth electrode base region, and the first transistor base region is arranged at the lower end of the first transistor emitter region; the first transistor collector region is arranged at the lower end of the first insulating material, the first transistor base region and the second conductive type semiconductor, the buffer region and the anode emitter region are sequentially arranged at the lower end of the first transistor collector region, the seventh electrode is arranged at the lower end of the anode emitter region, and the first transistor base region is adjacent to the second conductive type semiconductor.
The beneficial effects of the further scheme are as follows: the area of the base region of the first transistor is reduced, so that electrons in the device tend to flow to the region, and the control effect on carriers is further enhanced.
Drawings
Fig. 1 is a schematic structural diagram of a hybrid carrier control device including 1 depletion PMOS structure.
Fig. 2 is a schematic diagram of a hybrid carrier control device having two depletion PMOS structures.
Fig. 3 is a schematic view of carrier shunt characteristics in example 2.
Fig. 4 is a schematic view of another carrier shunt characteristic in example 2.
FIG. 5 is a schematic diagram of the anti-electromagnetic interference characteristics of example 2.
Fig. 6 is a schematic view of the shutdown characteristics of example 2.
Fig. 7 is a schematic diagram of a hybrid carrier control device having 3 depletion PMOS structures.
Fig. 8 is a schematic diagram of a hybrid carrier control device with one less NMOS transistor.
Fig. 9 is a schematic diagram of a hybrid carrier control device for reducing the area of the emitter region of the first transistor.
Fig. 10 is a schematic view of a hybrid carrier control device with shortened third insulating material.
Fig. 11 is a schematic diagram of a hybrid carrier control device with a reduced first depletion region.
Fig. 12 is a schematic view of a hybrid carrier control device with an added second conductivity type region.
Fig. 13 is a schematic diagram of a hybrid carrier control device with an enlarged first transistor base region.
Fig. 14 is a schematic view of a hybrid carrier control device structure that extends an electrode into the interior of the second conductivity type.
Wherein 111-the first electrode, 121-the second electrode, 131-the third electrode, 141-the fourth electrode, 151-the fifth electrode, 161-the sixth electrode, 171-the eighth electrode, 101-the seventh electrode, 181-the ninth electrode, 191-the tenth electrode, 201-the first insulating material, 211-the second insulating material, 221-the third insulating material, 231-the fourth insulating material, 241-the fifth insulating material, 301-the fourth electrode heavily doped ohmic contact region, 311-the first transistor emitter region, 321-the first transistor collector region, 331-the buffer region, 401-the fourth electrode base region, 411-the fifth electrode heavily doped ohmic contact region, 421-the sixth electrode ohmic contact region, 431-the first depletion region, 441-the second depletion region, 451-the base region of the first transistor, 461-the semiconductor of the second conductivity type, 471-the anode emitter region, 481-the ninth electrode heavily doped ohmic contact region, 491-the third depletion region.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
The invention provides a hybrid carrier control device, which comprises a main working unit and at least one depletion type PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 are disposed in the fourth electrode base region 401 and at the side edges of the first insulating material 201 and the second insulating material 211, respectively. According to the invention, two NMOS tube structures are formed through the design, and after the first electrode and the second electrode are positively pressurized, the formed NMOS tube can rapidly inject a large number of electron carriers to promote the device to be started.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at a lower end of the first depletion region 431 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. Through the design, when the semiconductor structure is conducted, a part of hole carriers flow into the second conduction type semiconductor, then pass through the first depletion region 431 and the fifth electrode heavily doped ohmic contact region 411 to finally reach the fifth electrode, and the hole carriers in the structure have a shunting effect, so that the conductivity modulation effect of the semiconductor structure during conduction is reduced, the saturation current of the semiconductor structure is effectively reduced, and the safe working area is improved. When the semiconductor device is turned off, all hole carriers pass through the second conductive type semiconductor, and all hole carriers enter the first depletion region 431 and the fifth electrode heavily doped ohmic contact region 411 to finally reach the fifth electrode 151, so that the extraction speed of excess carriers is increased, and the turn-off loss is reduced.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower ends of the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461. The first transistor emitter region 311, the first transistor base region 451, the first transistor collector region 321, the buffer region 331, and the anode emitter region 471 form a PNPN structure unique to a thyristor in the present invention. After the grid drive current exists, the PNPN structures are mutually coupled to form positive feedback, the PNPN structure quickly enters a conducting state from a blocking state, and the conducting voltage drop is low.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211 and the third insulating material 221 are all rectangular, the cross section area of the first insulating material 201 is larger than the cross section areas of the second insulating material 211 and the third insulating material 221, and the cross section areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451 and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121 and the third electrode 131 are the same; the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221, respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is the same as the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is the same as that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221. According to the invention, the PMOS region can be completely depleted through the design, so that an excess carrier extraction channel is formed; after being injected into the structure, the electron and hole carriers can rapidly pass through and finally reach the electrode.
In this embodiment, the cross-sectional area of the first insulating material 201 is larger and is in contact with the first transistor base region 451 and the first transistor collector region 321, so that two NMOS structures are formed on one side of the first insulating material 201, and an electron carrier can be injected rapidly during a conduction process, thereby increasing the turn-on speed of the structure of the present invention.
In this embodiment, in the present invention, the silicon dioxide doped with the first insulating material 201, the second insulating material 211, and the third insulating material 231 forms an oxide layer structure to isolate the metal electrode in the insulating material from the doped region; the heavily doped ohmic contact region 301, the first transistor collector region 321 and the buffer region 331 are doped N-type and can inject electrons when turned on; the fourth electrode base region 401 is P-type doped silicon, and an inversion layer channel is formed in the conduction process; the base region of the first transistor is P-type doped silicon, on one hand, an inversion layer channel is formed in the conduction process, and on the other hand, hole carriers can flow into the region when the first transistor is conducted; the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431 and the second conductivity type semiconductor 461 are P-type doped silicon to form a depletion type PMOS structure, a part of hole carriers flow through the depletion type PMOS structure when the depletion type PMOS structure is switched on, so that the conductance modulation effect is reduced, all surplus carriers flow through the depletion type PMOS structure when the depletion type PMOS structure is switched off, the switching-off speed is increased, and the trailing current and the switching-off loss are reduced.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 of the fifth electrode and the first depletion region 431 are both 1 micron; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thickness of the first transistor emitter region 311 and the first depletion region 431 are both 3 microns; the first transistor base region 451 has a thickness of 1 micron and a length of 12 microns; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 2 micrometers; the thickness of the second insulating material 211 and the third insulating material 221 is 4.2 micrometers, and the length is 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is provided with a second conductive type semiconductor 461; the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, on the basis of a conventional power semiconductor device, the present invention introduces P-type regions with different doping concentrations by combining the principle of shunting electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The invention can realize the function of current carrier shunting by utilizing the concentration difference formed by different doping concentrations of the two P-type regions. In addition, in the right region of the top of the structure of the present invention, a low-doped P-type region is introduced to form a depletion PMOS structure (the third electrode 131, the fifth electrode 151, the third insulating material 221, the fifth electrode heavily-doped ohmic contact region 411, the first depletion region 431, and the second conductivity type semiconductor 461 constitute a depletion PMOS structure). When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of the electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated by the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, the structure of the device is effectively protected, and the device can safely work. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention forms a channel, so that the excess current carriers in the device can be quickly pumped away, the contradiction between conduction voltage drop and turn-off loss is effectively solved, and the performance of the device during turning on and turning off is improved.
In the present embodiment, in the present invention, the silicon dioxide doped with the first insulating material 201, the second insulating material 211, and the third insulating material 231 forms an oxide layer structure to isolate the metal electrode in the insulating material from the doped region; the heavily doped ohmic contact region 301, the first transistor collector region 321 and the buffer region 331 are doped N-type and can inject electrons when turned on; the fourth electrode base region 401 is P-type doped silicon, and an inversion layer channel is formed in the conduction process; the first transistor base region 451 is P-type doped silicon, on one hand, an inversion layer channel is formed in the conducting process, and on the other hand, hole carriers can flow into the region when conducting; the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431 and the second conductivity type semiconductor 461 are P-type doped silicon to form a depletion type PMOS structure, a part of hole carriers flow through the region when the PMOS structure is switched on, so that the conductance modulation effect is reduced, and all excess carriers flow through the region when the PMOS structure is switched off, so that the switching-off speed is increased, and the trailing current and the switching-off loss are reduced.
Example 2
As shown in fig. 2, the present invention provides a hybrid current carrier control device, which includes a main operating unit and two depletion PMOS structures; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the two depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401; the first electrode 111 is disposed in the first insulating material 201; the second electrode 121 is disposed within the second insulating material 211; the fourth electrode 141 is disposed between the first insulating material 201 and the second insulating material 211; the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141; two heavily doped ohmic contact regions 301 of the fourth electrode are respectively disposed at the sides of the first insulating material 201 and the second insulating material 211 in the fourth electrode base region 421.
In this embodiment, the depletion PMOS structure includes a third electrode 131, a fifth electrode 151, a sixth electrode 161, an eighth electrode 171, a third insulating material 221, a fourth insulating material 231, a fifth electrode heavily doped ohmic contact region 411, a sixth electrode heavily doped ohmic contact region 421, a first depletion region 431, a second depletion region 441, and a second conductivity type semiconductor 461; the third electrode 131 is disposed within the third insulating material 221; the eighth electrode 171 is disposed within the fourth insulating material 231; the fifth electrode 151 is provided between the second insulating material 211 and the third insulating material 221; the sixth electrode 161 is disposed between the third insulating material 221 and the fourth insulating material 231; a fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151; the sixth electrode heavily doped ohmic contact region 421 is disposed at a lower end of the sixth electrode 161; a first depletion region 431 is disposed at the lower end of the fifth electrode heavily doped ohmic contact region 411; the second depletion region 441 is disposed at the lower end of the sixth electrode heavily doped ohmic contact region 421; a second conductive type semiconductor 461 is disposed under the first depletion region 431, the third insulating material 221, the second depletion region 441, and the fourth insulating material 231.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101; the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401; the first transistor base region 451 is disposed below the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductivity-type semiconductor 461; the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321; the seventh electrode 101 is disposed at the lower end of the anode emission region 471.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211, the third insulating material 221, and the fourth insulating material 231 are all rectangular; the cross-sectional area of the first insulating material 201 is larger than the cross-sectional areas of the second insulating material 211, the third insulating material 221, and the fourth insulating material 231; the cross-sectional areas of the second insulating material 211, the third insulating material 221, and the fourth insulating material 231 are the same.
In this embodiment, the volumes of the second electrode 121, the third electrode 131 and the eighth electrode 171 embedded by the second insulating material 211, the third insulating material 221 and the fourth insulating material 231 are the same, that is, the cross sections of the insulating materials in the depletion PMOS structure are the same, and the volumes of the electrodes in the depletion PMOS structure are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, the third insulating material 221, and the fourth insulating material 231 are silicon dioxide; the filling material in the heavily doped ohmic contact region 301 of the fourth electrode is N-type doped silicon; the fourth electrode base region 401 is P-type doped silicon; the fifth electrode heavily doped ohmic contact region 411 and the sixth electrode heavily doped ohmic contact region 421 are both P-type doped silicon; the first depletion region 431 and the second depletion region 441 are both P-type doped silicon; the second conductive type semiconductor 461 is P-type doped silicon; the first transistor emitter 311 is N-doped silicon; the first transistor base region 451 is P-type doped silicon; the first transistor collector region 321 is N-doped silicon; the buffer region 331 is N-doped silicon; the anode emitter region 471 is P-doped silicon.
In this embodiment, the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as the length of the sixth electrode heavily doped ohmic contact region 421, the first depletion region 431, and the second depletion region 441; the length of the first transistor collector region 321 is the same as the length of the buffer region 331 and the anode emitter region 471; the length of the first insulating material 201 is the same as the length of the second insulating material 211, the third insulating material 221, and the fourth insulating material 231; the thicknesses of the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411 and the sixth electrode heavily doped ohmic contact region 421 are the same; the thicknesses of the first transistor emitter region 311, the first depletion region 431, and the second depletion region 441 are all the same; the thickness of the first transistor base region 451 is the same as that of the second conductivity type semiconductor 461; the thicknesses of the second insulating material 211, the third insulating material 221, and the fourth insulating material 231 are all the same.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 9 micrometers; the lengths of the fifth electrode heavily doped ohmic contact region 411, the sixth electrode heavily doped ohmic contact region 421, the first depletion region 431 and the second depletion region 441 are all 1 micrometer; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411 and the sixth electrode heavily doped ohmic contact region 421 are all 1 micron; the thicknesses of the first transistor emitter region 311, the first depletion region 431 and the second depletion region 441 are all 3 micrometers; the first transistor base region 451 has a thickness of 1 micron and a length of 10 microns; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 4 micrometers; the second 211, third 221, and fourth 231 insulating materials have a thickness of 4.2 microns and a length of 1 micron; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron.
In this embodiment, the depletion PMOS region is specifically configured in such a manner that the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431 and the third insulating material 221 are in contact with each other and connected together, and the sixth electrode heavily doped ohmic contact region 421 and the second depletion region 441 are located between the third insulating material 221 and the fourth insulating material 231; the depletion PMOS region has a second conductivity type semiconductor 461 at the lower end.
In the embodiment, each structure is provided with one main working unit and two depletion type PMOS structures; the main working unit comprises a grid control area and a thyristor area; the first transistor base region 451 in the main operation unit is disposed adjacent to the second conductivity type semiconductor 461 in the depletion type PMOS structure; the first insulating material 201 in the main operating unit is provided at an end remote from the second conductivity type semiconductor 461.
In this embodiment, on the premise that the first electrode 111, the second electrode 121, the third electrode 131, and the eighth electrode 171 of the present invention are applied with positive voltages, a different voltage is applied to the seventh electrode 101, the heavily doped ohmic contact region 301 of the fourth electrode starts to inject electrons, the anode emission region 471 starts to inject holes, and the device is turned on; current flows through both the main operating region and the depletion PMOS region of the device, and the distribution of electron and hole current densities of the first transistor base region 451 and the second conductivity type semiconductor 461 are different; the electron current density is distributed almost entirely within the first transistor base region 451, as shown in fig. 3; the hole current density is distributed partly in the first transistor base region 451 and partly in the second conductivity type semiconductor 461 as shown in fig. 4. Under the premise that positive voltage is applied to the first electrode 111, the second electrode 121, the third electrode 131 and the eighth electrode 171 of the device, when the seventh electrode 101 is positively biased relative to the fourth electrode 141, the fifth electrode 151 and the sixth electrode 161, the fourth electrode heavily doped ohmic contact region 301 starts to inject electrons, the device is turned on, and since a part of holes flow away from the depletion PMOS region, charges accumulated near the first electrode 111 and the second electrode 121 are reduced, so that the overshoot current at the time of turning on is reduced, as shown in fig. 5; as the resistance applied to the first electrode 111, the second electrode 121, and the third electrode 131 increases, the overshoot current value becomes smaller.
In this embodiment, when the positive voltage of the first electrode 111, the second electrode 121, the third electrode 131, and the eighth electrode 171 of the device is changed to 0V, the device starts to turn off, and at this time, excess carriers existing inside the device are quickly pumped away through the depletion PMOS structure, so that the speed at the initial stage of current drop is fast, the current tailing effect is reduced, and the turn-off loss is reduced, as shown in fig. 6.
In this embodiment, on the basis of a conventional power semiconductor device, the P-type regions with different doping concentrations and a carrier shunt function are introduced by using a carrier shunt principle, and in addition, the low-doping P-type region is introduced in the right side region of the top of the device, so that a depletion type PMOS structure is formed. The invention has small conduction voltage drop when being started, strong anti-electromagnetic interference capability, can quickly pump out the excessive current carriers in the device when being turned off, effectively solves the contradiction relationship between the conduction voltage drop and the turn-off loss, and improves the performance of the device when being turned on and turned off.
Example 3
As shown in fig. 7, the present invention provides a hybrid carrier controller device, which includes a main operating unit and three depletion PMOS structures; the main working unit and the depletion type PMOS structure are respectively arranged at two ends of the MOS grid-controlled thyristor; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401; the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a sixth electrode 161, an eighth electrode 171, a ninth electrode 181, a tenth electrode 191, a third insulating material 221, a fourth insulating material 231, a fifth insulating material 241, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, a sixth electrode heavily doped ohmic contact region 421, a second depletion region 441, a third depletion region 491, a ninth electrode heavily doped ohmic contact region 481, and a second conductivity type semiconductor 461; the depletion type PMOS structure is arranged in a manner that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are in contact with and connected to the third insulating material 221, the sixth electrode heavily doped ohmic contact region 421 and the second depletion region 441 are located between the third insulating material 221 and the fourth insulating material 231, and the ninth electrode heavily doped ohmic contact region 481 and the third depletion region 491 are located between the fourth insulating material 231 and the fifth insulating material 241.
In this embodiment, the volume of the ninth electrode heavily doped ohmic contact region 481 is the same as that of the fifth electrode heavily doped ohmic contact region 411 and the sixth electrode heavily doped ohmic contact region 421, respectively; the volume of the third depletion region 491 is the same as that of the first depletion region 431 and the second depletion region 441, respectively; the volume of the fifth insulating material 241 is the same as the second insulating material 211, the third insulating material 221, and the fourth insulating material 231, respectively; the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 7 microns; the length of the first transistor base region 451 is 8 microns; the length of the second conductive type semiconductor 461 is 6 micrometers. In this embodiment, the turn-on voltage drop is slightly increased, and the turn-off loss is further reduced.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower end of the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211, the third insulating material 221, the fourth insulating material 231, and the fifth insulating material 241 are all rectangular, the cross-sectional area of the first insulating material 201 is larger than the cross-sectional areas of the second insulating material 211, the third insulating material 221, the fourth insulating material 231, and the fifth insulating material 241, and the cross-sectional areas of the second insulating material 211, the third insulating material 221, the fourth insulating material 231, and the fifth insulating material 241 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, the third insulating material 221, the fourth insulating material 231, and the fifth insulating material 241 are all silicon dioxide; the heavily doped ohmic contact region 301 of the fourth electrode, the collector region 321 of the first transistor and the buffer region 331 are all N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the sixth electrode heavily doped ohmic contact region 421, the first depletion region 431, the second depletion region 441, the second conductivity type semiconductor 461, the ninth electrode heavily doped ohmic contact region 481, the third depletion region 491, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121, the third electrode 131, the eighth electrode 171 and the tenth electrode 191 are the same; the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as the length of the first depletion region 431, the sixth electrode heavily doped ohmic contact region 421, the second depletion region 441, the ninth electrode heavily doped ohmic contact region 481 and the third depletion region 491; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211, the third insulating material 221, the fourth insulating material 231 and the fifth insulating material 241 respectively; the thickness of the fourth electrode base region 401 is the same as the thickness of the fifth electrode heavily doped ohmic contact region 411, the sixth electrode heavily doped ohmic contact region 421 and the ninth electrode heavily doped ohmic contact region 481; the thickness of the first transistor emitter region 311 is the same as the thickness of the first, second, and third depletion regions 431, 441, 491; the thickness of the first transistor base region 451 is the same as that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221, the fourth insulating material 231, and the fifth insulating material 241.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 7 micrometers; the lengths of the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the sixth electrode heavily doped ohmic contact region 421, the second depletion region 441, the ninth electrode heavily doped ohmic contact region 481 and the third depletion region 491 are all 1 micrometer; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the sixth electrode heavily doped ohmic contact region 421 and the ninth electrode heavily doped ohmic contact region 481 are all 1 micron; the thicknesses of the first transistor emitter region 311 and the first, second and third depletion regions 431, 441, 491 are all 3 microns; the first transistor base region 451 has a thickness of 1 micron and a length of 8 microns; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 6 micrometers; the second insulating material 211, the third insulating material 221, the fourth insulating material 231, and the fifth insulating material 241 have a thickness of 4.2 micrometers and a length of 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically configured in such a way that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are in contact with and connected to the third insulating material 221, the sixth electrode heavily doped ohmic contact region 421 and the second depletion region 441 are located between the third insulating material 221 and the fourth insulating material 231, and the ninth electrode heavily doped ohmic contact region 481 and the third depletion region 491 are located between the fourth insulating material 231 and the fifth insulating material 241; the lower end of the depletion type PMOS region is provided with a second conductive type semiconductor 461; the first insulating material 201 is provided at an end remote from the second conductivity type semiconductor 461. In this embodiment, the turn-on voltage drop is reduced and the turn-off loss is slightly increased.
In this embodiment, the first transistor base region 451 and the second conductivity type semiconductor 461, which have different doping concentrations, are introduced based on a conventional power semiconductor device by using a carrier shunt principle. The two regions, due to the concentration difference, can successfully separate electrons from hole carriers during device operation. After the current carriers are separated, the conductance modulation effect of the device during conduction can be effectively reduced, and current saturation can be achieved more quickly. And in the opening process, the accumulation of carriers near the gate electrode is reduced, so that the overshoot current of the opening transient state is reduced. Meanwhile, a depletion type PMOS structure is introduced, and the third electrode 131, the fifth electrode 151, the sixth electrode 161, the eighth electrode 171, the ninth electrode 181, the tenth electrode 191, the third insulating material 221, the fourth insulating material 231, the fifth insulating material 241, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the sixth electrode heavily doped ohmic contact region 421, the second depletion region 441, the ninth electrode heavily doped ohmic contact region 481, the third depletion region 491 and the second conductivity type semiconductor 461 form three depletion type PMSO structures. The invention effectively solves the contradiction between the conduction voltage drop and the turn-off loss, and improves the performance of the device during the turn-on and turn-off.
Example 4
As shown in fig. 8, the present invention provides a hybrid current carrier control device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401; the first electrode 111 is arranged in the first insulating material 201, the fourth electrode 141 is arranged between the first insulating material 201 and the second insulating material 211, the fourth electrode base region 401 is arranged at the lower end of the fourth electrode 141, and the fourth electrode heavily-doped ohmic contact region 301 is arranged on one side, close to the first insulating material 201, in the fourth electrode base region 401.
In this embodiment, the depletion PMOS regions each include a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; the depletion PMOS structure is arranged in such a way that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431 and the third insulating material 221 are in contact with each other and connected together.
In this embodiment, the volume of the second insulating material 211 is the same as the volume of the third insulating material 221; the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 microns; the first transistor base region 451 is 12 microns in length; the length of the second conductive type semiconductor 461 is 2 micrometers. In this embodiment, since no electrode is added in the second insulating material 211, it only plays a role of isolation. The number of NMOS tubes in the invention is reduced, the electron injection amount during conduction is reduced, and the starting speed is slowed down. However, since the depletion PMOS structure still exists, excess carriers can be extracted quickly, and the turn-off loss is reduced.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower end of the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all rectangular, the cross section area of the first insulating material 201 is larger than the cross section areas of the second insulating material 211 and the third insulating material 221, and the cross section areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the length of the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is the same as the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is the same as that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 of the fifth electrode and the first depletion region 431 are both 1 micron; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thickness of the first transistor emitter region 311 and the first depletion region 431 are both 3 microns; the first transistor base region 451 has a thickness of 1 micron and a length of 12 microns; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 2 micrometers; the second insulating material 211 and the third insulating material 221 have a thickness of 4.2 micrometers and a length of 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion PMOS region is specifically configured in such a way that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431 and the third insulating material 221 are in contact with each other and connected together.
In this embodiment, the first transistor base region 451 and the second conductivity type semiconductor 461 with different doping concentrations are introduced based on a conventional power semiconductor device by using a carrier shunt principle. The two regions, due to the concentration difference, can successfully separate electrons from hole carriers during device operation. After the current carriers are separated, the conductance modulation effect of the device during conduction can be effectively reduced, and current saturation can be achieved more quickly. And in the opening process, the accumulation of carriers near the gate electrode is reduced, so that the overshoot current of the opening transient state is reduced. At the same time, a second insulating material 211 is introduced, separating the main operating region of the device from the carrier extraction channel. When the PMOS transistor is turned off, the carriers can completely enter the depletion type PMOS structure and are quickly pumped away, and the trailing current is reduced. The invention improves the compromise relation between the on-state voltage drop and the off-state loss and improves the performance of the device during the on-state and the off-state.
Example 5
As shown in fig. 9, the present invention provides a hybrid carrier controller device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a grid control area and a thyristor area, the grid control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at a lower end of the first depletion region 431 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower ends of the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211 and the third insulating material 221 are all rectangular, the cross section area of the first insulating material 201 is larger than the cross section areas of the second insulating material 211 and the third insulating material 221, and the cross section areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121 and the third electrode 131 are the same; the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is smaller than the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is larger than that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 of the fifth electrode and the first depletion region 431 are both 1 micron; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thicknesses of the first transistor emitter region 311 and the first depletion region 431 are both 2 micrometers; the first transistor base region 451 is 2 microns thick and 12 microns long; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 2 micrometers; the thickness of the second insulating material 211 and the third insulating material 221 is 4.2 micrometers, and the length is 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is provided with a second conductive type semiconductor 461; the first insulating material 201 is provided at an end remote from the second conductivity type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, the present invention introduces P-type regions with different doping concentrations and areas based on a basic power semiconductor device and by combining a principle of shunting electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The concentration difference formed between the two P-type regions is utilized, so that the invention can realize the function of current carrier shunting. In addition, in the right region of the top of the structure of the present invention, a low-doped P-type region is introduced to form a depletion PMOS structure (the third electrode 131, the fifth electrode 151, the third insulating material 221, the fifth electrode heavily-doped ohmic contact region 411, the first depletion region 431, and the second conductivity type semiconductor 461 constitute a depletion PMOS structure). When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated by the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, the structure of the device is effectively protected, and the device can safely work. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention forms a channel, so that the excess current carriers in the device can be quickly pumped away, the contradiction between conduction voltage drop and turn-off loss is effectively solved, and the performance of the device during turning on and turning off is improved.
Example 6
As shown in fig. 10, the present invention provides a hybrid carrier controller device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each depletion PMOS region includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at lower ends of the first depletion region 431 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower ends of the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross-sections of the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all rectangular, the cross-sectional area of the first insulating material 201 is larger than the cross-sectional areas of the second insulating material 211 and the third insulating material 221, and the cross-sectional area of the second insulating material 211 is larger than the cross-sectional area of the third insulating material 221.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volume of the second electrode 121 is larger than that of the third electrode 131; the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is greater than the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is smaller than the thickness of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is greater than the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 and the first depletion region 431 of the fifth electrode are both 1 micrometer; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thickness of the first transistor emitter region 311 is 3 microns; the thickness of the first depletion region 431 is 2 microns; the first transistor base region 451 has a thickness of 1 micron and a length of 12 microns; the second conductivity type semiconductor 461 has a thickness of 2 micrometers and a length of 2 micrometers; the second insulating material 211 has a thickness of 4.2 microns and a length of 1 micron; the third insulating material 221 has a thickness of 3.2 microns and a length of 1 micron; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is a second conductivity type semiconductor 461; the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, the present invention introduces P-type regions with different doping concentrations and areas based on a basic power semiconductor device and by combining a principle of shunting electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The concentration difference formed by the two P-type regions is utilized, so that the invention can realize the function of current carrier shunting. In addition, in the right region of the top of the structure of the present invention, a low-doped P-type region is introduced to form a depletion PMOS structure (the third electrode 131, the fifth electrode 151, the third insulating material 221, the fifth electrode heavily-doped ohmic contact region 411, the first depletion region 431, and the second conductivity type semiconductor 461 constitute a depletion PMOS structure). When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of the electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated by the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, the structure of the device is effectively protected, and the device can safely work. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention forms a carrier fast extraction channel, so that the current reduction speed during the turn-off is accelerated, the trailing effect is weakened, the turn-off loss is reduced, the compromise relation between the turn-on voltage drop and the turn-off loss is effectively improved, and the performance of the device is improved.
Example 7
As shown in fig. 11, the present invention provides a hybrid current carrier control device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at a lower end of the first depletion region 431 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower ends of the first transistor emitter region 311 and the second insulating material 211; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross-sections of the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all rectangular, the cross-sectional area of the first insulating material 201 is larger than the cross-sectional areas of the second insulating material 211 and the third insulating material 221, and the cross-sectional areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121 and the third electrode 131 are the same; the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is greater than the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is smaller than the thickness of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 of the fifth electrode and the first depletion region 431 are both 1 micron; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thickness of the first transistor emitter region 311 is 3 microns; the thickness of the first depletion region 431 is 2 microns; the first transistor base region 451 is 1 micron thick and 12 microns long; the second conductivity type semiconductor 461 has a thickness of 2 micrometers and a length of 2 micrometers; the thickness of the second insulating material 211 and the third insulating material 221 is 4.2 micrometers, and the length is 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is a second conductivity type semiconductor 461; the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, on the basis of a conventional power semiconductor device, a P-type region with different doping concentrations and areas is introduced by combining the shunting principle of electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The concentration difference formed by the two P-type regions is utilized, so that the invention can realize the function of current carrier shunting. In addition, a low-doped P-type region is introduced into the right region at the top of the structure to form a depletion type PMOS structure. When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of the electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated by the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, the structure of the device is effectively protected, and the device can safely work. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention provides a channel, so that the excess current carriers in the device can be quickly pumped away, the turn-off loss of the device is effectively reduced, and the performance of the device during turn-on and turn-off is improved.
Example 8
As shown in fig. 12, the present invention provides a hybrid carrier controller device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at lower ends of the first depletion region 431, the second insulating material 211 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end far from the second conductive type semiconductor 461.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower end of the first transistor emitter region 311; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211 and the third insulating material 221 are all rectangular, the cross section area of the first insulating material 201 is larger than the cross section areas of the second insulating material 211 and the third insulating material 221, and the cross section areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121 and the third electrode 131 are the same; the length of the fourth electrode base region 401 is the same as the lengths of the first transistor emitter region 311 and the first transistor base region 451; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is the same as the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is the same as that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 of the fifth electrode and the first depletion region 431 are both 1 micron; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thickness of the first transistor emitter region 311 and the first depletion region 431 are both 3 microns; the first transistor base region 451 has a thickness of 1 micron and a length of 11 microns; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 3 micrometers; the thickness of the second insulating material 211 and the third insulating material 221 is 4.2 micrometers, and the length is 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is provided with a second conductive type semiconductor 461; the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, on the basis of a conventional power semiconductor device, a P-type region with different doping concentrations and areas is introduced by combining the shunting principle of electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The concentration difference formed by the two P-type regions is utilized, so that the invention can realize the function of current carrier shunting. In addition, a low-doped P-type region is introduced into the right side region at the top of the structure to form a depletion type PMOS structure. When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of the electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated in the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, and the device is effectively protected. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention can quickly pump away the excess carriers in the device, thereby improving the compromise relationship between the conduction voltage drop and the turn-off loss and improving the performance of the device when the device is turned on and turned off.
Example 9
As shown in fig. 13, the present invention provides a hybrid current carrier control device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a grid control area and a thyristor area, the grid control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at lower ends of the first depletion region 431, the second insulating material 211 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end far from the second conductive type semiconductor 461.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower end of the first transistor emitter region 311; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross-sections of the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all rectangular, the cross-sectional area of the first insulating material 201 is larger than the cross-sectional areas of the second insulating material 211 and the third insulating material 221, and the cross-sectional areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121 and the third electrode 131 are the same; the length of the fourth electrode base region 401 is the same as the lengths of the first transistor emitter region 311 and the first transistor base region 451; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is smaller than the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is larger than that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 and the first depletion region 431 of the fifth electrode are both 1 micrometer; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thickness of the first transistor emitter region 311 is 2 microns; the first depletion regions 431 are each 3 microns thick; the first transistor base region 451 has a thickness of 2 microns and a length of 11 microns; the second conductivity type semiconductor 461 has a thickness of 1 micrometer and a length of 3 micrometers; the second insulating material 211 and the third insulating material 221 have a thickness of 4.2 micrometers and a length of 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is provided with a second conductive type semiconductor 461; the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, on the basis of a conventional power semiconductor device, a P-type region with different doping concentrations and areas is introduced by combining the shunting principle of electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The concentration difference formed by the two P-type regions is utilized, so that the invention can realize the function of current carrier shunting. In addition, a low-doped P-type region is introduced into the right side region at the top of the structure to form a depletion type PMOS structure. When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of the electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated by the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, the structure of the device is effectively protected, and the device can safely work. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention can quickly pump away the excess carriers in the device, and effectively improves the contradiction between the conduction voltage drop and the turn-off loss.
Example 10
As shown in fig. 14, the present invention provides a hybrid carrier controller device comprising a main operating unit and at least one depletion PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
In this embodiment, the gate control region includes a first electrode 111, a first insulating material 201, a second electrode 121, a second insulating material 211, a fourth electrode 141, a fourth electrode heavily doped ohmic contact region 301, and a fourth electrode base region 401;
the first electrode 111 is disposed in the first insulating material 201, the second electrode 121 is disposed in the second insulating material 211, the fourth electrode base region 401 is disposed at the lower end of the fourth electrode 141, and the two heavily doped ohmic contact regions 301 of the fourth electrode are disposed in the fourth electrode base region 401 and at the sides of the first insulating material 201 and the second insulating material 211, respectively.
In this embodiment, each of the depletion PMOS regions includes a third electrode 131, a fifth electrode 151, a third insulating material 221, a fifth electrode heavily doped ohmic contact region 411, a first depletion region 431, and a second conductivity type semiconductor 461; each depletion type PMOS region is disposed in such a manner that the heavily doped ohmic contact region 411 of the fifth electrode, the first depletion region 431, and the third insulating material 221 are in contact and connected together.
The third electrode 131 is disposed in the third insulating material 221, the fifth electrode 151 is disposed between the third insulating material 221 and the second insulating material 211, the fifth electrode heavily doped ohmic contact region 411 is disposed at a lower end of the fifth electrode 151, the first depletion region 431 is disposed at a lower end of the fifth electrode heavily doped ohmic contact region 411, the second conductive type semiconductor 461 is disposed at lower ends of the first depletion region 431, the second insulating material 211 and the third insulating material 221, the thyristor region is adjacent to the second conductive type semiconductor 461, and the first insulating material 201 is disposed at an end far from the second conductive type semiconductor 461.
In this embodiment, the thyristor region includes a first transistor emitter region 311, a first transistor base region 451, a first transistor collector region 321, a buffer region 331, an anode emitter region 471, and a seventh electrode 101;
the first transistor emitter region 311 is disposed at the lower end of the fourth electrode base region 401, and the first transistor base region 451 is disposed at the lower end of the first transistor emitter region 311; the first transistor base region 321 is disposed at the lower end of the first insulating material 201, the first transistor base region 451, and the second conductive type semiconductor 461, the buffer region 331 and the anode emitter region 471 are sequentially disposed at the lower end of the first transistor collector region 321, the seventh electrode 101 is disposed at the lower end of the anode emitter region 471, and the first transistor base region 451 is adjacent to the second conductive type semiconductor 461.
In this embodiment, the cross sections of the first insulating material 201, the second insulating material 211 and the third insulating material 221 are all rectangular, the cross section area of the first insulating material 201 is larger than the cross section areas of the second insulating material 211 and the third insulating material 221, and the cross section areas of the second insulating material 211 and the third insulating material 221 are the same.
In this embodiment, the first insulating material 201, the second insulating material 211, and the third insulating material 221 are all silicon dioxide; the heavily doped ohmic contact region 301, the first transistor emitter region 311, the first transistor collector region 321 and the buffer region 331 are all made of N-type doped silicon; the fourth electrode base region 401, the fifth electrode heavily doped ohmic contact region 411, the first depletion region 431, the second conductivity type semiconductor 461, the first transistor base region 451, and the anode emitter region 471 are all P-type doped silicon.
In this embodiment, the volumes of the second electrode 121 and the third electrode 131 are the same; the length of the fourth electrode base region 401 is the same as the length of the first transistor emitter region 311 and the length of the first transistor base region 451; the length of the fifth electrode heavily doped ohmic contact region 411 is the same as that of the first depletion region 431; the lengths of the first transistor collector region 321 are the same as the lengths of the buffer region 331 and the anode emitter region 471, respectively; the length of the first insulating material 201 is the same as the length of the second insulating material 211 and the third insulating material 221 respectively; the thickness of the fourth electrode base region 401 is the same as that of the fifth electrode heavily doped ohmic contact region 411; the thickness of the first transistor emitter region 311 is the same as the thickness of the first depletion region 431; the thickness of the first transistor base region 451 is the same as that of the second conductivity type semiconductor 461; the thickness of the second insulating material 211 is the same as the thickness of the third insulating material 221.
In this embodiment, the lengths of the fourth electrode base region 401 and the first transistor emitter region 311 are both 11 micrometers; the lengths of the heavily doped ohmic contact region 411 and the first depletion region 431 of the fifth electrode are both 1 micrometer; the lengths of the first transistor collector region 321, the buffer region 331 and the anode emitter region 471 are all 15 micrometers; the thicknesses of the fourth electrode base region 401 and the fifth electrode heavily doped ohmic contact region 411 are both 1 micrometer; the thicknesses of the first transistor emitter region 311 and the first depletion region 431 are both 2 micrometers; the first transistor base region 451 is 2 microns thick and 12 microns long; the second conductivity type semiconductor 461 has a thickness of 2 micrometers and a length of 2 micrometers; the thickness of the second insulating material 211 and the third insulating material 221 is 4.2 micrometers, and the length is 1 micrometer; the first insulating material 201 has a thickness of 5.3 microns and a length of 1 micron; the depletion type PMOS region is specifically arranged in a mode that the fifth electrode heavily doped ohmic contact region 411 and the first depletion region 431 are contacted and connected with the third insulating material 221; the lower end of the depletion type PMOS region is provided with a second conductive type semiconductor 461; the first insulating material 201 is disposed at an end away from the second conductive type semiconductor 461. In the embodiment, the conduction voltage drop is reduced, and the turn-off loss is smaller.
In this embodiment, on the basis of a conventional power semiconductor device, a P-type region with different doping concentrations and areas is introduced by combining the shunting principle of electron and hole carriers: a first transistor base region 451 and a second conductivity type semiconductor 461. The concentration difference formed by the two P-type regions is utilized, so that the invention can realize the function of current carrier shunting. In addition, a low-doped P-type region is introduced into the right side region at the top of the structure to form a depletion type PMOS structure. When the invention is conducted, the conducting voltage drop is small. In the opening transient state, due to the shunting effect of the electron and hole carriers, the charge quantity accumulated near the gate electrode is reduced, so that the overshoot current generated by the opening transient state is reduced, the anti-electromagnetic interference capability is enhanced, the structure of the device is effectively protected, and the device can safely work. Meanwhile, when the device is turned off, the depletion type PMOS structure introduced by the invention provides a channel for quickly pumping away carriers, so that the turn-off loss of the device is reduced, the compromise relation between the turn-on voltage drop and the turn-off loss is effectively improved, and the performance of the device during turning on and off is improved.
The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (7)

1. A hybrid carrier control device comprising a main operating unit and at least one depletion mode PMOS structure; the main working unit comprises a gate control area and a thyristor area, the gate control area, the depletion type PMOS area and the thyristor area are arranged from top to bottom, and the depletion type PMOS structures are arranged in parallel in an adjacent mode.
2. The hybrid carrier controller of claim 1, wherein the gate control region comprises a first electrode (111), a first insulating material (201), a second insulating material (211), a fourth electrode (141), a fourth electrode heavily doped ohmic contact region (301), and a fourth electrode base region (401);
the first electrode (111) is arranged in the first insulating material (201), the fourth electrode base region (401) is arranged at the lower end of the fourth electrode (141), and the heavily doped ohmic contact region (301) of the fourth electrode is arranged in the fourth electrode base region (401) and is positioned at the side edge of the first insulating material (201).
3. The hybrid carrier controller of claim 1, wherein the gate control region comprises a first electrode (111), a first insulating material (201), a second electrode (121), a second insulating material (211), a fourth electrode (141), a fourth electrode heavily doped ohmic contact region (301), and a fourth electrode base region (401);
the first electrode (111) is arranged in the first insulating material (201), the second electrode (121) is arranged in the second insulating material (211), the fourth electrode base region (401) is arranged at the lower end of the fourth electrode (141), and the fourth electrode heavily-doped ohmic contact region (301) is arranged in the fourth electrode base region (401) and is respectively positioned on the lateral sides of the first insulating material (201) and the second insulating material (211).
4. The hybrid current carrier controller of claim 3, wherein each depletion type PMOS region comprises a third electrode (131), a fifth electrode (151), a third insulating material (221), a fifth electrode heavily doped ohmic contact region (411), a first depletion region (431), and a second conductivity type semiconductor (461); the depletion type PMOS regions are arranged in parallel in a mode that the fifth electrode heavily-doped ohmic contact region (411) and the first depletion region (431) are in contact connection with a third insulating material (221);
the third electrode (131) is disposed in the third insulating material (221), the fifth electrode (151) is disposed between the third insulating material (221) and the second insulating material (211), the fifth electrode heavily doped ohmic contact region (411) is disposed at a lower end of the fifth electrode (151), the first depletion region (431) is disposed at a lower end of the fifth electrode heavily doped ohmic contact region (411), the second conductive type semiconductor (461) is disposed at a lower end of the first depletion region (431) and the third insulating material (221), the thyristor region is adjacent to the second conductive type semiconductor (461), and the first insulating material (201) is disposed at an end far from the second conductive type semiconductor (461).
5. The hybrid carrier control device according to claim 4, wherein each of the depletion type PMOS regions comprises a third electrode (131), a fifth electrode (151), a third insulating material (221), a fifth electrode heavily doped ohmic contact region (411), a first depletion region (431), and a second conductivity type semiconductor (461); the depletion type PMOS regions are arranged in parallel in a mode that the fifth electrode heavily-doped ohmic contact region (411) and the first depletion region (431) are in contact connection with a third insulating material (221);
the third electrode (131) is disposed in the third insulating material (221), the fifth electrode (151) is disposed between the third insulating material (221) and the second insulating material (211), the fifth electrode heavily doped ohmic contact region (411) is disposed at a lower end of the fifth electrode (151), the first depletion region (431) is disposed at a lower end of the fifth electrode heavily doped ohmic contact region (411), the second conductivity type semiconductor (461) is disposed at a lower end of the second insulating material (211), the first depletion region (431) and the third insulating material (221), the thyristor region is adjacent to the second conductivity type semiconductor (461), and the first insulating material (201) is disposed at an end far away from the second conductivity type semiconductor (461).
6. The hybrid carrier control device of claim 5, wherein the thyristor region comprises a first transistor emitter region (311), a first transistor base region (451), a first transistor collector region (321), a buffer region (331), an anode emitter region (471), and a seventh electrode (101);
the first transistor emitter region (311) is arranged at the lower end of the fourth electrode base region (401), and the first transistor base region (451) is arranged at the lower ends of the first transistor emitter region (311) and the second insulating material (211); the first transistor collector region (321) is arranged at the lower end of the first insulating material (201), the first transistor base region (451) and the second conductive type semiconductor (461), the buffer region (331) and the anode emitter region (471) are sequentially arranged at the lower end of the first transistor collector region (321), the seventh electrode (101) is arranged at the lower end of the anode emitter region (471), and the first transistor base region (451) is adjacent to the second conductive type semiconductor (461).
7. The hybrid carrier control device of claim 5, wherein the thyristor region comprises a first transistor emitter region (311), a first transistor base region (451), a first transistor collector region (321), a buffer region (331), an anode emitter region (471), and a seventh electrode (101);
the first transistor emitter region (311) is arranged at the lower end of the fourth electrode base region (401), and the first transistor base region (451) is arranged at the lower end of the first transistor emitter region (311); the first transistor collector region (321) is arranged at the lower end of the first insulating material (201), the first transistor base region (451) and the second conductive type semiconductor (461), the buffer region (331) and the anode emitter region (471) are sequentially arranged at the lower end of the first transistor collector region (321), the seventh electrode (101) is arranged at the lower end of the anode emitter region (471), and the first transistor base region (451) is adjacent to the second conductive type semiconductor (461).
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