CN112289814A - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN112289814A CN112289814A CN202011182557.3A CN202011182557A CN112289814A CN 112289814 A CN112289814 A CN 112289814A CN 202011182557 A CN202011182557 A CN 202011182557A CN 112289814 A CN112289814 A CN 112289814A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
An array substrate, a preparation method thereof and a display device are provided, wherein the array substrate comprises: the substrate comprises a substrate base plate and a cutting and binding device, wherein the substrate base plate comprises a display area and an edge area, the edge area comprises a cutting reserved area and a binding area, and the binding area is positioned between the display area and the cutting reserved area; a planarization layer on the display region and the edge region, and exposing the cutting reserved region and the binding region; an electrode spacer on a portion of the cutting reserve and in contact with the planarization layer; the electrode layer is positioned on the display area and positioned on the surface of one side, away from the substrate, of the planarization layer; the bonding connecting lines are electrically connected with the bonding regions and extend from the bonding regions to the cutting reserved regions along the top surfaces of the planarization layers; the electrode spacers are arranged on the cutting reserved areas between the adjacent binding connection lines. The array substrate can avoid the display area from generating dark lines.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
An Organic Light-Emitting Diode (OLED) display is a display device with great development prospect, and has the characteristics of self-luminescence, simple structure, ultra-thinness, high response speed, wide viewing angle, low power consumption, flexible display and the like, and is favored by various display manufacturers. Compared with the LCD display, the OLED display has the advantages of thinness, lightness, wide visual angle, active luminescence, continuously adjustable luminescence color, low cost, high response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high luminescence efficiency, flexible display and the like, and the investment of production equipment is far less than that of the LCD display. The OLED display is a great concern in the industry and the scientific community because of its incomparable advantages and good application prospects.
However, the display area of the prior art OLED display is prone to dark lines.
Disclosure of Invention
The invention aims to solve the technical problem of generating dark lines in a display area in the prior art.
In order to solve the above technical problem, the present invention provides an array substrate, including: the substrate comprises a display area and an edge area surrounding the display area, wherein the edge area comprises a cutting reserved area and a binding area, and the binding area is positioned between the display area and the cutting reserved area; a planarization layer on the display region and the edge region, and exposing the cutting reserved region and the binding region; an electrode spacer on a portion of the cutting reserve and in contact with the planarization layer; the electrode layer is positioned on the display area and positioned on the surface of one side, away from the substrate, of the planarization layer; the bonding connecting lines extend from the bonding regions to the cutting reserved regions along the top surfaces of the planarization layers, and the electrode spacers are arranged on the cutting reserved regions between the adjacent bonding connecting lines.
Optionally, the electrode spacer comprises a first host material layer; the electrode layer includes a second main material layer having a material reducibility stronger than that of the first main material layer.
Optionally, the material of the first main material layer includes Ti, and the material of the second main material layer includes ITO.
Optionally, the binding region is provided with a plurality of conductive connecting lines; the planarization layer exposes the conductive connection line; the binding connecting lines are electrically connected with the conductive connecting lines respectively; the electrode spacer and the conductive connecting line are arranged in the same layer.
Optionally, the electrode spacer has the same structure as the conductive connection line.
Optionally, the electrode spacer comprises a Ti/Al/Ti structure.
Optionally, the electrode spacers and the conductive connection lines are separated from each other, and the electrode spacers are located between the adjacent binding connection lines.
Optionally, the electrode spacers are spaced apart from adjacent ones of the bonding wires by equal distances.
Optionally, the width of the electrode spacer occupies 1/6-1/5 of the spacing between adjacent bonding wires.
Optionally, the electrode spacer is connected to the conductive connection line in an extending direction of the conductive connection line, a partial region of the electrode spacer is covered by the bonding connection line, and a width of the electrode spacer is greater than a width of the conductive connection line and greater than a width of the bonding connection line.
Optionally, the electrode spacer and the width difference 1/2 of the bonding connection line occupy 1/6 ~ 1/5 of the spacing between adjacent bonding connection lines.
Optionally, a partial region of the electrode spacer extends to an edge region between the cutting reserved region and the binding region and is covered by the planarization layer.
The invention also provides a preparation method of the array substrate, which comprises the following steps: providing a substrate base plate, wherein the substrate base plate comprises a display area and an edge area surrounding the display area, the edge area comprises a cutting reserved area and a binding area, and the binding area is positioned between the display area and the cutting reserved area; forming an electrode spacer on a portion of the cutting margin; forming a planarization layer on the display region and the edge region, and the planarization layer exposes the cutting margin region and the binding region, the electrode spacer being in contact with the planarization layer; forming an electrode layer on the display area, wherein the electrode layer is positioned on the surface of the planarization layer on the side away from the substrate base plate; and forming a plurality of binding connection lines electrically connected with the binding regions on the binding regions, wherein the binding connection lines extend from the binding regions along the top surface of the planarization layer to the cutting reserved regions, and the electrode spacers are arranged on the cutting reserved regions between the adjacent binding connection lines.
Optionally, before forming the planarization layer, the bonding region is provided with a plurality of conductive connection lines; forming the electrode spacer in a process of forming the conductive connection line; after forming the planarization layer, the planarization layer exposes the conductive connection line; the binding connecting lines are electrically connected with the conductive connecting lines respectively.
Optionally, the electrode spacer comprises a first main material layer, the electrode layer comprises a second main material layer, and the material reducibility of the second main material layer is stronger than that of the first main material layer; the preparation method for forming the electrode layer comprises the following steps: forming an electrode material film on the planarization layer, the cutting reservation region and the binding region; etching the electrode material film by adopting a wet etching process to remove the electrode material film on the cutting reserved area and the binding area and part of the electrode material film on the planarization layer to form the electrode layer; in the process of carrying out the wet etching process, the second main material layer in the electrode material film, the first main material layer in the electrode spacer and the etching solution which are positioned on the cutting reserved area and close to the edge of the planarization layer carry out electrochemical reaction, the second main material layer is used as a negative electrode of the electrochemical reaction, and the first main material layer in the electrode spacer is used as a positive electrode of the electrochemical reaction.
Optionally, the electrode spacers and the conductive connection lines are separated from each other, and the electrode spacers are located between the adjacent binding connection lines.
Optionally, the electrode spacer is connected to the conductive connection line in an extending direction of the conductive connection line, a partial region of the electrode spacer is covered by the bonding connection line, and a width of the electrode spacer is greater than a width of the conductive connection line and greater than a width of the bonding connection line.
The invention also provides a display device comprising the array substrate.
The technical scheme of the invention has the following advantages:
1. according to the array substrate provided by the technical scheme of the invention, the cutting reserved area is an area which is reserved for cutting the substrate and is positioned near the cutting channel, and the planarization layer does not cover the cutting reserved area, so that the planarization layer is not influenced by cutting and does not influence the cutting process in the cutting process of the substrate. Because the electrode spacing piece which is contacted with the planarization layer is arranged on part of the cutting reserved area and is used for preventing the electrode material film adopted in the preparation process of the electrode layer from remaining on the cutting reserved area, and because the electrode material film cannot remain on the edge of the planarization layer facing the cutting reserved area, even if the binding connecting lines extend to the cutting reserved area, the adjacent binding connecting lines cannot be shorted together, so that the display area is prevented from generating dark lines.
2. Further, the electrode spacer includes a first host material layer; the electrode layer includes a second main material layer having a material reducibility stronger than that of the first main material layer. The electrode spacer is suitable for participating in electrochemical regulation in the process of forming the electrode layer, even if the electrode residual material is formed on the cutting reserved area at the initial moment in the process of forming the electrode layer, the second main material layer in the electrode residual material can be used as a negative electrode of electrochemical reaction, and the first main material layer in the electrode spacer can be used as a positive electrode of the electrochemical reaction, so that the electrode residual material loses electrons and is reduced, and the electrode residual material is finally removed in the process of the electrochemical reaction, the electrode layer material cannot be remained on the cutting reserved area, and adjacent binding connecting lines cannot be shorted together, so that a display area is prevented from appearing dark lines.
3. Furthermore, the binding region is provided with a plurality of conductive connecting lines; the planarization layer exposes the conductive connection line; the binding connecting lines are electrically connected with the conductive connecting lines respectively; the electrode spacer and the conductive connection line are arranged on the same layer, so that the electrode spacer can be formed by using a process for forming the conductive connection line without an additional process for forming the electrode spacer.
4. In the preparation method of the array substrate provided by the technical scheme of the invention, because the electrode spacing piece in contact with the planarization layer is arranged on part of the cutting reserved area, the electrode spacing piece is used for preventing the material of the electrode layer from remaining on the cutting reserved area, and the material of the electrode layer cannot remain on the edge of the planarization layer facing the cutting reserved area, even if the binding connecting line extends to the cutting reserved area, the adjacent binding connecting lines cannot be shorted together, so that the display area is prevented from generating a dark line.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a top view of an array substrate;
FIG. 2 is a schematic sectional view taken along the line M-M1 in FIG. 1;
fig. 3 is a top view of an array substrate according to an embodiment of the invention;
FIG. 4 is a cross-sectional view of the array substrate taken along line N-N1 in FIG. 3 according to an embodiment of the present invention;
fig. 5 is a top view of an array substrate according to another embodiment of the present invention;
fig. 6 is a flowchart illustrating a manufacturing process of an array substrate according to another embodiment of the present invention.
Detailed Description
As described in the background, the display area of the array substrate in the related art is prone to generate dark lines.
An array substrate, referring to fig. 1 and 2 in combination, comprising: a substrate base plate 100, the substrate base plate 100 including a display region C1 and an edge region D1, the edge region D1 including a cutting reserved region a and a binding region B, the binding region B being located between the display region C1 and the cutting reserved region a; a planarization layer 110 on the display region C1 and the edge region D1, and the planarization layer 110 exposes the cutting reservation region a and the binding region B; an anode layer 120 located on the display region C1 and located on a surface of the planarization layer 110 on a side facing away from the substrate 100; a plurality of bonding wires 130 electrically connected to the conductive connection wires 160 of the bonding region B, the bonding wires 130 extending from the bonding region B along the top surface of the planarization layer 110 onto the cutting-reserved region a.
The cutting reserved area a is an area reserved for cutting the substrate 100 and located near a cutting path, and the planarization layer 110 does not cover the cutting reserved area, so that the planarization layer 110 is not affected by cutting in the cutting process of the substrate 100, specifically, the cutting process does not contact the planarization layer 110 to avoid tearing the film layer of the planarization layer 110, on the other hand, the planarization layer 110 does not affect the cutting process, and specifically, the material of the planarization layer 110 does not stick to a cutting tool to affect the normal operation process of cutting.
The anode layer 120 is made of Ag/ITO/Ag, and in the process of forming the anode layer 120, an anode material layer is formed on the planarization layer 110 and the cutting reserved area a, and then the anode material layer is etched to form the anode layer 120 on the display area. In the process of etching the anode material layer, the anode material layer formed on the cutting reserved area a cannot be completely removed, and an anode residual material c may be formed at an edge of the planarization layer 110 facing the cutting reserved area a. Since the bonding wires 130 extend from the bonding regions to the cutting margin a along the top surface of the planarization layer 110, and the anode residual material c is formed at the edge of the planarization layer 110 facing the cutting margin a, the adjacent bonding wires 130 are connected together by the anode residual material c to generate short circuits, thereby generating dark lines in the display region.
On this basis, an embodiment of the present invention provides an array substrate, please refer to fig. 3 and 4, including:
a substrate base plate 200, the substrate base plate 200 including a display region C and an edge region D surrounding the display region C, the edge region D including a cutting reserved region D1 and a binding region D2, the binding region D2 being located between the display region C and the cutting reserved region D1;
a planarization layer 210 on the display region C and the edge region D, and the planarization layer 210 exposes the cutting reservation region D1 and the binding region D2;
an electrode spacer 220 on a portion of the cutting margin d1 and in contact with the planarization layer 210;
an electrode layer 230 located on the display region C and located on a surface of the planarization layer 210 facing away from the substrate 200;
a plurality of bonding wires 240 electrically connected to the bonding regions d2, the bonding wires 240 extending from the bonding regions d2 along the top surface of the planarization layer 210 onto the cutting preserved regions d1, the electrode spacers 220 being on the cutting preserved regions d1 between adjacent bonding wires 240.
The base substrate 200 is a transparent substrate. The display region C of the substrate 200 includes a plurality of pixel units arranged in an array, and each pixel unit includes a driving transistor. The driving transistor includes a source region 251 and a drain region 252, an active layer 253, a gate electrode 254, and a gate dielectric layer 255. The driving transistor is of a top gate structure or a bottom gate structure, and fig. 4 illustrates the driving transistor as the top gate structure.
The substrate base plate 200 is further provided with an interlayer dielectric layer 270, the display region C and the edge region D are both provided with the interlayer dielectric layer 270, in the display region C, the interlayer dielectric layer 270 is located on the driving transistor, and in the edge region D, the interlayer dielectric layer 270 is located on the gate dielectric layer 255.
The interlayer dielectric layer 270 has a first via hole therein, which is located on the drain region 252 and the source region 251, and also extends into the gate dielectric layer 255. The display area C has a source/drain layer 290 thereon in the first via hole.
The bonding region d2 has a pad layer 280 thereon, and the pad layer 280 is located between the interlayer dielectric layer 270 and the gate dielectric layer 255. The material of the pad layer 280 includes Mo.
The interlayer dielectric layer 270 further has a second via hole therein, which is located on the pad layer 280.
The bonding region d2 is provided with a plurality of conductive connection lines 260, specifically, the conductive connection lines 260 are located on the interlayer dielectric layer 270 and in the second via holes, and the conductive connection lines 260 are connected to the pad layer 280 through the second via holes.
The source/drain layers 290 and the conductive connection line 260 may be disposed in the same layer.
The edge region D is further provided with a plurality of anti-static connection lines 291, the plurality of anti-static connection lines 291 extend from the edge region D between the cutting reserved region D1 and the binding region D2 to the cutting reserved region D1, the anti-static connection lines 291 are located at the bottom of the interlayer dielectric layer 270, and the anti-static connection lines 291 may also be located at the bottom of the gate dielectric layer 255 and covered by the gate dielectric layer 255.
The interlayer dielectric layer 270 further has a third via hole located between the cutting reserved region d1 and the binding region d2 and located on the anti-static connection line 291, the third via hole may further extend into the gate dielectric layer 255, and the conductive connection line 260 may further extend into the third via hole and be connected to the anti-static connection line 291.
The planarization layer 210 is located on the substrate base plate 200, specifically, the planarization layer 210 is located on the interlayer dielectric layer 270 and the conductive connection line 260, the planarization layer 210 has a fourth via therein, the fourth via is located on the source/drain layer 290, specifically, in this embodiment, the fourth via is located on the drain layer; the planarization layer 210 exposes the cutting reserved region d1 and the bonding region d2, the planarization layer 210 has several slots separated from each other, the slots expose the conductive connection line 260 on the bonding region d2 and a portion of the interlayer dielectric layer 270 at the side of the conductive connection line 260, respectively, and the planarization layer 210 exposes the interlayer dielectric layer 270 on the cutting reserved region d 1.
The bonding wires 240 are electrically connected to the conductive connection wires 260 through the slots, respectively.
In this embodiment, the conductive connection line 260 has a Ti/Al/Ti structure. The conductive connection line 260 includes a first conductive film, a third conductive film, and a second conductive film between the first conductive film and the third conductive film, the first conductive film and the third conductive film include Ti, and the second conductive film includes Al. The first conductive film, the second conductive film, and the third conductive film are stacked from a direction perpendicular to the surface of the base substrate 200.
The cutting reserved area d1 is an area reserved for cutting the substrate 200 and located near the cutting track, and the planarization layer 210 does not cover the cutting reserved area d1, so that the planarization layer 210 itself is not affected by cutting during the cutting process of the substrate 200, specifically, the cutting process does not contact the planarization layer 210 to avoid tearing the film layer of the planarization layer 210, on the other hand, the planarization layer 210 does not affect the cutting process, and specifically, the material of the planarization layer 210 does not stick to the cutting tool to affect the normal operation process of cutting.
The electrode spacer 220 is used for preventing the electrode layer from being remained on the cutting reserved area by using an electrode material film in the preparation process, the electrode material film cannot be remained on the edge of the planarization layer facing the cutting reserved area, and even if the binding connection line extends to the cutting reserved area, the adjacent binding connection lines cannot be shorted together, so that a dark line in the display area is avoided.
The electrode layer 230 is an anode layer, and the electrode layer 230 is connected to the source/drain layer 290 through the fourth via hole, specifically, in this embodiment, the electrode layer 230 is connected to the drain layer through the fourth via hole. In this embodiment, the structure of the electrode layer 230 includes an ITO/Ag/ITO structure. That is, the electrode layer 230 includes a first electrode film, a third electrode film, and a second electrode film located between the first electrode film and the third electrode film, a material of the first electrode film and the third electrode film includes ITO, and a material of the second electrode film includes Ag. The first electrode film, the second electrode film, and the third electrode film are stacked from a direction perpendicular to the surface of the base substrate 200.
The electrode spacer 220 comprises a first main material layer and the electrode layer 230 comprises a second main material layer having a material reducibility stronger than that of the first main material layer. The electrode spacer 220 is suitable for participating in electrochemical regulation in the process of forming the electrode layer 230, and even if the electrode residue material is formed on the cutting reserved area d1 at the initial moment in the process of forming the electrode layer 230, the second main material layer in the electrode residue material can be used as a negative electrode of an electrochemical reaction, and the first main material layer in the electrode spacer 220 can be used as a positive electrode of the electrochemical reaction, so that the electrode residue material loses electrons and is reduced, and finally the electrode residue material is removed in the process of the electrochemical reaction, so that the electrode layer material is not left on the cutting reserved area d1, and the adjacent binding connecting lines 240 are not short-connected together, thereby avoiding a dark line in a display area.
In a specific embodiment, the material of the first main material layer is Ti, and the material of the second main material layer is ITO.
In this embodiment, the electrode spacer 220 and the conductive connection line 260 are disposed in the same layer. This allows the electrode spacer 220 to be formed using a process of forming the conductive connection line 260 without an additional process of forming the electrode spacer 220.
In this embodiment, the electrode spacer 220 has the same structure as the conductive connection line 260. The electrode spacer 220 is of a Ti/Al/Ti structure. The electrode spacer 220 includes a first spacer film, a third spacer film, and a second spacer film between the first spacer film and the third spacer film. The first and third spacers and the material include Ti, and the material of the second spacer includes Al. The first spacer film, the second spacer film, and the third spacer film are stacked from a direction perpendicular to the surface of the base substrate 200.
In this embodiment, the electrode spacer 220 and the conductive connection line 260 are separated from each other, and the electrode spacer 220 is located between the adjacent bonding connection lines 240. The electrode spacer 220 and the bonding wire 240 are separated from each other without the position of the bonding wire 240 being shifted.
In a specific embodiment, the distances from the electrode spacer 220 to the adjacent bonding connection lines 240 are equal. This makes the distance from the electrode spacer 220 to the bonding wire 240 on either side relatively large, and makes it difficult to short-circuit the electrode spacer 220 and the bonding wire 240 even if some conductive foreign matter exists between the electrode spacer 220 and the bonding wire 240.
In other embodiments, the distance between the electrode spacers to adjacent ones of the bonding wires is unequal.
If the width of the electrode spacer 220 is too small, the requirement for exposure accuracy is high, the process difficulty is high, and the cost is high; if the width of the electrode spacer 220 is too large, the risk of the electrode spacer 220 itself connecting with the adjacent bonding connection line 240 increases. Thus, in one embodiment, the electrode spacers 220 have a width of 1/6-1/5, such as 1/6, 2/11, 1/5, between adjacent bond wires 240.
In a specific embodiment, the pitch between adjacent bonding wires 240 is 10 microns to 12 microns, and the width of the electrode spacer 220 is 1.5 microns to 2.5 microns, such as 1.5 microns, 1.8 microns, 2.0 microns, 2.3 microns, or 2.5 microns.
The width of the electrode spacer 220 refers to a size of the electrode spacer along the arrangement direction of the binding connection line 240.
The spacing between adjacent bonding connection lines 240 refers to: a minimum spacing between edges of adjacent bonding wires 240.
In this embodiment, a partial region of the electrode spacer 220 extends to the edge region D between the cutting margin D1 and the bonding region D2 and is covered by the planarization layer 210. This allows the electrode spacer 220 to reduce the positional accuracy requirements for forming the electrode spacer 220 while ensuring contact with the planarization layer 210.
In other embodiments, the electrode spacers are aligned with edges of the planarization layer toward the cutting reserve d 1.
It should be noted that the electrode spacer 220 needs to be in contact with the planarization layer 210 toward the edge of the cutting margin d1, so that the electrode spacer 220 participates in the electrochemical reaction and prevents the material of the electrode layer 230 from remaining on the cutting margin d 1.
It should be noted that Q represents a cleavage line.
After the array substrate is manufactured, the array substrate is cut along the cutting lines, and after the cutting, the plurality of anti-static connection lines 291 are disconnected.
Referring to fig. 5, the array substrate of the present embodiment is different from the array substrate of the previous embodiment in that: the electrode spacer 220 ' is connected to the conductive connection line 260 in an extending direction of the conductive connection line 260, a partial region of the electrode spacer 220 ' is covered by the bonding connection line 240, and a width of the electrode spacer 220 ' is greater than a width of the conductive connection line 260 and greater than a width of the bonding connection line 240.
The electrode spacer 220' is disposed at the same layer as the conductive connection line 260. The electrode spacer 220' has the same structure as the conductive connection line 260; the electrode spacer 220' may be of a Ti/Al/Ti structure.
Since the width of the electrode spacer 220 'is greater than the width of the conductive connection line 260, the process difficulty of forming the electrode spacer 220' is reduced.
If the ratio of the difference 1/2 between the widths of the electrode spacer 220 'and the bonding wire 240 to the pitch between the adjacent bonding wires 240 is too small, the electrode spacer 220' cannot be exposed on both sides of the bonding wire 240 in the width direction if the bonding wire 240 is displaced; if the ratio of the difference 1/2 between the widths of the electrode spacer 220 'and the bonding wire 240 to occupy the space between the adjacent bonding wires 240 is too large, the adjacent bonding wires 240 are at risk of being shorted by the electrode spacer 220'. In summary, in one embodiment, the width difference 1/2 between the electrode spacer 220' and the bonding wires 240 occupies 1/6-1/5, such as 1/6, 2/11, 1/5, of the spacing between adjacent bonding wires 240.
In a specific embodiment, the difference between the widths of the electrode spacer 220' and the bonding wires 240 is 8 to 10 micrometers, and the distance between the adjacent bonding wires 240 is 15 to 25 micrometers.
The same contents in this embodiment as in the previous embodiment are not described in detail.
Accordingly, another embodiment of the present invention further provides a method for manufacturing an array substrate, referring to fig. 5, including the following steps:
s01: providing a substrate base plate 200, wherein the substrate base plate 200 comprises a display region C and an edge region D surrounding the display region C, the edge region D comprises a cutting reserved region D1 and a binding region D2, and the binding region D2 is located between the display region C and the cutting reserved region D1;
s02: forming an electrode spacer 220/220' on a portion of the cut reserve d 1;
s03: forming a planarization layer 210 on the display region C and the edge region D, and the planarization layer 210 exposing the cutting margin region D1 and the binding region D2, the electrode spacer 220/220' being in contact with the planarization layer 210;
s04: forming an electrode layer 230 on the display region C, wherein the electrode layer 230 is located on the surface of the planarization layer 210 on the side away from the substrate 200;
s05: a plurality of bonding wires 240 electrically connected to the bonding region d2 are formed on the bonding region d2, the bonding wires 240 extend from the bonding region d2 along the top surface of the planarization layer 210 to the cutting reservation region d1, and the electrode spacers 220/220' are formed on the cutting reservation regions d1 between the adjacent bonding wires 240.
In the method for manufacturing the array substrate, before the planarization layer 210 is formed, the bonding region d2 is provided with a plurality of conductive connection lines 260; forming the electrode spacers 220/220' during the process of forming the conductive connection lines 260; after the planarization layer 210 is formed, the planarization layer 210 exposes the conductive connection line 260; after the bonding wires 240 are formed, the bonding wires 240 are electrically connected to the conductive connection wires 260, respectively.
In this embodiment, the preparation method for forming the electrode layer 230 includes: forming a film of electrode material (not shown) on the planarization layer 210, the cutting margin d1 and the binding region d 2; the electrode material film is etched to remove the electrode material film on the cutting reserved region d1 and the binding region d2, and a portion of the electrode material film on the planarization layer 210, thereby forming the electrode layer 230.
In this embodiment, the method for etching the electrode material film adopts a wet etching process. In a specific embodiment, the etching solution used in the wet etching process includes HNO3、CH3COOH、H3PO4 and a chelating agent. In the course of performing the wet etching process, the second main material layer of the electrode material film located on the cutting margin d1 near the edge of the planarization layer 210, the first main material layer of the electrode spacer 220, and the etching solution are electrochemically reacted, and the second main material layer serves as electricityThe chemically reacted negative electrode, the first main material layer in electrode spacer 220/220', acts as the positive electrode for the electrochemical reaction, causing the loss of electrons from the electrode material film located on cut reserve d1 near the edge of planarization layer 210 to be reduced, eventually avoiding the formation of electrode residue material from planarization layer 210 toward the edge of cut reserve d 1. Specifically, when the material of the first main material layer is Ti and the material of the second main material layer is ITO, in the electrochemical reaction, ITO in the electrode material film serves as a negative electrode of the electrochemical reaction, and Ti in the electrode separator 220/220' serves as a positive electrode of the electrochemical reaction.
In one embodiment, the electrode spacer 220 and the conductive connection line 260 are separated from each other, and the electrode spacer 220 is located between the adjacent bonding connection lines 240.
In another embodiment, the electrode spacer 220 ' is connected to the conductive connection line 260 in an extending direction of the conductive connection line 260, a partial region of the electrode spacer 220 ' is covered by the bonding connection line 240, and a width of the electrode spacer 220 ' is greater than a width of the conductive connection line 260 and greater than a width of the bonding connection line 240.
In one particular embodiment, the electrode spacers 220/220' may be formed using a separate process. Specifically, a method of forming the electrode spacer 220/220' includes: depositing a layer of electrode spacing material on the planarization layer 210, and on the cutting reservation region d1 and the bonding region d 2; the electrode spacer material layer is etched to form the electrode spacers 220/220'.
In another embodiment, the electrode spacers 220/220 'are formed in the same process as the conductive link 260, i.e., the electrode spacers 220/220' are formed during the formation of the conductive link layer 260. This simplifies the process steps.
In the method for manufacturing an array substrate provided in this embodiment, since the electrode spacer in contact with the planarization layer is disposed on a portion of the cut-reserved area, the electrode spacer is used to prevent an electrode material film used in a manufacturing process of the electrode layer from remaining on the cut-reserved area, and the electrode material film does not remain on an edge of the planarization layer facing the cut-reserved area, so that even if the bonding connection line extends to the cut-reserved area, adjacent bonding connection lines are not shorted together, thereby avoiding a dark line in the display area.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. An array substrate, comprising:
the substrate comprises a display area and an edge area surrounding the display area, wherein the edge area comprises a cutting reserved area and a binding area, and the binding area is positioned between the display area and the cutting reserved area;
a planarization layer on the display region and the edge region, and exposing the cutting reserved region and the binding region;
an electrode spacer on a portion of the cutting reserve and in contact with the planarization layer;
the electrode layer is positioned on the display area and positioned on the surface of one side, away from the substrate, of the planarization layer;
the bonding connecting lines extend from the bonding regions to the cutting reserved regions along the top surfaces of the planarization layers, and the electrode spacers are arranged on the cutting reserved regions between the adjacent bonding connecting lines.
2. The array substrate of claim 1, wherein the electrode spacer comprises a first host material layer; the electrode layer comprises a second main material layer, and the material reducibility of the second main material layer is stronger than that of the first main material layer;
preferably, the material of the first main material layer includes Ti, and the material of the second main material layer includes ITO.
3. The array substrate of claim 1 or 2, wherein the bonding region is provided with a plurality of conductive connection lines; the planarization layer exposes the conductive connection line; the binding connecting lines are electrically connected with the conductive connecting lines respectively;
the electrode spacer and the conductive connecting line are arranged in the same layer.
4. The array substrate of claim 3, wherein the electrode spacer has the same structure as the conductive connection line;
preferably, the electrode spacer comprises a Ti/Al/Ti structure.
5. The array substrate of claim 3, wherein the electrode spacers and the conductive connection lines are discrete from each other, and the electrode spacers are located between the adjacent bonding connection lines;
preferably, the distance between the electrode spacer and the adjacent binding connection line is equal;
preferably, the electrode spacers have a width occupying 1/6-1/5 of a space between adjacent bonding wires.
6. The array substrate according to claim 3, wherein the electrode spacers are connected to the conductive connection lines in an extending direction of the conductive connection lines, a partial region of the electrode spacers is covered by the bonding connection lines, and a width of the electrode spacers is larger than a width of the conductive connection lines and larger than a width of the bonding connection lines;
preferably, the electrode spacer and the width difference 1/2 of the bonding wires occupy 1/6 ~ 1/5 of the spacing between adjacent bonding wires.
7. The array substrate of claim 1 or 2, wherein a partial region of the electrode spacer extends onto an edge region between the cutting reservation region and the binding region and is covered by the planarization layer.
8. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate base plate, wherein the substrate base plate comprises a display area and an edge area surrounding the display area, the edge area comprises a cutting reserved area and a binding area, and the binding area is positioned between the display area and the cutting reserved area;
forming an electrode spacer on a portion of the cutting margin;
forming a planarization layer on the display region and the edge region, and the planarization layer exposes the cutting margin region and the binding region, the electrode spacer being in contact with the planarization layer;
forming an electrode layer on the display area, wherein the electrode layer is positioned on the surface of the planarization layer on the side away from the substrate base plate;
and forming a plurality of binding connection lines electrically connected with the binding regions on the binding regions, wherein the binding connection lines extend from the binding regions along the top surface of the planarization layer to the cutting reserved regions, and the electrode spacers are arranged on the cutting reserved regions between the adjacent binding connection lines.
9. The method for manufacturing the array substrate according to claim 8, wherein before the planarization layer is formed, the bonding region is provided with a plurality of conductive connection lines; forming the electrode spacer in a process of forming the conductive connection line; after forming the planarization layer, the planarization layer exposes the conductive connection line; the binding connecting lines are electrically connected with the conductive connecting lines respectively;
preferably, the electrode spacer includes a first main material layer, the electrode layer includes a second main material layer having a material reducibility stronger than that of the first main material layer; the preparation method for forming the electrode layer comprises the following steps: forming an electrode material film on the planarization layer, the cutting reservation region and the binding region; etching the electrode material film by adopting a wet etching process to remove the electrode material film on the cutting reserved area and the binding area and part of the electrode material film on the planarization layer to form the electrode layer; in the process of carrying out the wet etching process, carrying out electrochemical reaction on a second main material layer in the electrode material film, a first main material layer in the electrode spacer and an etching solution, wherein the second main material layer is positioned on the cutting reserved area and close to the edge of the planarization layer, the second main material layer is used as a negative electrode of the electrochemical reaction, and the first main material layer in the electrode spacer is used as a positive electrode of the electrochemical reaction; preferably, the electrode spacers and the conductive connecting lines are discrete from each other, and the electrode spacers are located between the adjacent binding connecting lines;
preferably, the electrode spacer is connected to the conductive connection line in an extending direction of the conductive connection line, a partial region of the electrode spacer is covered by the bonding connection line, and a width of the electrode spacer is greater than a width of the conductive connection line and greater than a width of the bonding connection line.
10. A display device comprising the array substrate according to any one of claims 1 to 7.
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| CN113013356A (en) * | 2021-02-22 | 2021-06-22 | 京东方科技集团股份有限公司 | Display device, display panel and manufacturing method thereof |
| CN114460773A (en) * | 2022-01-27 | 2022-05-10 | 武汉华星光电技术有限公司 | Display panel to be cut, display panel and display device |
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| CN108878500A (en) * | 2018-07-13 | 2018-11-23 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
| CN109659304A (en) * | 2017-10-12 | 2019-04-19 | 上海和辉光电有限公司 | A kind of array substrate, display panel and display device |
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| CN109659304A (en) * | 2017-10-12 | 2019-04-19 | 上海和辉光电有限公司 | A kind of array substrate, display panel and display device |
| CN108878500A (en) * | 2018-07-13 | 2018-11-23 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113013356A (en) * | 2021-02-22 | 2021-06-22 | 京东方科技集团股份有限公司 | Display device, display panel and manufacturing method thereof |
| CN113013356B (en) * | 2021-02-22 | 2023-02-03 | 京东方科技集团股份有限公司 | Display device, display panel and manufacturing method thereof |
| CN114460773A (en) * | 2022-01-27 | 2022-05-10 | 武汉华星光电技术有限公司 | Display panel to be cut, display panel and display device |
| CN114460773B (en) * | 2022-01-27 | 2023-09-26 | 武汉华星光电技术有限公司 | Display panel to be cut, display panel and display device |
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