CN108878500A - Display base plate and preparation method thereof, display device - Google Patents
Display base plate and preparation method thereof, display device Download PDFInfo
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- CN108878500A CN108878500A CN201810770563.7A CN201810770563A CN108878500A CN 108878500 A CN108878500 A CN 108878500A CN 201810770563 A CN201810770563 A CN 201810770563A CN 108878500 A CN108878500 A CN 108878500A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 239000010409 thin film Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 85
- 239000011229 interlayer Substances 0.000 description 5
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of display base plate and preparation method thereof, display device, belongs to field of display technology.Display base plate of the invention, including viewing area and binding area；The display base plate includes：Substrate is located at the viewing area, and thin film transistor (TFT) on the substrate is arranged；Positioned at the binding area, and signal wire on the substrate is set；And the thin film transistor (TFT) and the signal wire are set away from the planarization layer of the substrate side；Wherein, the planarization layer includes first part and second part；The first part of the planarization layer is located at the viewing area, and the second part is located at the binding area, and the second part covers the signal wire；Wherein, the thickness of the first part is greater than the thickness of the second part.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display substrate and a preparation method thereof.
Background
An Organic Light Emitting Diode (OLED) display panel gradually becomes the mainstream of the display field by virtue of its excellent properties such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility, and can be widely applied to terminal products such as smart phones, tablet computers, televisions, and the like.
In an OLED display panel, a main portion of the OLED display panel is an OLED substrate, and in an existing manufacturing process of the OLED substrate, a driving element such as a thin film transistor is generally formed on a substrate at a position corresponding to a display area, a signal line and other structures are formed in a bonding area, and then a planarization layer is formed on the substrate on which the driving element such as the thin film transistor and the signal line and other structures are formed, and the planarization layer only covers the display area, and is generally thick (1.5-3.5 um), so that a step difference of the planarization layer is formed in the display area and the bonding area. The step difference may cause the photoresist thickness to be non-uniform during the photolithography process for forming the display electrode (i.e., the anode of the OLED device) in the next step. If the exposure energy is too small to meet the requirement of the display area, the photoresist at the level difference of the planarization layer of the binding area is remained, so that the display electrode layer is remained near the level difference of the planarization layer and short circuits a lower signal line, and poor display is caused; if the exposure is too large to ensure that no display electrode material remains at the planarization layer level difference of the binding region, the display region will have poor line breaking.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a display substrate, a method for manufacturing the same, and a display device.
The technical scheme adopted for solving the technical problem of the invention is that the display substrate comprises a display area and a binding area; the display substrate includes: the substrate is positioned in the display area and is provided with a thin film transistor on the substrate; the signal line is positioned in the binding region and arranged on the substrate; and a planarization layer disposed on a side of the thin film transistor and the signal line away from the substrate; wherein,
the planarization layer includes a first portion and a second portion; the first part of the planarization layer is positioned in the display area, the second part of the planarization layer is positioned in the binding area, and the second part of the planarization layer covers the signal line; wherein the thickness of the first portion is greater than the thickness of the second portion.
Preferably, the source and the drain of the thin film transistor are arranged in the same layer and made of the same material as the signal line.
It is further preferable that a via hole is provided at a position of the first portion of the planarization layer corresponding to the drain electrode of the thin film transistor; a display electrode is arranged on one side, away from the substrate, of the first part of the planarization layer; the display electrode is connected with the drain electrode through the through hole.
It is further preferable that the display substrate further includes a pixel defining layer located in the display region and disposed on a side of the display electrode facing away from the substrate, and a spacer disposed on a side of the pixel defining layer facing away from the substrate.
The technical scheme adopted for solving the technical problem of the invention is a preparation method of a display substrate, wherein the display substrate comprises a display area and a binding area; the preparation method comprises the following steps:
forming each layer structure of the thin film transistor positioned in the display area and a signal wire positioned in the binding area on the substrate;
forming a first part and a second part of a planarization layer on the side, away from the substrate, of the thin film transistor and the signal line through a patterning process; wherein a first portion of the planarization layer is located in the display region, a second portion of the planarization layer is located in the binding region, and the second portion covers the signal line; the first portion has a thickness greater than a thickness of the second portion.
Preferably, the step of forming the first and second portions of the planarization layer on the side of the thin film transistor and the signal line away from the substrate by the patterning process includes:
a planarization material layer is formed on one side, away from the substrate, of the thin film transistor and the signal line;
and exposing the planarization material layer by using mask plates with different precisions to form a first part and a second part of the planarization layer.
Preferably, the source electrode and the drain electrode of the thin film transistor and the signal line are prepared by adopting a one-step composition process.
Preferably, a via hole is formed in the first portion of the planarization layer at a position corresponding to the drain electrode of the thin film transistor; the preparation method further comprises the following steps:
forming a display electrode on a side of the first portion of the planarization layer facing away from the substrate; the display electrode is connected with the drain electrode through the through hole.
Further preferably, the preparation method further comprises:
and forming a pixel limiting layer on the side of the display electrode, which faces away from the substrate, and forming a spacer on the side of the pixel limiting layer, which faces away from the substrate.
The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the display substrate.
The invention has the following beneficial effects:
in the display substrate, the second part structure of the planarization layer covers the signal wires in the binding region, namely, the insulating material covers the signal wires, so that when the display electrodes are formed on the planarization layer, even if the material of the display electrodes is remained above the signal wires due to the segment difference between the first part and the second part, the second part of the planarization layer can insulate and separate the signal wires from the display electrode material, the problem that the display electrode material short-circuits the signal wires is effectively solved, and the yield of the display substrate is improved.
Drawings
Fig. 1 is a schematic structural diagram of a display substrate according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a display substrate according to embodiment 1 of the present invention;
fig. 3 is a flowchart of a method for manufacturing a display substrate according to embodiment 2 of the present invention;
fig. 4 is a process flow chart of a method for manufacturing a display substrate according to embodiment 2 of the present invention.
Wherein the reference numerals are: 1. a substrate; 2. a thin film transistor; 21. an active layer; 22. a gate electrode; 23. a source electrode; 24. a drain electrode; 3. a gate insulating layer; 4. an interlayer insulating layer; 5. a signal line; 6. a planarization layer; 61. a first portion; 62. a second portion; 63. a via hole; 7. a display electrode; 8. a pixel defining layer; 81. an accommodating portion; 9. a spacer; q1, display area; q2, binding.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
as shown in fig. 1, the present embodiment provides a display substrate having a display region Q1 and a bonding region Q2, and the display substrate specifically includes: a substrate 1, a thin film transistor 2 disposed on the substrate 1, and located in the display region Q1; a signal line 5 located in the bonding region Q2 and disposed on the substrate 1; and a planarization layer 6 disposed on a side of the thin film transistor 2 and the signal line 5 facing away from the substrate 1; wherein the planarization layer 6 comprises a first portion 61 and a second portion 62; the first portion 61 of the planarization layer 6 is located at the display region Q1, the second portion 62 is located at the binding region Q2, and the second portion 62 covers the signal line 5; wherein the thickness of the first portion 61 is greater than the thickness of the second portion 62 (at this time, there is a step difference between the first portion 61 and the second portion 62).
In the display substrate of the embodiment, since the second portion 62 of the planarization layer 6 covers the signal line 5 in the bonding region Q2, that is, the signal line 5 covers the insulating material, when the display electrode 7 is formed on the planarization layer 6, even if the material of the display electrode 7 remains above the signal line 5 due to the step difference between the first portion 61 and the second portion 62, the second portion 62 of the planarization layer 6 can insulate and separate the signal line 5 from the material of the display electrode 7, thereby effectively solving the problem that the material of the display electrode 7 short-circuits the signal line 5, and improving the yield of the display substrate.
It should be noted that the first portion 61 of the planarization layer 6 is thicker than the second portion 62 in this embodiment because the second portion 62 is located in the bonding region Q2, and the signal line 5 connecting pad needs to be bonded with the pad on the chip later.
In the display substrate of this embodiment, the thin film transistor 2 may be a top gate thin film transistor 2, or a bottom gate thin film transistor 2; taking the bottom gate type thin film transistor 2 as an example in the present embodiment, the thin film transistor 2 specifically includes an active layer 21, a gate insulating layer 3, a gate electrode 22, an interlayer insulating layer 4, a source electrode 23, and a drain electrode 24, which are sequentially disposed on the substrate 1; the source and drain electrodes 23 and 24 are connected to the active layer 21 through source and drain contact vias, respectively, which penetrate the gate insulating layer 3 and the interlayer insulating layer 4. Specifically, in the present embodiment, the signal line 5 is disposed in the same layer as the source electrode 23 and the drain electrode 24, and the material is the same. Thus, the signal line 5, the source electrode 23, and the drain electrode 24 can be manufactured in one process.
The display substrate of the present embodiment may be an OLED substrate, or an array substrate for a liquid crystal panel. In this embodiment, the display substrate is an OLED substrate. The display substrate in this embodiment includes not only the above structure, but also, as shown in fig. 2, a via hole 63 is provided at a position corresponding to the drain 24 of the thin film transistor 2 in the first portion 61 of the planarization layer 6; a display electrode 7 (i.e. the anode of the OLED device) is also provided on the side of the first portion 61 of the planarisation layer 6 facing away from the substrate 1; the display electrode 7 is connected to the drain electrode 24 through the via hole 63; of course, there is a possibility that there will be residual display electrode 7 material above the second portion 62 of the planarization layer 6 due to the different thicknesses of the first portion 61 and the second portion 62 of the planarization layer 6. The OLED substrate further comprises a pixel limiting layer 8 which is positioned in the display area Q1 and is arranged on the side, facing away from the substrate 1, of the display electrode 7, and a spacer 9 which is arranged on the side, facing away from the substrate 1, of the pixel limiting layer 8. Note that, for the pixel defining layer 8, the display electrode 7 is exposed at the position of the accommodating portion 81 of the pixel defining layer 8, and the light emitting layer and the cathode of the OLED device are also provided in the accommodating portion 81.
Example 2:
with reference to fig. 3 and 4, this embodiment provides a method for manufacturing a display substrate, where the method for manufacturing a display substrate in embodiment 1 can include the following steps:
step one, the layer structure of the thin film transistor 2 in the display region Q1 and the signal line 5 in the bonding region Q2 are formed on the substrate 1.
The thin film transistor 2 can be a top gate thin film transistor 2, or a bottom gate thin film transistor 2; in the present embodiment, the first step is specifically described by taking the bottom gate thin film transistor 2, the signal line 5 and the source 23 and the drain 24 of the thin film transistor 2 as the same layer as each other as an example.
Firstly, forming a semiconductor material layer on a substrate 1, and forming a pattern of an active layer 21 of a thin film transistor 2 through a composition process after dehydrogenation and excimer laser annealing; then, sequentially forming a gate insulating layer 3 and a gate 22 above the active layer 21, then performing ion implantation on a source contact region and a drain contact region of the active layer 21, depositing an interlayer insulating layer 4, and finally forming a source 23, a drain 24 and a signal line 5 through a one-time composition process; the source and drain electrodes 23 and 24 are connected to the active layer 21 through source and drain contact vias, respectively, which penetrate the gate insulating layer 3 and the interlayer insulating layer 4.
Step two, forming a first part 61 and a second part 62 of the planarization layer 6 on one side of the thin film transistor 2 and the signal line 5, which is far away from the substrate 1, through a patterning process, and arranging a through hole 63 at a position of the first part 61, which corresponds to the drain electrode 24 of the thin film transistor 2; wherein the first portion 61 of the planarization layer 6 is located in the display region Q1, the second portion 62 is located in the binding region Q2, and the second portion 62 covers the signal line 5; the thickness of the first portion 61 is greater than the thickness of the second portion 62.
The step may specifically include: firstly, a planarization material layer is formed on the side, away from the substrate 1, of the thin film transistor 2 and the signal line 5; the planarization material layer is then exposed using different precision reticles to form a first portion 61 and a second portion 62 of the planarization layer 6, and a via 63 is provided in the first portion 61 at a location corresponding to the drain 24 of the tft 2. The masks with different precisions include but are not limited to gray-scale masks and half-exposure masks.
Step three, forming a display electrode 7 on one side of the first part 61 of the planarization layer 6, which is far away from the substrate 1; the display electrode 7 is connected to the drain electrode 24 of the thin film transistor 2 through the via 63. The display electrode 7 may be the anode of an OLED device.
And step four, forming a pixel limiting layer 8 on the side, away from the substrate 1, of the display electrode 7, and forming a spacer 9 on the side, away from the substrate 1, of the pixel limiting layer 8.
Note that, for the pixel defining layer 8, the display electrode 7 is exposed at the position of the accommodating portion 81 of the pixel defining layer 8, and the light emitting layer and the cathode of the OLED device are also provided in the accommodating portion 81.
Here, the display substrate in the present embodiment may also be an array substrate for a liquid crystal panel, in which the display electrode 7 is a pixel electrode.
In the manufacturing method of the display substrate of the embodiment, since the second portion 62 of the planarization layer 6 covers the signal line 5 in the bonding region Q2, that is, the signal line 5 covers the insulating material, when the display electrode 7 is formed on the planarization layer 6, even if the material of the display electrode 7 remains above the signal line 5 due to the step difference between the first portion 61 and the second portion 62, the second portion 62 of the planarization layer 6 can insulate and separate the signal line 5 from the material of the display electrode 7, thereby effectively solving the problem that the material of the display electrode 7 short-circuits the signal line 5, and improving the yield of the display substrate.
Example 3:
the present embodiment provides a display device including the display substrate provided in embodiment 1.
Since the display device in this embodiment includes the display substrate in embodiment 1, the yield is higher.
The display device may be an OLED display device or a liquid crystal display device, such as any product or component with a display function, such as electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A display substrate includes a display area and a binding area; characterized in that, the display substrate includes: the substrate is positioned in the display area and is provided with a thin film transistor on the substrate; the signal line is positioned in the binding region and arranged on the substrate; and a planarization layer disposed on a side of the thin film transistor and the signal line away from the substrate; wherein,
the planarization layer includes a first portion and a second portion; the first part of the planarization layer is positioned in the display area, the second part of the planarization layer is positioned in the binding area, and the second part of the planarization layer covers the signal line; wherein the thickness of the first portion is greater than the thickness of the second portion.
2. The display substrate according to claim 1, wherein the source and the drain of the thin film transistor are disposed on the same layer and have the same material as the signal line.
3. The display substrate according to claim 2, wherein a via hole is provided in a position of the first portion of the planarization layer corresponding to the drain electrode of the thin film transistor; a display electrode is arranged on one side, away from the substrate, of the first part of the planarization layer; the display electrode is connected with the drain electrode through the through hole.
4. The display substrate of claim 3, further comprising a pixel defining layer disposed in the display region and on a side of the display electrode facing away from the substrate, and a spacer disposed on a side of the pixel defining layer facing away from the substrate.
5. A preparation method of a display substrate comprises a display area and a binding area of the display substrate; the preparation method is characterized by comprising the following steps:
forming each layer structure of the thin film transistor positioned in the display area and a signal wire positioned in the binding area on the substrate;
forming a first part and a second part of a planarization layer on the side, away from the substrate, of the thin film transistor and the signal line through a patterning process; wherein a first portion of the planarization layer is located in the display region, a second portion of the planarization layer is located in the binding region, and the second portion covers the signal line; the first portion has a thickness greater than a thickness of the second portion.
6. The method according to claim 5, wherein the step of forming a first portion and a second portion of a planarization layer on the side of the thin film transistor and the signal line away from the base by a patterning process comprises:
a planarization material layer is formed on one side, away from the substrate, of the thin film transistor and the signal line;
and exposing the planarization material layer by using mask plates with different precisions to form a first part and a second part of the planarization layer.
7. The method for manufacturing a display substrate according to claim 5, wherein the source electrode and the drain electrode of the thin film transistor and the signal line are manufactured by a one-step patterning process.
8. The method for manufacturing a display substrate according to claim 5, wherein a via hole is formed in the first portion of the planarization layer at a position corresponding to the drain electrode of the thin film transistor; the preparation method further comprises the following steps:
forming a display electrode on a side of the first portion of the planarization layer facing away from the substrate; the display electrode is connected with the drain electrode through the through hole.
9. The method for manufacturing a display substrate according to claim 8, further comprising:
and forming a pixel limiting layer on the side of the display electrode, which faces away from the substrate, and forming a spacer on the side of the pixel limiting layer, which faces away from the substrate.
10. A display device comprising the display substrate according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810770563.7A CN108878500A (en) | 2018-07-13 | 2018-07-13 | Display base plate and preparation method thereof, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810770563.7A CN108878500A (en) | 2018-07-13 | 2018-07-13 | Display base plate and preparation method thereof, display device |
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| CN108878500A true CN108878500A (en) | 2018-11-23 |
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| CN201810770563.7A Pending CN108878500A (en) | 2018-07-13 | 2018-07-13 | Display base plate and preparation method thereof, display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112289814A (en) * | 2020-10-29 | 2021-01-29 | 昆山国显光电有限公司 | Array substrate, preparation method thereof and display device |
| CN113516910A (en) * | 2020-04-09 | 2021-10-19 | 上海和辉光电有限公司 | Display panel and binding region planarization method thereof |
| CN113707674A (en) * | 2021-08-31 | 2021-11-26 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN114171567A (en) * | 2021-12-07 | 2022-03-11 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel and electronic equipment |
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| US20180039115A1 (en) * | 2016-01-05 | 2018-02-08 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Liquid Crystal Display Panel, Array Substrate And Manufacturing Method For The Same |
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| US20180039115A1 (en) * | 2016-01-05 | 2018-02-08 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Liquid Crystal Display Panel, Array Substrate And Manufacturing Method For The Same |
| CN107024813A (en) * | 2017-06-06 | 2017-08-08 | 厦门天马微电子有限公司 | Array base palte, liquid crystal display panel and display device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113516910A (en) * | 2020-04-09 | 2021-10-19 | 上海和辉光电有限公司 | Display panel and binding region planarization method thereof |
| CN112289814A (en) * | 2020-10-29 | 2021-01-29 | 昆山国显光电有限公司 | Array substrate, preparation method thereof and display device |
| CN112289814B (en) * | 2020-10-29 | 2022-09-13 | 昆山国显光电有限公司 | Array substrate, preparation method thereof and display device |
| CN113707674A (en) * | 2021-08-31 | 2021-11-26 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN113707674B (en) * | 2021-08-31 | 2024-05-07 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN114171567A (en) * | 2021-12-07 | 2022-03-11 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel and electronic equipment |
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