CN108231671B - Preparation method of thin film transistor and array substrate, array substrate and display device - Google Patents
Preparation method of thin film transistor and array substrate, array substrate and display device Download PDFInfo
- Publication number
- CN108231671B CN108231671B CN201810040432.3A CN201810040432A CN108231671B CN 108231671 B CN108231671 B CN 108231671B CN 201810040432 A CN201810040432 A CN 201810040432A CN 108231671 B CN108231671 B CN 108231671B
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- active layer
- semiconductor active
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 79
- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 252
- 239000004065 semiconductor Substances 0.000 claims abstract description 133
- 238000000034 method Methods 0.000 claims abstract description 109
- 230000008569 process Effects 0.000 claims abstract description 88
- 239000000203 mixture Substances 0.000 claims abstract description 22
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 230000000149 penetrating effect Effects 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 48
- 238000000059 patterning Methods 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 230000002093 peripheral effect Effects 0.000 claims description 26
- 229910044991 metal oxide Inorganic materials 0.000 claims description 25
- 150000004706 metal oxides Chemical class 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 230000014759 maintenance of location Effects 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 41
- 238000005530 etching Methods 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The disclosure provides a preparation method of a thin film transistor and an array substrate, the array substrate and a display device. The preparation method of the thin film transistor comprises the following steps: forming a first semiconductor active layer through a one-time composition process; forming a first insulating layer and forming a light shielding layer and a first grid electrode which are positioned in the effective display area through a one-time composition process; forming a second insulating layer and forming a via hole penetrating through the first insulating layer and the second insulating layer by a one-time composition process; forming a semiconductor reserved pattern which is contacted with the first semiconductor active layer through the through hole, a first source electrode and a first drain electrode which are positioned on the semiconductor reserved pattern, a second semiconductor active layer which is opposite to the shading layer, and a second source electrode and a second drain electrode which are contacted with the second semiconductor active layer through a one-time composition process; and forming a protective layer and a second grid electrode facing the second semiconductor active layer through a one-time composition process. The method can reduce the times of the composition process, improve the productivity and save the cost.
Description
Technical Field
The disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a method for manufacturing an array substrate, and a display device.
Background
Display devices have been developed to have high integration and low cost in recent years. By taking a Gate Driver on Array (GOA) technology as a representative, and integrating a Gate driving circuit in a peripheral area of an Array substrate by using the GOA technology, a narrow frame design can be realized, and at the same time, a module process yield can be effectively improved, a product yield can be improved, and a cost can be saved.
in order to ensure that a liquid Crystal Display (L i liquid Crystal Display, L CD) or an organic light Emitting Diode Display (O L TPS) can simultaneously realize a narrow frame and a low power consumption function, a low Temperature polysilicon (L ow Temperature polysilicon, L TPS) technology is generally used to prepare a thin film transistor in a GOA region, since the L TPS thin film transistor has a high mobility and a small size, the frame size can be effectively reduced, and since the L TPS thin film transistor can be driven at a low frequency, which can be as low as 1Hz, the power consumption can be effectively reduced.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a method for manufacturing a thin film transistor and an array substrate, and a display device, so as to solve the problems of too low productivity and too high cost caused by too many times of a patterning process of the array substrate.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to an aspect of the present disclosure, there is provided a method of manufacturing a thin film transistor, including:
Forming a first semiconductor active layer positioned in a peripheral circuit region above the substrate through a one-step composition process;
Forming a first insulating layer above the first semiconductor active layer, and forming a light shielding layer located in an effective display area and a first gate electrode facing the first semiconductor active layer above the first insulating layer through a one-time composition process;
Forming a second insulating layer above the light shielding layer and the first gate, and forming a first via hole and a second via hole penetrating through the first insulating layer and the second insulating layer by a one-time composition process, wherein the first via hole and the second via hole respectively expose two sides of the first semiconductor active layer;
Forming a disconnected second semiconductor reserved pattern which is respectively contacted with two sides of the first semiconductor active layer through the first via hole and the second via hole, a first source electrode and a first drain electrode which are respectively positioned on the second semiconductor reserved pattern, a second semiconductor active layer which is opposite to the light shielding layer, and a second source electrode and a second drain electrode which are respectively contacted with two sides of the second semiconductor active layer through a one-time composition process above the second insulating layer;
And forming a protective layer and a second grid electrode which is opposite to the second semiconductor active layer above the first source electrode, the first drain electrode, the second source electrode and the second drain electrode through a one-time composition process.
In one exemplary embodiment of the present disclosure, forming a first semiconductor active layer located in a peripheral circuit region over a substrate by a one-time patterning process includes:
And forming a polycrystalline silicon thin film on the substrate with the buffer layer by adopting a low-temperature polycrystalline silicon process, and forming a polycrystalline silicon active layer positioned in the peripheral circuit region by using the polycrystalline silicon thin film through a one-step composition process.
In an exemplary embodiment of the present disclosure, forming a light shielding layer located in an effective display region and a first gate electrode facing the first semiconductor active layer over the first insulating layer by a one-time patterning process includes:
And forming a first metal layer film above the first insulating layer, and forming a light shielding layer positioned in the effective display area and a first grid electrode opposite to the first semiconductor active layer on the first metal layer film through a one-time composition process.
In an exemplary embodiment of the present disclosure, forming, by a one-time composition process, a disconnected second semiconductor remaining pattern respectively in contact with both sides of the first semiconductor active layer through the first via hole and the second via hole, a first source electrode and a first drain electrode respectively on the second semiconductor remaining pattern, a second semiconductor active layer facing the light shielding layer, and a second source electrode and a second drain electrode respectively in contact with both sides of the second semiconductor active layer over the second insulating layer includes:
Sequentially forming a metal oxide semiconductor film and a second metal layer film above the second insulating layer;
And forming a disconnected metal oxide semiconductor retaining pattern which is respectively contacted with two sides of the first semiconductor active layer through the first via hole and the second via hole and a metal oxide semiconductor active layer which is opposite to the shading layer by using a half gray scale mask process, and forming a first source electrode and a first drain electrode which are respectively positioned on the metal oxide semiconductor retaining pattern and a second source electrode and a second drain electrode which are respectively contacted with two sides of the metal oxide semiconductor active layer by using the second metal layer film.
In an exemplary embodiment of the present disclosure, forming a protective layer and a second gate electrode facing the second semiconductor active layer over the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode by a one-time patterning process includes:
Sequentially forming a protective layer film and a third metal layer film above the first source electrode, the first drain electrode, the second source electrode and the second drain electrode;
And forming a region for disconnecting the effective display region and the peripheral circuit region in the protective layer film by adopting a half gray scale mask process to form the protective layer, and forming a second grid electrode which is opposite to the second semiconductor active layer on the third metal layer film.
In an exemplary embodiment of the present disclosure, the first insulating layer and the second insulating layer are each a silicon oxide thin film on a side contacting the first gate electrode and the light shielding layer.
According to an aspect of the present disclosure, a method for manufacturing an array substrate is provided, including the above method for manufacturing a thin film transistor; and the number of the first and second groups,
And forming a flat layer with a third via hole and a pixel electrode electrically connected with the second drain electrode through the third via hole above the second gate electrode.
According to an aspect of the present disclosure, an array substrate is provided, which includes a thin film transistor manufactured by the above method for manufacturing a thin film transistor;
The first grid, the first semiconductor active layer, the first source and the first drain constitute a first thin film transistor of a peripheral circuit region of the array substrate;
The second grid electrode, the second semiconductor active layer, the second source electrode and the second drain electrode form a second thin film transistor of the effective display area of the array substrate.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
The second thin film transistor comprises a second gate electrode, a second through hole and a pixel electrode, wherein the second through hole is formed in the second gate electrode, and the pixel electrode is electrically connected with the second drain electrode of the second thin film transistor through the second through hole.
According to an aspect of the present disclosure, a display device is provided, which includes the array substrate.
In the thin film transistor and array substrate manufacturing method, the array substrate, and the display device according to the exemplary embodiment of the present disclosure, the thin film transistor in the peripheral circuit region 10a and the thin film transistor in the effective display region 10b are designed to be in a top gate structure, and the above special process is adopted to achieve the purpose of reducing the number of patterning processes. Thus, compared with the prior art, the exemplary embodiment can effectively reduce the number of times of the patterning process, thereby achieving the effects of improving productivity and saving cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 schematically illustrates a flow chart for manufacturing a thin film transistor in an exemplary embodiment of the present disclosure;
Fig. 2 to 6 schematically illustrate a process for manufacturing a thin film transistor in an exemplary embodiment of the present disclosure;
Fig. 7 to 11 schematically illustrate a process of a one-time half gray scale mask process of a thin film transistor in an exemplary embodiment of the present disclosure;
Fig. 12 to 16 are schematic views illustrating another half gray scale mask process of the thin film transistor in the exemplary embodiment of the present disclosure;
Fig. 17 schematically illustrates a structure of an array substrate in an exemplary embodiment of the present disclosure;
Fig. 18 schematically illustrates a flow chart for manufacturing an array substrate in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The example embodiment provides a method for manufacturing a thin film transistor, which is applied to the manufacture of a GOA array substrate. As shown in fig. 1, the method for manufacturing a thin film transistor may include:
S1, as shown in fig. 2, forming a first semiconductor active layer 101 in the peripheral circuit region 10a by a one-step patterning process above the substrate;
S2, as shown in fig. 3, forming a first insulating layer 102 above the first semiconductor active layer 101, and forming a light shielding layer 103 located in the effective display region 10b and a first gate electrode 104 facing the first semiconductor active layer 101 above the first insulating layer 102 by a one-time patterning process;
S3, as shown in fig. 4, forming a second insulating layer 105 above the light shielding layer 103 and the first gate electrode 104, and forming a first via hole 106 and a second via hole 107 penetrating through the first insulating layer 102 and the second insulating layer 105 by a single patterning process, wherein the first via hole 106 and the second via hole 107 respectively expose two sides of the first semiconductor active layer 101;
S4, as shown in fig. 5, forming a second semiconductor reserved pattern 108 which is respectively in contact with and disconnected from both sides of the first semiconductor active layer 101 through the first via hole 106 and the second via hole 107, a first source electrode 109 and a first drain electrode 110 which are respectively located on the second semiconductor reserved pattern 108, a second semiconductor active layer 111 which faces the light shielding layer 103, and a second source electrode 112 and a second drain electrode 113 which are respectively in contact with both sides of the second semiconductor active layer 111, over the second insulating layer 105 through a one-time patterning process;
S5, as shown in fig. 6, a protective layer 114 and a second gate electrode 115 facing the second semiconductor active layer 111 are formed over the first source electrode 109, the first drain electrode 110, the second source electrode 112 and the second drain electrode 113 by a single patterning process.
The peripheral circuit region 10a is a region for providing the GOA circuit, and the effective display region 10b is a region for displaying actually. In this example, the first semiconductor active layer 101, the first gate electrode 104, the second semiconductor retention pattern 108, the first source electrode 109, and the first drain electrode 110 may constitute a first thin film transistor in the peripheral circuit region 10 a; the second semiconductor active layer 111, the second gate electrode 115, the second source electrode 112, and the second drain electrode 113 may constitute a second thin film transistor located in the effective display region 10 b.
It should be noted that: the one-time patterning process refers to one-time photolithography process, which may include, for example, exposure, development, and etching processes.
In the method for manufacturing a thin film transistor according to the exemplary embodiment of the present disclosure, the first thin film transistor located in the peripheral circuit region 10a and the second thin film transistor located in the effective display region 10b are designed to be of a top gate structure, and the above special process is adopted to achieve the purpose of reducing the number of patterning processes. Thus, compared with the prior art, the exemplary embodiment can effectively reduce the number of times of the patterning process, thereby achieving the effects of improving productivity and saving cost.
in the present exemplary embodiment, the first thin film transistor in the peripheral circuit region 10a is preferably an L TPS thin film transistor to facilitate a narrow frame design, and the second thin film transistor in the active display region 10b is preferably an L TPO thin film transistor to facilitate low frequency driving.
Based on this, the method for manufacturing the thin film transistor is described in detail below with reference to the accompanying drawings.
In step S1, referring to fig. 2, a first semiconductor active layer 101 located in the peripheral circuit region 10a is formed over the substrate by a one-time patterning process.
the substrate may be a substrate 10 such as a glass substrate or a flexible substrate, but may also be a substrate formed with other film layers such as the buffer layer 100. in view of the current-voltage (IV) characteristics and stability of the top gate type L TPS thin film transistor, the latter scheme, i.e., including the buffer layer 100, is preferably adopted in the present embodiment, and the buffer layer 100 may be provided as a silicon oxide thin film, for example.
For example, the step S1 may specifically include:
S101, forming a polycrystalline silicon thin film on the substrate with the buffer layer 100 by adopting an L TPS process;
S102, forming a polysilicon active layer in the peripheral circuit region 10a by the polysilicon thin film through a one-step patterning process, where the polysilicon active layer is the first semiconductor active layer 101.
The forming process of the polysilicon active layer may be, for example: coating a layer of photoresist on the polycrystalline silicon film, exposing the substrate coated with the photoresist by adopting a mask plate and developing the exposed substrate to obtain a photoresist reserved part and a photoresist removing part, wherein the photoresist reserved part corresponds to the polycrystalline silicon active layer to be formed, etching the polycrystalline silicon film exposed from the photoresist removing part by an etching process to transfer the pattern of the mask plate to the polycrystalline silicon film, and finally removing the residual photoresist to obtain the required polycrystalline silicon active layer.
In step S2, referring to fig. 3, a first insulating layer 102 is formed over the first semiconductor active layer 101, and a light shielding layer 103 located in the effective display region 10b and a first gate electrode 104 facing the first semiconductor active layer 101 are formed over the first insulating layer 102 by a one-time patterning process.
in this embodiment, the first insulating layer 102 may have a single-layer structure or a multi-layer structure, but in order to ensure the IV characteristics and stability of the L TPS thin film transistor, a silicon oxide film is required to be used on the side of the first insulating layer 102 contacting the light-shielding layer 103 and the first gate electrode 104, i.e., on the upper surface of the first insulating layer 102.
For example, the step S2 may specifically include:
S201, forming a first insulating layer 102 above the first semiconductor active layer 101, wherein the upper surface of the first insulating layer is a silicon oxide film;
S202, forming a first metal layer film above the first insulating layer 102;
S203, forming the light shielding layer 103 in the effective display area 10b and the first gate electrode 104 facing the first semiconductor active layer 101 on the first metal layer film by a single patterning process.
The forming process of the light-shielding layer 103 and the first gate 104 may be, for example: coating a layer of photoresist on the first metal layer film, exposing the substrate coated with the photoresist by using a mask plate and developing the exposed substrate to obtain a photoresist reserved part and a photoresist removing part, wherein the photoresist reserved part corresponds to the light shielding layer 103 and the first grid 104 to be formed, etching the first metal layer film exposed by the photoresist removing part by an etching process to transfer the pattern of the mask plate to the first metal layer film, and finally removing the residual photoresist to obtain the required light shielding layer 103 and the first grid 104.
Therefore, the light-shielding layer 103 in the effective display region 10b and the first gate 104 in the peripheral circuit region 10a can be formed by performing the same patterning process on the same metal layer, and the material and thickness of the two layers are the same. Since the effective display region 10b is an oxide thin film transistor and the oxide semiconductor active layer is very sensitive to light, the embodiment forms a light shielding layer 103 below the oxide thin film transistor to be formed to prevent the oxide thin film transistor from being modified by light, thereby ensuring the stability of the oxide thin film transistor.
In step S3, referring to fig. 4, a second insulating layer 105 is formed over the light shielding layer 103 and the first gate electrode 104, and a first via hole 106 and a second via hole 107 penetrating the first insulating layer 102 and the second insulating layer 105 are formed through a single patterning process, wherein the first via hole 106 and the second via hole 107 respectively expose both sides of the first semiconductor active layer 101.
in this embodiment, the second insulating layer 105 may have a single-layer structure or a multi-layer structure, and a side of the second insulating layer 105 facing away from the light-shielding layer 103 and the first gate electrode 104, that is, an upper surface of the second insulating layer 105 may have a silicon oxide film, since the second semiconductor active layer 111, such as a metal oxide semiconductor, is formed above the second insulating layer 105, and a layer having a higher hydrogen content, such as a silicon nitride film or a silicon oxynitride film, may be used to make a metal oxide semiconductor material conductive, thereby deteriorating the performance of the L TPO tft.
In this step, the forming process of the first via hole 106 and the second via hole 107 may be, for example: coating a layer of photoresist on the second insulating layer 105, exposing the substrate coated with the photoresist by using a mask plate and developing the exposed substrate to obtain a photoresist reserved part and a photoresist removed part, wherein the photoresist removed part corresponds to a first via hole 106 and a second via hole 107 to be formed, etching the second insulating layer 105 and the first insulating layer 102 exposed by the photoresist removed part by using an etching process to transfer the pattern of the mask plate to the second insulating layer 105 and the first insulating layer 102, and finally removing the residual photoresist to obtain the required first via hole 106 and second via hole 107.
In step S4, referring to fig. 5, a second semiconductor remaining pattern 108 that is respectively in contact with and disconnected from both sides of the first semiconductor active layer 101 by the first and second via holes 106 and 107, a first source electrode 109 and a first drain electrode 110 that are respectively positioned on the second semiconductor remaining pattern 108, a second semiconductor active layer 111 that faces the light shielding layer 103, and a second source electrode 112 and a second drain electrode 113 that are respectively in contact with both sides of the second semiconductor active layer 111 are formed over the second insulating layer 105 through a single patterning process.
The second semiconductor remaining pattern 108 and the second semiconductor active layer 111 may be made of materials including, but not limited to, IGZTO (Indium Gallium Zinc Tin Oxide), IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IGTO (Indium Gallium Tin Oxide), IZO (Indium Gallium Zinc Oxide), and oxynitride of Zinc.
The second semiconductor reserved pattern 108 and the second semiconductor active layer 111 are formed at the same layer, and the first source electrode 109 and the first drain electrode 110 and the second source electrode 112 and the second drain electrode 113 are formed at the same layer.
For example, as shown in fig. 7 to 11, the step S4 may specifically include:
S401, sequentially forming a metal oxide semiconductor film 201 and a second metal layer film 202 above the second insulating layer 105;
S402, a half gray-scale mask process is adopted to enable the metal oxide semiconductor film 201 to form a metal oxide semiconductor retaining pattern 108 which is respectively contacted and disconnected with two sides of the first semiconductor active layer 101 through the first through hole 106 and the second through hole 107, and a metal oxide semiconductor active layer which is opposite to the shading layer 103, namely a second semiconductor active layer 111, and enable the second metal film 202 to form a first source electrode 109 and a first drain electrode 110 which are respectively positioned on the metal oxide semiconductor retaining pattern, and a second source electrode 112 and a second drain electrode 113 which are respectively contacted with two sides of the metal oxide semiconductor active layer.
The semi-gray level mask process comprises the following specific processes: coating a layer of photoresist 200 on a substrate on which a metal oxide semiconductor film 201 and a second metal layer film 202 are formed, exposing the substrate coated with the photoresist 200 by using a halftone mask or a gray-tone mask and developing the exposed substrate to obtain a photoresist complete retention portion 20a, a photoresist half retention portion 20b and a photoresist removal portion 20c, wherein the photoresist complete retention portion 20a corresponds to a metal oxide semiconductor retention pattern 108 to be formed, a first source electrode 109 and a first drain electrode 110, and a second source electrode 112 and a second drain electrode 113; sequentially etching the second metal layer film 202 and the metal oxide semiconductor film 201 exposed by the photoresist removing part 20c by an etching process to obtain a metal oxide semiconductor retention pattern 108, a first source electrode 109 and a first drain electrode 110; removing the photoresist 20 of the photoresist half-remaining portion 20b by ashing, and etching the exposed second metal layer film 202 by an etching process to obtain the second source electrode 112 and the second drain electrode 113, and the second semiconductor active layer 111; finally, the remaining photoresist is removed to obtain the substrate shown in fig. 5.
In step S5, referring to fig. 6, a protective layer 114 and a second gate electrode 115 facing the second semiconductor active layer 111 are formed over the first source electrode 109, the first drain electrode 110, the second source electrode 112 and the second drain electrode 113 by a single patterning process.
The protective layer 114 may have a single-layer structure or a multi-layer structure, and may be formed using a resin.
For example, as shown in fig. 12 to 16, the step S5 may specifically include:
S501, sequentially forming a protective layer film 301 and a third metal layer film 302 above the first source electrode 109, the first drain electrode 110, the second source electrode 112 and the second drain electrode 113;
S502, a half gray scale mask process is used to form a region in the protective layer film 301 to separate the effective display region 10b from the peripheral circuit region 10a to form the protective layer 114, and the third metal layer film 301 is used to form the second gate electrode 115 facing the second semiconductor active layer.
The semi-gray level mask process comprises the following specific processes: coating a layer of photoresist 200 on a substrate on which a protective layer film 301 and a third metal layer film 302 are formed, exposing the substrate coated with the photoresist 200 by using a halftone mask or a gray tone mask and developing the exposed substrate to obtain a photoresist complete retention part 20a, a photoresist semi-retention part 20b and a photoresist removal part 20c, wherein the photoresist complete retention part 20a corresponds to a second gate electrode 115 to be formed; etching the third metal layer film 302 and the protective layer film 301 exposed by the photoresist removing portion 20c by an etching process to obtain a protective layer 114 that separates the effective display area 10b from the peripheral circuit area 10 a; removing the photoresist 20 of the photoresist half-remaining portion 20b by ashing, and etching the exposed third metal layer thin film 302 by an etching process to obtain a second gate electrode 115 facing the second semiconductor active layer; finally, the remaining photoresist is removed to obtain the substrate shown in fig. 6.
Based on the above process, the first thin film transistor in the peripheral circuit region 10a and the second thin film transistor in the effective display region 10b can be obtained by five patterning processes. Wherein the first thin film transistor may include a first semiconductor active layer 101, a first gate electrode 104, a second semiconductor retention pattern 108, and first source and drain electrodes 109 and 110, and the second thin film transistor may include a second semiconductor active layer 111, a second gate electrode 115, and second source and drain electrodes 112 and 113.
The present exemplary embodiment further provides a method for manufacturing an array substrate, as shown in fig. 17, including the above-described method for manufacturing a thin film transistor and forming a pixel electrode 117 above the second thin film transistor in the effective display area 10 b.
Based on this, as shown in fig. 18, the method for manufacturing the array substrate may specifically include:
S1, referring to fig. 2, forming a first semiconductor active layer 101 in the peripheral circuit region 10a by a one-step patterning process above the substrate;
S2, referring to fig. 3, forming a first insulating layer 102 on the first semiconductor active layer 101, and forming a light shielding layer 103 in the effective display region 10b and a first gate electrode 104 opposite to the first semiconductor active layer 101 on the first insulating layer 102 by a one-time patterning process;
S3, referring to fig. 4, forming a second insulating layer 105 over the light shielding layer 103 and the first gate electrode 104, and forming a first via hole 106 and a second via hole 107 penetrating through the first insulating layer 102 and the second insulating layer 105 by a single patterning process, wherein the first via hole 106 and the second via hole 107 respectively expose two sides of the first semiconductor active layer 101;
S4, referring to fig. 5, forming a second semiconductor remaining pattern 108 which is respectively in contact with and disconnected from both sides of the first semiconductor active layer 101 through the first via hole 106 and the second via hole 107, a first source electrode 109 and a first drain electrode 110 which are respectively located on the second semiconductor remaining pattern 108, a second semiconductor active layer 111 facing the light shielding layer 103, and a second source electrode 112 and a second drain electrode 113 which are respectively in contact with both sides of the second semiconductor active layer 111, over the second insulating layer 105 through a single patterning process;
S5, referring to fig. 6, a protective layer 114 and a second gate electrode 115 facing the second semiconductor active layer 111 are formed over the first source electrode 109, the first drain electrode 110, the second source electrode 112 and the second drain electrode 113 by a single patterning process.
S6, referring to fig. 18, a planarization layer 116 having a third via hole and a pixel electrode 117 electrically connected to the second drain electrode 113 through the third via hole are formed above the second gate electrode 115.
It should be noted that: the third via hole in the planarization layer 116 needs to penetrate the protection layer 114 to electrically connect to the second drain electrode 113, so the third via hole can be formed at the same time when the protection layer 114 is formed in step S5.
based on the above steps S1-S6, a GOA array substrate is formed, wherein the array substrate includes a first thin film transistor, such as an L TPS thin film transistor, located in the peripheral circuit region 10a and a second thin film transistor, such as an L TPO thin film transistor, located in the active display region 10 b.
Thus, the array substrate manufactured by the method for manufacturing an array substrate provided by the exemplary embodiment can not only realize the functions of narrow frame and power consumption reduction, but also reduce the number of patterning processes of the GOA array substrate, thereby improving the productivity and reducing the cost.
Based on this, the present exemplary embodiment also provides an array substrate, as shown in fig. 18, including a thin film transistor manufactured by the above-described method of manufacturing a thin film transistor, and a pixel electrode 117 formed above the thin film transistor in the effective display region 10 b.
Wherein the first semiconductor active layer 101, the first gate electrode 104, the second semiconductor retention pattern 108, the first source electrode 109 and the first drain electrode 110 may constitute a first thin film transistor in the peripheral circuit region 10 a; the second semiconductor active layer 111, the second gate electrode 115, the second source electrode 112, and the second drain electrode 113 may constitute a second thin film transistor located in the effective display region 10 b.
In this embodiment, the pixel electrode 117 may be electrically connected to the second drain electrode 113 of the second thin film transistor, which may be electrically connected to the second drain electrode 113 of the second thin film transistor through a third via hole penetrating the planarization layer 116 and the protection layer 114, for example.
The array substrate can realize the functions of narrow frame and power consumption reduction at the same time, and can reduce the composition process times of the GOA array substrate, thereby improving the productivity and reducing the cost.
The exemplary embodiment also provides a display device, which includes the array substrate, where the array substrate is a GOA array substrate.
The display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (10)
1. A method for manufacturing a thin film transistor includes:
Forming a first semiconductor active layer positioned in a peripheral circuit region above the substrate through a one-step composition process;
Forming a first insulating layer above the first semiconductor active layer, and forming a light shielding layer located in an effective display area and a first gate electrode facing the first semiconductor active layer above the first insulating layer through a one-time composition process;
Forming a second insulating layer above the light shielding layer and the first gate, and forming a first via hole and a second via hole penetrating through the first insulating layer and the second insulating layer by a one-time composition process, wherein the first via hole and the second via hole respectively expose two sides of the first semiconductor active layer;
Forming a disconnected second semiconductor reserved pattern which is respectively contacted with two sides of the first semiconductor active layer through the first via hole and the second via hole, a first source electrode and a first drain electrode which are respectively positioned on the second semiconductor reserved pattern, a second semiconductor active layer which is opposite to the light shielding layer, and a second source electrode and a second drain electrode which are respectively contacted with two sides of the second semiconductor active layer through a one-time composition process above the second insulating layer;
And forming a protective layer and a second grid electrode which is opposite to the second semiconductor active layer above the first source electrode, the first drain electrode, the second source electrode and the second drain electrode through a one-time composition process.
2. The method of claim 1, wherein forming the first semiconductor active layer on the peripheral circuit region by a single patterning process over the substrate comprises:
And forming a polycrystalline silicon thin film on the substrate with the buffer layer by adopting a low-temperature polycrystalline silicon process, and forming a polycrystalline silicon active layer positioned in the peripheral circuit region on the polycrystalline silicon thin film by adopting a one-step composition process, wherein the polycrystalline silicon active layer is the first semiconductor active layer.
3. The method of claim 1, wherein forming a light shielding layer over the first insulating layer and over the active display region and a first gate electrode opposite to the first semiconductor active layer by a single patterning process comprises:
And forming a first metal layer film above the first insulating layer, and forming a light shielding layer positioned in the effective display area and a first grid electrode opposite to the first semiconductor active layer on the first metal layer film through a one-time composition process.
4. The method of manufacturing according to claim 1, wherein forming, by a single patterning process, the disconnected second semiconductor remaining pattern, the first source electrode and the first drain electrode on the second semiconductor remaining pattern, the second semiconductor active layer facing the light shielding layer, and the second source electrode and the second drain electrode in contact with both sides of the second semiconductor active layer through the first via hole and the second via hole, respectively, over the second insulating layer comprises:
Sequentially forming a metal oxide semiconductor film and a second metal layer film above the second insulating layer;
Forming a disconnected metal oxide semiconductor retaining pattern which is respectively contacted with two sides of the first semiconductor active layer through the first via hole and the second via hole and a metal oxide semiconductor active layer which is opposite to the shading layer by the metal oxide semiconductor thin film by adopting a half gray scale mask process, and forming a first source electrode and a first drain electrode which are respectively positioned on the metal oxide semiconductor retaining pattern and a second source electrode and a second drain electrode which are respectively contacted with two sides of the metal oxide semiconductor active layer by the second metal thin film;
Wherein the metal oxide semiconductor retention pattern is the second semiconductor retention pattern; the metal oxide semiconductor active layer is the second semiconductor active layer.
5. The method according to claim 1, wherein forming a protective layer and a second gate electrode facing the second semiconductor active layer over the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode by a single patterning process comprises:
Sequentially forming a protective layer film and a third metal layer film above the first source electrode, the first drain electrode, the second source electrode and the second drain electrode;
And forming a region for disconnecting the effective display region and the peripheral circuit region in the protective layer film by adopting a half gray scale mask process to form the protective layer, and forming a second grid electrode which is opposite to the second semiconductor active layer on the third metal layer film.
6. The production method according to any one of claims 1 to 5, wherein the first insulating layer and the second insulating layer are both silicon oxide thin films on a side contacting the first gate electrode and the light-shielding layer.
7. A method for manufacturing an array substrate, comprising the method for manufacturing a thin film transistor according to any one of claims 1 to 6; and the number of the first and second groups,
And forming a flat layer with a third via hole and a pixel electrode electrically connected with the second drain electrode through the third via hole above the second gate electrode.
8. An array substrate comprising a thin film transistor produced by the method for producing a thin film transistor according to any one of claims 1 to 6;
The first grid, the first semiconductor active layer, the first source and the first drain constitute a first thin film transistor of a peripheral circuit region of the array substrate;
The second grid electrode, the second semiconductor active layer, the second source electrode and the second drain electrode form a second thin film transistor of the effective display area of the array substrate.
9. The array substrate of claim 8, further comprising:
The second thin film transistor comprises a second gate electrode, a second through hole and a pixel electrode, wherein the second through hole is formed in the second gate electrode, and the pixel electrode is electrically connected with the second drain electrode of the second thin film transistor through the second through hole.
10. A display device comprising the array substrate according to claim 8 or 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810040432.3A CN108231671B (en) | 2018-01-16 | 2018-01-16 | Preparation method of thin film transistor and array substrate, array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810040432.3A CN108231671B (en) | 2018-01-16 | 2018-01-16 | Preparation method of thin film transistor and array substrate, array substrate and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108231671A CN108231671A (en) | 2018-06-29 |
| CN108231671B true CN108231671B (en) | 2020-07-31 |
Family
ID=62640590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810040432.3A Active CN108231671B (en) | 2018-01-16 | 2018-01-16 | Preparation method of thin film transistor and array substrate, array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108231671B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273409B (en) * | 2018-08-24 | 2022-01-18 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN109192736A (en) * | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
| CN111613637B (en) * | 2019-02-26 | 2022-10-28 | 京东方科技集团股份有限公司 | Display substrate, bad adjusting method thereof and display device |
| CN110148600A (en) * | 2019-05-05 | 2019-08-20 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method |
| CN111128874A (en) * | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
| CN111668238B (en) * | 2020-06-19 | 2022-09-09 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and manufacturing method thereof |
| US12022698B2 (en) | 2020-09-22 | 2024-06-25 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate, display panel, and display device |
| CN112309990B (en) * | 2020-10-30 | 2023-03-28 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN113571531B (en) * | 2021-07-12 | 2023-10-03 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN113611712B (en) * | 2021-07-29 | 2023-10-17 | 武汉华星光电技术有限公司 | Array substrate, display panel and manufacturing method thereof |
| CN116487388A (en) * | 2022-01-14 | 2023-07-25 | 京东方科技集团股份有限公司 | Array substrate and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187417A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor device and method for manufacturing the same |
| CN103715196A (en) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105408813A (en) * | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon and semiconducting oxide thin-film transistors |
| CN106803510A (en) * | 2015-11-26 | 2017-06-06 | 乐金显示有限公司 | Thin film transistor base plate, display and its manufacture method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101048965B1 (en) * | 2009-01-22 | 2011-07-12 | 삼성모바일디스플레이주식회사 | Organic electroluminescent display |
-
2018
- 2018-01-16 CN CN201810040432.3A patent/CN108231671B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187417A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor device and method for manufacturing the same |
| CN105408813A (en) * | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon and semiconducting oxide thin-film transistors |
| CN103715196A (en) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106803510A (en) * | 2015-11-26 | 2017-06-06 | 乐金显示有限公司 | Thin film transistor base plate, display and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108231671A (en) | 2018-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108231671B (en) | Preparation method of thin film transistor and array substrate, array substrate and display device | |
| CN108231795B (en) | Array substrate, manufacturing method, display panel and display device | |
| US10312268B2 (en) | Display device | |
| US9711542B2 (en) | Method for fabricating display panel | |
| US9502436B2 (en) | Thin film transistor, array substrate and method for fabricating the same, and display device | |
| US20140120657A1 (en) | Back Channel Etching Oxide Thin Film Transistor Process Architecture | |
| US8895334B2 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
| US10964790B1 (en) | TFT substrate and manufacturing method thereof | |
| US11087985B2 (en) | Manufacturing method of TFT array substrate | |
| WO2018201770A1 (en) | Array substrate, preparation method therefor and display device | |
| US10263115B2 (en) | Thin film transistor and manufacturing method of the same, array substrate and display device | |
| CN103137558A (en) | Twisted nematic (TN) type array substrate and manufacturing method thereof and display device thereof | |
| US20160027797A1 (en) | Array substrate, manufacturing method thereof, and display device | |
| US6500702B2 (en) | Method for manufacturing thin film transistor liquid crystal display | |
| US8421096B2 (en) | Pixel structure and display panel | |
| US10763283B2 (en) | Array substrate, manufacturing method thereof, display panel and manufacturing method thereof | |
| US6558992B2 (en) | Method to fabricate flat panel display | |
| KR20070068776A (en) | Liquid crystal display device and fabricating method thereof | |
| CN109119428B (en) | Manufacturing method of TFT substrate | |
| US8021972B1 (en) | Method of manufacturing array substrate | |
| CN109937484B (en) | Thin film transistor, array substrate, display device and method for manufacturing thin film transistor | |
| JP2003031780A (en) | Method for manufacturing thin film transistor panel | |
| CN201251667Y (en) | Thin film transistor array substrate | |
| US8536575B2 (en) | Pixel structure of display panel and method of fabricating the same | |
| CN111863728A (en) | Array substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |