CN108231671A - The preparation method of thin film transistor (TFT) and array substrate, array substrate and display device - Google Patents
The preparation method of thin film transistor (TFT) and array substrate, array substrate and display device Download PDFInfo
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- CN108231671A CN108231671A CN201810040432.3A CN201810040432A CN108231671A CN 108231671 A CN108231671 A CN 108231671A CN 201810040432 A CN201810040432 A CN 201810040432A CN 108231671 A CN108231671 A CN 108231671A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The disclosure provides preparation method, array substrate, the display device of a kind of thin film transistor (TFT) and array substrate.The preparation method of the thin film transistor (TFT) includes：The first semiconductor active layer is formed by a patterning processes；It forms the first insulating layer and passes through a patterning processes and form the light shield layer and first grid for being located at effective display area；It forms second insulating layer and passes through a patterning processes and formed through the first insulating layer and the via of second insulating layer；The semiconductor being in contact by a patterning processes formation by via with the first semiconductor active layer retains pattern, the first source electrode and the first drain electrode on semiconductor reservation pattern, the second semiconductor active layer of face light shield layer and the second source electrode being in contact with the second semiconductor active layer and the second drain electrode；The second grid of the second semiconductor active layer of protective layer and face is formed by a patterning processes.The disclosure can reduce patterning processes number, and raising production capacity is simultaneously cost-effective.
Description
Technical field
This disclosure relates to display technology field more particularly to the preparation method of a kind of thin film transistor (TFT) and array substrate, battle array
Row substrate and display device.
Background technology
Display device presented the development trend of high integration and low cost in recent years.It is driven with array substrate row
(Gate Driver on Array, GOA) technology is representative, and gate driving circuit is integrated in array substrate using GOA technologies
Neighboring area, can while narrow frame design is realized, it is effective promote module process yields, promote product yield and
It is cost-effective.
Low-temperature polysilicon oxide (Low Temperature Poly-Oxide, LTPO) technology is film emerging in recent years
Transistor technology.In order to ensure that liquid crystal display (Liquid Crystal Display, LCD) or Organic Light Emitting Diode are shown
Show that device (Orginic Light Emitting Diode, OLED) can be achieved at the same time narrow frame and low-power consumption function, in GOA areas
Domain would generally prepare thin film transistor (TFT) using low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) technology,
It since the mobility of LTPS thin film transistor (TFT)s is high, size is smaller, can effectively reduce frame size, and effectively show
Area would generally use metal oxide thin-film transistor, due to metal oxide thin-film transistor can with low frequency driving, it is minimum can
To 1Hz, therefore power consumption can be effectively reduced.But it is more using the patterning processes number of LTPO technologies at present, such as from more
Crystal silicon layer at least needs 7~8 photoetching processes to protective layer, therefore process costs are higher.
It should be noted that information is only used for strengthening the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore can include not forming the information to the prior art known to persons of ordinary skill in the art.
Invention content
A kind of preparation method for being designed to provide thin film transistor (TFT) and array substrate of the disclosure, array substrate and
Display device, for solve the patterning processes number of array substrate it is excessive caused by production capacity it is too low and cost is excessively high asks
Topic.
Other characteristics and advantages of the disclosure will be by the following detailed description apparent from or partially by the disclosure
Practice and acquistion.
According to one aspect of the disclosure, a kind of preparation method of thin film transistor (TFT) is provided, including：
The first semiconductor active layer for being located at periphery circuit region is formed by a patterning processes in the top of substrate；
The first insulating layer is formed, and lead in the top of first insulating layer in the top of first semiconductor active layer
Cross the first grid that a patterning processes form the first semiconductor active layer described in the light shield layer for being located at effective display area and face
Pole；
Second insulating layer is formed, and pass through a patterning processes and formed in the top of the light shield layer and the first grid
Through first insulating layer and the first via and the second via of the second insulating layer, first via and described
Two vias expose the both sides of first semiconductor active layer respectively；
It is formed in the top of the second insulating layer by a patterning processes through first via and described second
Second semiconductor of the disconnection that via is in contact respectively with the both sides of first semiconductor active layer retains pattern, is located at respectively
Second semiconductor active of light shield layer described in the first source electrode and the first drain electrode, face on the second semiconductor reservation pattern
Layer and the second source electrode being in contact respectively with the both sides of second semiconductor active layer and the second drain electrode；
Pass through in first source electrode, first drain electrode, second source electrode and the top of second drain electrode primary
Patterning processes form the second grid of the second semiconductor active layer described in protective layer and face.
In a kind of exemplary embodiment of the disclosure, formed in the top of substrate by a patterning processes and be located at periphery electricity
First semiconductor active layer in road area includes：
Polysilicon membrane is formed on the substrate for be formed with buffer layer using low temperature polysilicon process, and passes through a composition
Technique makes the polysilicon membrane form the polysilicon active layer positioned at the periphery circuit region.
In a kind of exemplary embodiment of the disclosure, formed in the top of first insulating layer by a patterning processes
The first grid of the first semiconductor active layer includes described in light shield layer and face positioned at effective display area：
The first metal layer film is formed in the top of first insulating layer, makes first gold medal by a patterning processes
Belong to the first grid that layer film forms the first semiconductor active layer described in the light shield layer for being located at the effective display area and face.
In a kind of exemplary embodiment of the disclosure, formed in the top of the second insulating layer by a patterning processes
The disconnection being in contact with the both sides of first semiconductor active layer respectively by first via and second via
Second semiconductor retains pattern, the first source electrode being located at respectively on second semiconductor reservation pattern and the first drain electrode, face
Second semiconductor active layer of the light shield layer and be in contact respectively with the both sides of second semiconductor active layer second
Source electrode and the second drain electrode include：
Metal oxide semiconductor films and second metal layer film are sequentially formed above the second insulating layer；
The metal oxide semiconductor films is made to be formed through first via and institute using half gray level mask technique
The metal-oxide semiconductor (MOS) for stating the disconnection that the second via is in contact respectively with the both sides of first semiconductor active layer retains
The metal-oxide semiconductor (MOS) active layer of light shield layer described in pattern and face, and form the second metal layer film and divide
Not Wei Yu the metal-oxide semiconductor (MOS) retain the first source electrode on pattern and the first drain electrode and respectively with the metal oxygen
The second source electrode and the second drain electrode that the both sides of compound semiconductor active layer are in contact.
In a kind of exemplary embodiment of the disclosure, first source electrode, it is described first drain electrode, second source electrode and
The top of second drain electrode forms the of the second semiconductor active layer described in protective layer and face by patterning processes
Two grids include：
It is sequentially formed in first source electrode, first drain electrode, second source electrode and the top of second drain electrode
Protect layer film and third metal layer thin film；
Being formed in the protection layer film using half gray level mask technique makes the effective display area and periphery electricity
There is the second semiconductor described in the third metal layer thin film formation face in the region that road area disconnects to form the protective layer
The second grid of active layer.
In a kind of exemplary embodiment of the disclosure, first insulating layer and the second insulating layer are contacting described the
The side of one grid and the light shield layer is silicon oxide film.
According to one aspect of the disclosure, a kind of preparation method of array substrate is provided, including above-mentioned thin film transistor (TFT)
Preparation method；And
The flatness layer with third via is formed in the top of second grid and is leaked by the third via and second
The pixel electrode of pole electrical connection.
According to one aspect of the disclosure, a kind of array substrate is provided, includes the preparation method of above-mentioned thin film transistor (TFT)
Prepared by thin film transistor (TFT)；
First grid, the first semiconductor active layer, the first source electrode and the first drain electrode form the periphery electricity of the array substrate
The first film transistor in road area；
Second grid, the second semiconductor active layer, the second source electrode and the second drain electrode form the effectively aobvious of the array substrate
Show second thin film transistor (TFT) in area.
In a kind of exemplary embodiment of the disclosure, the array substrate further includes：
Flatness layer with third via above the second grid and by the third via with it is described
The pixel electrode of second drain electrode electrical connection of the second thin film transistor (TFT).
According to one aspect of the disclosure, a kind of display device is provided, including above-mentioned array substrate.
Thin film transistor (TFT) and the preparation method of array substrate that disclosure illustrative embodiments are provided, array substrate,
And display device, it will be set positioned at the thin film transistor (TFT) of periphery circuit region 10a and positioned at the thin film transistor (TFT) of effective display area 10b
Top-gate type structure is calculated as, and special process more than use handles and achievees the purpose that reduce patterning processes number.So,
Compared with the prior art, this example embodiment can effectively reduce the number of patterning processes, so as to reach improve production capacity with
And cost-effective effect.
It should be understood that above general description and following detailed description are only exemplary and explanatory, not
The disclosure can be limited.
Description of the drawings
Attached drawing herein is incorporated into specification and forms the part of this specification, shows the implementation for meeting the disclosure
Example, and for explaining the principle of the disclosure together with specification.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments, for those of ordinary skill in the art, without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 schematically shows the preparation flow figure of thin film transistor (TFT) in disclosure exemplary embodiment；
Fig. 2 to Fig. 6 schematically shows the preparation process schematic diagram of thin film transistor (TFT) in disclosure exemplary embodiment；
Fig. 7 to Figure 11 schematically shows the primary half gray level mask technique of thin film transistor (TFT) in disclosure exemplary embodiment
Process schematic；
Figure 12 to Figure 16 schematically shows another half gray level mask of thin film transistor (TFT) in disclosure exemplary embodiment
The process schematic of technique；
Figure 17 schematically shows the structure diagram of array substrate in disclosure exemplary embodiment；
Figure 18 schematically shows the preparation flow figure of array substrate in disclosure exemplary embodiment.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be in any suitable manner incorporated in one or more embodiments.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note represents same or similar part, thus will omit repetition thereof.Attached some block diagrams shown in figure are work(
Can entity, not necessarily must be corresponding with physically or logically independent entity.Software form may be used to realize these work(
Entity or these functional entitys can be realized in one or more hardware modules or integrated circuit or at heterogeneous networks and/or place
These functional entitys are realized in reason device device and/or microcontroller device.
This example embodiment provides a kind of preparation method of thin film transistor (TFT), the preparation applied to GOA array substrates.
As shown in Figure 1, the preparation method of the thin film transistor (TFT) can include：
S1, it is located at the first of periphery circuit region 10a as shown in Fig. 2, being formed in the top of substrate by a patterning processes
Semiconductor active layer 101；
S2, as shown in figure 3, the top of the first semiconductor active layer 101 formed the first insulating layer 102, and first absolutely
It is led by the light shield layer 103 and face the first half that patterning processes are formed positioned at effective display area 10b the top of edge layer 102
The first grid 104 of body active layer 101；
S3, as shown in figure 4, forming second insulating layer 105 in the top of light shield layer 103 and first grid 104, and pass through one
Secondary patterning processes are formed through the first insulating layer 102 and the first via 106 and the second via 107 of second insulating layer 105, should
First via 106 and second via 107 respectively expose the both sides of the first semiconductor active layer 101；
S4, pass through the first via 106 as shown in figure 5, being formed in the top of second insulating layer 105 by a patterning processes
Retain pattern with the second semiconductor that the second via 107 is in contact and disconnects with the both sides of the first semiconductor active layer 101 respectively
108th, it is located at the second semiconductor respectively and retains the first source electrode 109 on pattern 108 and the first drain electrode 110, face light shield layer 103
Second semiconductor active layer 111 and the second source electrode 112 being in contact respectively with the both sides of the second semiconductor active layer 111 and
Second drain electrode 113；
S5, as shown in fig. 6, the top of drain in the first source electrode 109, first 110, second source electrode 112 and the second drain electrode 113
The second grid 115 of protective layer 114 and the second semiconductor active layer of face 111 is formed by a patterning processes.
Wherein, the periphery circuit region 10a refers to the region for setting GOA circuits, and the effective display area 10b refers to
It is actually used in the region of display.In this example, the first semiconductor active layer 101, first grid 104, the second semiconductor retain figure
Case 108, the first source electrode 109 and the first drain electrode 110 may make up the first film transistor positioned at periphery circuit region 10a；The second half
Conductor active layer 111, second grid 115, the second source electrode 112 and the second drain electrode 113 may make up the positioned at effective display area 10b
Two thin film transistor (TFT)s.
It should be noted that：Patterning processes refer to a photoetching process, such as can include exposure, show
The processes such as shadow and etching.
The preparation method for the thin film transistor (TFT) that disclosure illustrative embodiments are provided will be located at periphery circuit region 10a
First film transistor and be designed as top-gate type structure positioned at the second thin film transistor (TFT) of effective display area 10b, and use with
On special process processing and achieve the purpose that reduce patterning processes number.So, compared with the prior art, this example is real
The mode of applying can effectively reduce the number of patterning processes, so as to achieve the effect that improve production capacity and cost-effective.
In this example embodiment, the first film transistor positioned at periphery circuit region 10a is brilliant preferably using LTPS films
Body pipe, in order to realize narrow frame design, and the second thin film transistor (TFT) positioned at effective display area 10b preferably uses LTPO films
Transistor, in order to realize low frequency driving.
Based on this, the preparation method of the thin film transistor (TFT) is described in detail below in conjunction with the accompanying drawings.
In step sl, it is located at periphery circuit region refering to what is shown in Fig. 2, being formed in the top of substrate by a patterning processes
The first semiconductor active layer 101 of 10a.
Here substrate can be underlay substrate 10 such as glass substrate or flexible base board but it is also possible to be being formed with it
The substrate of its film layer such as buffer layer 100.Current-voltage (IV) characteristic in view of top gate type LTPS thin film transistor (TFT)s and steady
Qualitative, the present embodiment is preferably the scheme for including buffer layer 100 using the latter, and the buffer layer 100 for example could be provided as
Silicon oxide film.
Exemplary, this step S1 can specifically include：
S101, polysilicon membrane is formed on the substrate of buffer layer 100 is formed with using LTPS techniques；
S102, the polysilicon membrane is made to form the polycrystalline silicon active positioned at periphery circuit region 10a by a patterning processes
Layer, which is the first semiconductor active layer 101.
Wherein, the forming process of polysilicon active layer for example can be：One layer of photoetching is coated in the top of polysilicon membrane
Glue is exposed the substrate for being coated with photoresist using mask plate and develops to the substrate after exposure, to obtain photoetching
Glue member-retaining portion and photoresist removal part, the photoresist member-retaining portion are corresponding polysilicon active layer to be formed, pass through quarter
Photoresist is removed the polysilicon membrane exposed part and performed etching by etching technique, and the pattern of mask plate is transferred to the polysilicon
Film finally removes remaining photoresist, you can obtains required polysilicon active layer.
In step s 2, refering to what is shown in Fig. 3, forming the first insulating layer 102 in the top of the first semiconductor active layer 101,
And light shield layer 103 and just positioned at effective display area 10b is formed by patterning processes in the top of the first insulating layer 102
To the first grid 104 of the first semiconductor active layer 101.
In the present embodiment, the first insulating layer 102 can be single layer structure or multilayered structure, but in order to ensure LTPS films
Side i.e. the of the IV characteristics and stability of transistor, first insulating layer 102 contact light shield layer 103 and first grid 104
The upper surface of one insulating layer 102 is needed using silicon oxide film.It follows that the first insulating layer 102 can be silicon oxide film
Single layer structure or multilayered structure for upper strata silicon oxide film and lower floor's silicon nitride film.
Exemplary, this step S2 can specifically include：
S201, the first insulating layer 102, the upper table of first insulating layer are formed in the top of the first semiconductor active layer 101
Face is silicon oxide film；
S202, the first metal layer film is formed in the top of the first insulating layer 102；
S203, the first metal layer film is made to form the light shield layer positioned at effective display area 10b by a patterning processes
103 and the first grid 104 of the first semiconductor active layer of face 101.
Wherein, the forming process of light shield layer 103 and first grid 104 for example can be：In the upper of the first metal layer film
One layer of photoresist of side's coating, is exposed the substrate for being coated with photoresist using mask plate and the substrate after exposure is shown
Shadow, to obtain photoresist member-retaining portion and photoresist removal part, which is corresponding light shield layer to be formed
103 and first grid 104, photoresist is removed by the first metal layer film exposed part by etching technics and is performed etching, with
The pattern of mask plate is transferred to the first metal layer film, finally removes remaining photoresist, you can obtain required shading
Layer 103 and first grid 104.
It follows that the light shield layer 103 positioned at effective display area 10b and the first grid 104 positioned at periphery circuit region 10a
It can be passed through by same layer metal with a patterning processes and obtained, the material and thickness all same of the two.Due to effective display area 10b
Using oxide thin film transistor, and oxide semiconductor active layer is very sensitive to light, therefore the present embodiment is treating shape
Into oxide thin film transistor below be initially formed a light shield layer 103, become to prevent oxide thin film transistor by illumination
Property, so as to ensure the stability of oxide thin film transistor.
In step s3, refering to what is shown in Fig. 4, forming second insulating layer in the top of light shield layer 103 and first grid 104
105, and pass through patterning processes and form the first via 106 through the first insulating layer 102 and second insulating layer 105 and the
Two vias 107, first via 106 and second via 107 respectively expose the both sides of the first semiconductor active layer 101.
In the present embodiment, second insulating layer 105 can be single layer structure or multilayered structure, which carries on the back
Silicon oxide film may be used in upper surface from light shield layer 103 and side, that is, second insulating layer 105 of first grid 104.Due to
It will form the second such as metal-oxide semiconductor (MOS) of semiconductor active layer 111 in the top of second insulating layer 105, and hydrogen content
Higher film layer such as silicon nitride film or silicon oxynitride film can make metal oxide semiconductor material conductor, so as to lead
The penalty of LTPO thin film transistor (TFT)s is caused, therefore the upper surface of the second insulating layer 105 is needed using silicon oxide film.Thus
It is found that second insulating layer 105 can be the single layer structure of silicon oxide film or be upper strata silicon oxide film and lower floor's silicon nitride
The multilayered structure of film.
In this step, the forming process of the first via 106 and the second via 107 for example can be：In second insulating layer 105
Top coat one layer of photoresist, the substrate for being coated with photoresist is exposed using mask plate and to the substrate after exposure into
Row development, to obtain photoresist member-retaining portion and photoresist removal part, photoresist removal part i.e. corresponding to be formed the
Photoresist is removed the second insulating layer 105 and first exposed part by one via 106 and the second via 107 by etching technics
Insulating layer 102 performs etching, and the pattern of mask plate is transferred to 105 and first insulating layer 102 of second insulating layer, is finally removed
Remaining photoresist, you can obtain required the first via 106 and the second via 107.
In step s 4, with reference to as shown in figure 5, being formed in the top of second insulating layer 105 by a patterning processes logical
It crosses the first via 106 and the second via 107 is in contact and disconnects with the both sides of the first semiconductor active layer 101 respectively the second half
Conductor, which retains pattern 108, is located at the second semiconductor respectively retains the first source electrode 109 on pattern 108 and the first drain electrode 110, just
It the second semiconductor active layer 111 to light shield layer 103 and is in contact respectively with the both sides of the second semiconductor active layer 111
Second source electrode 112 and the second drain electrode 113.
Wherein, the second semiconductor retains pattern 108 and the material of the second semiconductor active layer 111 can include but is not limited to
IGZTO (Indium Gallium Zinc Tin Oxide, indium gallium zinc tin oxide), IGZO (Indium Gallium Zinc
Oxide, indium gallium zinc oxide), ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide), IGTO (Indium
Gallium Tin Oxide, indium gallium tin-oxide), the nitrogen of IZO (Indium Zinc Oxide, indium-zinc oxide) and zinc
Oxide etc..
Second semiconductor retains 108 and second semiconductor active layer 111 of pattern and is formed in same layer, 109 He of the first source electrode
First drain electrode 110 and the second source electrode 112 and the second drain electrode 113 are formed in same layer.
Exemplary, as shown in Fig. 7 to Figure 11, this step S4 can specifically include：
S401, metal oxide semiconductor films 201 and second metal layer are sequentially formed in the top of second insulating layer 105
Film 202；
S402, metal oxide semiconductor films 201 is made to be formed through 106 and of the first via using half gray level mask technique
The metal-oxide semiconductor (MOS) that second via 107 is in contact and disconnects with the both sides of the first semiconductor active layer 101 respectively retains
The metal-oxide semiconductor (MOS) active layer of pattern 108 and face light shield layer 103 i.e. the second semiconductor active layer 111, and make
Two metal layer thin films 202 form the first source electrode 109 being located at respectively on metal-oxide semiconductor (MOS) reservation pattern and the first drain electrode
110 and the second source electrode 112 being in contact respectively with the both sides of metal-oxide semiconductor (MOS) active layer and the second drain electrode 113.
Wherein, the detailed process of the half gray level mask technique is：It is being formed with metal oxide semiconductor films 201 and
One layer of photoresist 200 is coated on the substrate of two metal layer thin films 202, using half-tone mask plate or gray mask plate to applying
The substrate for being covered with photoresist 200 is exposed and develops to the substrate after exposure, and part is fully retained to obtain photoresist
20a, half member-retaining portion 20b of photoresist and photoresist removal part 20c, the photoresist are fully retained part 20a i.e. correspondence and treat shape
Into metal-oxide semiconductor (MOS) retain pattern 108, the first source electrode 109 and the first drain electrode 110 and the second source electrode 112 and the
Two drain electrodes 113；Photoresist is removed to the second metal layer film 202 and metal oxide of part 20c exposings by etching technics
Semiconductive thin film 201 performs etching successively, retains pattern 108, the first source electrode 109 and first to obtain metal-oxide semiconductor (MOS)
Drain electrode 110；The photoresist 20 of half member-retaining portion 20b of removal photoresist is handled by being ashed, and passes through etching technics by exposing
Second metal layer film 202 performs etching, to obtain the second source electrode 112 and the second drain electrode 113 and the second semiconductor active layer
111；It finally removes remaining photoresist and can obtain substrate shown in fig. 5.
In step s 5, refering to what is shown in Fig. 6, in the first source electrode 109, first drain electrode the 110, second source electrode 112 and the second leakage
The top of pole 113 forms the second grid of protective layer 114 and the second semiconductor active layer of face 111 by a patterning processes
115。
Wherein, the protective layer 114 can be single layer structure or be multilayered structure, and resin shape specifically may be used
Into.
Exemplary, as shown in Figure 12 to Figure 16, this step S5 can specifically include：
S501, it is sequentially formed in the top of the first source electrode 109, first drain electrode the 110, second source electrode 112 and the second drain electrode 113
Protect layer film 301 and third metal layer thin film 302；
S502, it is formed in layer film 301 is protected using half gray level mask technique and makes effective display area 10b and peripheral circuit
The region that area 10a is disconnected makes third metal layer thin film 301 form the second semiconductor active layer of face to form protective layer 114
Second grid 115.
Wherein, the detailed process of the half gray level mask technique is：It is thin in formation matcoveredn film 301 and third metal layer
One layer of photoresist 200 is coated on the substrate of film 302, using half-tone mask plate or gray mask plate to being coated with photoresist
200 substrate is exposed and develops to the substrate after exposure, and part 20a, photoresist is fully retained to obtain photoresist
Half member-retaining portion 20b and photoresist removal part 20c, the photoresist are fully retained part 20a and correspond to second gate to be formed
Pole 115；By etching technics to photoresist remove part 20c expose third metal layer thin film 302 and protection layer film 301 into
Row etching, to obtain the protective layer 114 of effective display area 10b and periphery circuit region 10a disconnections；Removal light is handled by being ashed
The photoresist 20 of half member-retaining portion 20b of photoresist, and pass through etching technics and perform etching the third metal layer thin film 302 of exposing,
To obtain the second grid 115 of the second semiconductor active layer of face；Finally remove remaining photoresist can obtain it is shown in fig. 6
Substrate.
It is the first film crystal that can be obtained positioned at periphery circuit region 10a by five patterning processes based on the above process
Pipe and the second thin film transistor (TFT) positioned at effective display area 10b.Wherein, which can include the first semiconductor
Active layer 101, first grid 104, the second semiconductor retain 108 and first source electrode 109 of pattern and the first drain electrode 110, this
Two thin film transistor (TFT)s can include the second semiconductor active layer 111,115 and second source electrode 112 of second grid and the second drain electrode
113。
This example embodiment additionally provides a kind of preparation method of array substrate, as shown in figure 17, including above-mentioned film
The preparation method of transistor and positioned at effective display area 10b the second thin film transistor (TFT) top formed pixel electrode 117.
Based on this, as shown in figure 18, the preparation method of the array substrate can specifically include：
S1, refering to what is shown in Fig. 2, forming the positioned at periphery circuit region 10a by patterning processes in the top of substrate
Semiconductor active layer 101；
S2, refering to what is shown in Fig. 3, the first insulating layer 102 is formed in the top of the first semiconductor active layer 101, and first
The top of insulating layer 102 forms the light shield layer 103 and face the first half positioned at effective display area 10b by patterning processes
The first grid 104 of conductor active layer 101；
S3, refering to what is shown in Fig. 4, forming second insulating layer 105 in the top of light shield layer 103 and first grid 104, and pass through
Patterning processes are formed through the first insulating layer 102 and the first via 106 and the second via 107 of second insulating layer 105,
First via 106 and second via 107 respectively expose the both sides of the first semiconductor active layer 101；
S4, pass through the first via refering to what is shown in Fig. 5, being formed in the top of second insulating layer 105 by a patterning processes
106 and second the second semiconductor reservation figure that is in contact and disconnects with the both sides of the first semiconductor active layer 101 respectively of via 107
Case 108, the first source electrode 109 being located at respectively on the second semiconductor reservation pattern 108 and the first drain electrode 110, face light shield layer 103
The second semiconductor active layer 111 and the second source electrode 112 for being in contact respectively with the both sides of the second semiconductor active layer 111
With the second drain electrode 113；
S5, refering to what is shown in Fig. 6, draining the upper of the 110, second source electrode 112 and the second drain electrode 113 in the first source electrode 109, first
Side forms the second grid 115 of protective layer 114 and the second semiconductor active layer of face 111 by a patterning processes.
S6, with reference to shown in figure 18, flatness layer 116 with third via and logical is formed in the top of second grid 115
Cross the pixel electrode 117 that third via is electrically connected with the second drain electrode 113.
It should be noted that：Third via in flatness layer 116 also needs pierce through the protection layer 114 that could realize and the second drain electrode
Electrical connection between 113, thus in step s 5 formed protective layer 114 when can also be formed simultaneously the third via.
Based on above-mentioned steps S1-S6, you can form GOA array substrates, which includes being located at periphery circuit region 10a
First film transistor such as LTPS thin film transistor (TFT)s and positioned at effective display area 10b the second thin film transistor (TFT) for example
LTPO thin film transistor (TFT)s.
So, array substrate made from the preparation method of the array substrate provided using this example embodiment,
Narrow frame can not only be realized simultaneously and reduces the function of power consumption, and can also reduce the patterning processes of GOA array substrates
Number, so as to improve production capacity, reduce cost.
Based on this, this example embodiment additionally provides a kind of array substrate, with reference to shown in figure 18, including using above-mentioned thin
Prepared by preparation method of film transistor thin film transistor (TFT) and the thin film transistor (TFT) positioned at effective display area 10b top
Form pixel electrode 117.
Wherein, the first semiconductor active layer 101, first grid 104, the second semiconductor retain pattern 108, the first source electrode
109 and first drain electrode 110 may make up the first film transistor positioned at periphery circuit region 10a；Second semiconductor active layer 111,
Second grid 115, the second source electrode 112 and the second drain electrode 113 may make up the second thin film transistor (TFT) positioned at effective display area 10b.
In the present embodiment, pixel electrode 117 can be electrically connected, such as can with the second drain electrode 113 of the second thin film transistor (TFT)
To realize electricity by the second drain electrode 113 of third via and second thin film transistor (TFT) for penetrating flatness layer 116 and protective layer 114
Connection.
The array substrate can not only realize narrow frame and reduce the function of power consumption, but also can also reduce GOA times simultaneously
The patterning processes number of row substrate, so as to improve production capacity, reduce cost.
This example embodiment additionally provides a kind of display device, and including above-mentioned array substrate, which is GOA
Array substrate.
Wherein, the display device can for example include mobile phone, tablet computer, television set, laptop, digital phase
Any product or component with display function such as frame, navigator.
It should be noted that although several modules or list for acting the equipment performed are referred in above-detailed
Member, but this division is not enforceable.In fact, according to embodiment of the present disclosure, it is above-described two or more
The feature and function of module either unit can embody in a module or unit.A conversely, above-described mould
Either the feature and function of unit can be further divided into being embodied by multiple modules or unit block.
In addition, although describing each step of method in the disclosure with particular order in the accompanying drawings, this does not really want
Asking or implying must could realize according to the particular order come the step for performing these steps or having to carry out shown in whole
Desired result.It is additional or alternative, it is convenient to omit certain steps, by multiple steps merge into a step perform and/
Or a step is decomposed into execution of multiple steps etc..
Those skilled in the art will readily occur to the disclosure its after considering specification and putting into practice invention disclosed herein
His embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Adaptive change follow the general principle of the disclosure and including the undocumented common knowledge in the art of the disclosure or
Conventional techniques.Description and embodiments are considered only as illustratively, and the true scope and spirit of the disclosure are by claim
It points out.
It should be understood that the present disclosure is not limited to the precise structures that have been described above and shown in the drawings, and
And various modifications and changes may be made without departing from the scope thereof.The scope of the present disclosure is only limited by appended claim.
Claims (10)
1. a kind of preparation method of thin film transistor (TFT), which is characterized in that including：
The first semiconductor active layer for being located at periphery circuit region is formed by a patterning processes in the top of substrate；
The first insulating layer is formed, and pass through one in the top of first insulating layer in the top of first semiconductor active layer
Secondary patterning processes form the first grid of the first semiconductor active layer described in the light shield layer for being located at effective display area and face；
Second insulating layer is formed in the top of the light shield layer and the first grid, and passes through a patterning processes formation and runs through
In first insulating layer and the first via and the second via of the second insulating layer, first via and second mistake
Expose the both sides of first semiconductor active layer respectively in hole；
It is formed in the top of the second insulating layer by a patterning processes through first via and second via
Second semiconductor of the disconnection being in contact respectively with the both sides of first semiconductor active layer retains pattern, respectively positioned at described
Second semiconductor retain the first source electrode on pattern and the first drain electrode, light shield layer described in face the second semiconductor active layer, with
And the second source electrode being in contact respectively with the both sides of second semiconductor active layer and second drains；
Pass through a composition in first source electrode, first drain electrode, second source electrode and the top of second drain electrode
Technique forms the second grid of the second semiconductor active layer described in protective layer and face.
2. preparation method according to claim 1, which is characterized in that formed in the top of substrate by a patterning processes
The first semiconductor active layer positioned at periphery circuit region includes：
Polysilicon membrane is formed on the substrate for be formed with buffer layer using low temperature polysilicon process, and passes through a patterning processes
The polysilicon membrane is made to form the polysilicon active layer positioned at the periphery circuit region.
3. preparation method according to claim 1, which is characterized in that pass through a structure in the top of first insulating layer
The first grid that figure technique forms the first semiconductor active layer described in the light shield layer for being located at effective display area and face includes：
The first metal layer film is formed in the top of first insulating layer, makes the first metal layer by a patterning processes
Film forms the first grid of the first semiconductor active layer described in the light shield layer for being located at the effective display area and face.
4. preparation method according to claim 1, which is characterized in that pass through a structure in the top of the second insulating layer
The formation of figure technique is connected by the both sides of first via and second via respectively with first semiconductor active layer
Second semiconductor of tactile disconnection retains pattern, the first source electrode and first being located at respectively on second semiconductor reservation pattern
Second semiconductor active layer of light shield layer described in drain electrode, face and respectively the both sides phase with second semiconductor active layer
Second source electrode of contact and the second drain electrode include：
Metal oxide semiconductor films and second metal layer film are sequentially formed above the second insulating layer；
The metal oxide semiconductor films is made to be formed through first via and described the using half gray level mask technique
The metal-oxide semiconductor (MOS) reservation pattern for the disconnection that two vias are in contact respectively with the both sides of first semiconductor active layer,
And the metal-oxide semiconductor (MOS) active layer of light shield layer described in face, and the second metal layer film formation is made to be located at respectively
The metal-oxide semiconductor (MOS) retain the first source electrode on pattern and the first drain electrode and respectively with the metal oxide half
The second source electrode and the second drain electrode that the both sides of conductor active layer are in contact.
5. preparation method according to claim 1, which is characterized in that first source electrode, it is described first drain electrode, it is described
The top of second source electrode and second drain electrode forms the second semiconductor described in protective layer and face by a patterning processes
The second grid of active layer includes：
Protection is sequentially formed in first source electrode, first drain electrode, second source electrode and the top of second drain electrode
Layer film and third metal layer thin film；
Being formed in the protection layer film using half gray level mask technique makes the effective display area and the periphery circuit region
The region of disconnection makes the third metal layer thin film form the second semiconductor active layer described in face to form the protective layer
Second grid.
6. according to claim 1-5 any one of them preparation methods, which is characterized in that first insulating layer and described second
Insulating layer is silicon oxide film in the side for contacting the first grid and the light shield layer.
7. a kind of preparation method of array substrate, which is characterized in that including claim 1-6 any one of them thin film transistor (TFT)s
Preparation method；And
The flatness layer with third via is formed in the top of second grid and is drained by the third via and second electric
The pixel electrode of connection.
8. a kind of array substrate, which is characterized in that including the preparation using claim 1-6 any one of them thin film transistor (TFT)s
Prepared by method thin film transistor (TFT)；
First grid, the first semiconductor active layer, the first source electrode and the first drain electrode form the periphery circuit region of the array substrate
First film transistor；
Second grid, the second semiconductor active layer, the second source electrode and the second drain electrode form the effective display area of the array substrate
The second thin film transistor (TFT).
9. array substrate according to claim 8, which is characterized in that further include：
Flatness layer with third via above the second grid and pass through the third via and described second
The pixel electrode of second drain electrode electrical connection of thin film transistor (TFT).
10. a kind of display device, which is characterized in that including the array substrate described in claim 8 or 9.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192736A (en) * | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100182223A1 (en) * | 2009-01-22 | 2010-07-22 | Samsung Mobile Display Co., Ltd. | Organic light emitting display device |
| CN103187417A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor device and method for manufacturing the same |
| CN103715196A (en) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105408813A (en) * | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon and semiconducting oxide thin-film transistors |
| CN106803510A (en) * | 2015-11-26 | 2017-06-06 | 乐金显示有限公司 | Thin film transistor base plate, display and its manufacture method |
-
2018
- 2018-01-16 CN CN201810040432.3A patent/CN108231671B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100182223A1 (en) * | 2009-01-22 | 2010-07-22 | Samsung Mobile Display Co., Ltd. | Organic light emitting display device |
| CN103187417A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Semiconductor device and method for manufacturing the same |
| CN105408813A (en) * | 2013-08-26 | 2016-03-16 | 苹果公司 | Displays with silicon and semiconducting oxide thin-film transistors |
| CN103715196A (en) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106803510A (en) * | 2015-11-26 | 2017-06-06 | 乐金显示有限公司 | Thin film transistor base plate, display and its manufacture method |
Cited By (19)
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| CN109192736A (en) * | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
| JP7417549B2 (en) | 2019-02-26 | 2024-01-18 | 京東方科技集團股▲ふん▼有限公司 | Display substrate, its adjustment method, and display device |
| JP2022521108A (en) * | 2019-02-26 | 2022-04-06 | 京東方科技集團股▲ふん▼有限公司 | Display board and its adjustment method, display device |
| WO2020224095A1 (en) * | 2019-05-05 | 2020-11-12 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method, and display apparatus |
| CN111128874A (en) * | 2019-12-18 | 2020-05-08 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and OLED touch display device |
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| WO2022061523A1 (en) * | 2020-09-22 | 2022-03-31 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display apparatus |
| US12022698B2 (en) | 2020-09-22 | 2024-06-25 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate, display panel, and display device |
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