CN213483274U - TFT array substrate and display panel comprising same - Google Patents
TFT array substrate and display panel comprising same Download PDFInfo
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- CN213483274U CN213483274U CN202022837227.5U CN202022837227U CN213483274U CN 213483274 U CN213483274 U CN 213483274U CN 202022837227 U CN202022837227 U CN 202022837227U CN 213483274 U CN213483274 U CN 213483274U
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Abstract
The utility model provides a TFT array substrate and a display panel comprising the same, wherein the TFT array substrate comprises a first substrate and a circuit layer; the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer and a planarization layer; the first electrode layer includes electrodes of a plurality of thin film transistors; the first bonding pad layer comprises a plurality of first bonding pads; the first pad is electrically connected with the first electrode through contact holes respectively penetrating through the insulating layer; the insulating layer is provided with a plurality of grooves, and the projection of each groove on the first substrate covers the projection of the edge of the first pad on the first substrate. Have the utility model discloses a TFT array substrate's display panel has reduced because the planarization layer among the TFT array substrate leads to the electrical contact failure with the difference in height of first pad, has greatly improved the electric connection performance of circuit driver and TFT array substrate, has ensured drive signal's reliability, has improved display panel's yield.
Description
Technical Field
The utility model relates to a display panel field, specifically speaking relates to a TFT array substrate and including its display panel.
Background
A thin film transistor circuit for a display may include a pad, a buffer layer, an insulating layer, and a Planarization Layer (PLN), etc. The planarization layer may be patterned by photolithography to form contact holes at the metal electrodes, and pads electrically connected to the underlying metal electrodes may be formed at the contact holes by the patterning by photolithography.
The pad may be electrically connected to an electrode formed under a driver IC or a Flexible Printed Circuit (FPC) of the substrate through an Anisotropic Conductive Film (ACF).
In order to prevent the metal electrode under the pad from being exposed to the etchant for etching the pad on the upper layer, the pad covers the metal electrode under, and at this time, a thicker planarization layer is required, which may cover the edge of the pad due to the fluidity of the surface of the planarization layer, so that the surface of the pad is relatively lower than the surface of the planarization layer, and the bonding pressure of the electrode under the driver IC or the Flexible Printed Circuit (FPC) and the pad may not be concentrated on the pad but may be diffused to other areas (planarization layer) than the pad, and insufficient pressure between the electrode under the driver IC or the Flexible Printed Circuit (FPC) and the pad may cause poor contact between the two and even fatal contact failure.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
To the problem in the prior art, the utility model aims to provide a TFT array substrate reaches display panel including it, TFT array substrate is through setting up the slot at the insulating layer to make the planarization layer can not cover first pad, reduce the difference in height of planarization layer and first pad, be used for display panel when this TFT array substrate, when encapsulating with circuit driver, can not arouse circuit driver and TFT array substrate's electric connection performance because the difference in height of planarization layer and pad.
Some embodiments of the utility model provide a TFT array substrate, include:
the circuit board comprises a first substrate and a circuit layer arranged on one side of the first substrate;
the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer and a planarization layer;
the first electrode layer comprises a plurality of first electrodes which are arranged on one side of the first substrate and are electrodes of the thin film transistor;
the insulating layer is arranged on one side, away from the first substrate, of the first electrode layer;
the first bonding pad layer comprises a plurality of first bonding pads and is arranged on one side of the insulating layer, which is far away from the first electrode layer;
the first pad is electrically connected with the first electrode through contact holes respectively penetrating through the insulating layer;
the planarization layer is arranged on one side, away from the first electrode layer, of the insulating layer;
the insulating layer is provided with a plurality of grooves, and the projection of each groove on the first substrate covers the projection of the edge of the first pad on the first substrate.
According to some examples of the invention, the depth of the groove is between 50nm and 500 nm.
According to some examples of the invention, the width of the groove is between 1um to 500 um.
According to some examples of the present invention, the TFT array substrate further comprises a polysilicon layer, the polysilicon layer comprising a plurality of polysilicon film blocks;
the projection of the groove on the first substrate falls into the projection of the polycrystalline silicon film block on the first substrate.
According to some examples of the invention, the polysilicon layer has a thickness between 20nm and 100 nm.
According to some examples of the present invention, the TFT array substrate further comprises a second electrode layer comprising a plurality of second electrodes;
the second electrode layer is arranged on one side, away from the first substrate, of the first electrode layer;
projection of the second electrode on the first substrate the projection of the first electrode on the first substrate overlaps;
the first electrode, the second electrode and the first pad are electrically connected to each other.
According to some examples of the invention, the thickness of the second electrode layer is between 200nm and 500 nm.
According to some examples of the present invention, the TFT array substrate further includes a functional layer including a plurality of functional blocks;
the projection of the functional block on the first substrate overlaps the projection of the first electrode on the first substrate;
the first pad is electrically connected to the first electrode through contact holes respectively penetrating the insulating layer and the functional block.
According to some examples of the invention, the functional layer has a thickness of between 200nm and 500 nm.
Other embodiments of the present invention further provide a display panel, including the above TFT array substrate.
According to some examples of the invention, the display panel further comprises a circuit driving device, the circuit driving device comprising:
a second substrate;
a driving circuit disposed at one side of the second substrate;
the second bonding pad layer comprises a plurality of second bonding pads and is arranged on the other side of the second substrate, and each second bonding pad is led out from one electrode of the driving circuit;
and the driving chip and the TFT array substrate are packaged through the anisotropic conductive film layer.
The utility model discloses TFT array substrate sets up the slot through the insulating layer at to make the planarization layer can not cover first pad, reduce the planarization layer and the difference in height that is used for the first pad of electricity to be connected, have the utility model discloses a TFT array substrate's display panel has reduced because the planarization layer among the TFT array substrate leads to the electrical contact failure with the difference in height of first pad, has greatly improved the electric connection performance of circuit driver spare with TFT array substrate, has ensured drive signal's reliability, has improved display panel's yield.
Drawings
Other features, objects, and advantages of the invention will be apparent from the following detailed description of non-limiting embodiments, which proceeds with reference to the accompanying drawings and which is incorporated in and constitutes a part of this specification, illustrating embodiments consistent with this application and together with the description serve to explain the principles of this application. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a TFT array substrate according to another embodiment of the present invention;
fig. 3 is a schematic structural diagram of a TFT array substrate according to still another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a TFT array substrate according to another embodiment of the present invention.
Reference numerals
100 first substrate
200 buffer layer
310 first electrode layer
320 second electrode layer
400 insulating layer
410 groove
420 polysilicon layer
500 first pad layer
600 planarization layer
700 anisotropic conductive film
710 conductive particles
800 second pad layer
900 second substrate
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.
Fig. 1 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention, specifically, the TFT array substrate includes:
a first substrate 100 and a circuit layer disposed on one side of the first substrate 100;
the circuit layer includes a first electrode layer 310, an insulating layer, a first pad layer, and a planarization layer;
the first electrode layer 310 includes a plurality of first electrodes disposed on one side of the first substrate 100, and the first electrodes are electrodes of thin film transistors;
preferably, as shown in the embodiment of fig. 1, a buffer layer 200 may be disposed between the first electrode layer 310 and the first substrate 100.
The insulating layer 400 is disposed on a side of the first electrode layer 310 facing away from the first substrate 100, and the insulating layer may include multiple dielectric layers, such as a first insulating layer and a second insulating layer formed by two dielectric layers.
The first pad layer 500 includes a plurality of first pads disposed on a side of the insulating layer 400 facing away from the first electrode layer 310;
it should be noted that, in fig. 1 to 4, a pad and a related structure on the first substrate are taken as examples, and the first pad is electrically connected to the first electrode through contact holes respectively penetrating through the insulating layer 400.
The planarization layer 600 is disposed on a side of the insulation layer 400 facing away from the first electrode layer 310;
the insulating layer 400 is provided with a plurality of grooves 410, and a projection of each groove 410 on the first substrate 100 covers a projection of an edge of the first pad on the first substrate 100.
The first electrode layer 310, the insulating layer 400, the first pad layer 500, and the like may all adopt a patterning process, and the patterning process may refer to a process including a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. Corresponding patterning processes may be selected according to the structures formed in the present invention.
The utility model discloses a TFT array substrate, when preparing the planarization layer, because its mobility, edge at first pad, owing to be provided with slot 410, the slot is filled to planarization layer 600, thereby reduce the cover to the edge of first pad, make the planarization layer of the edge of first pad highly be not more than first pad, the problem that the planarization layer is higher than the pad among the prior art has been solved promptly, be used for display panel when this TFT array substrate, when encapsulating with circuit driver, can not arouse circuit driver and TFT array substrate's electric connection performance because the difference in height of planarization layer and pad
In some embodiments, the depth of the trench 410 is between 50nm and 500nm, preferably, the depth of the trench 410 is 100nm, 200nm, or 400 nm; the width of the trench 410 is between 1um to 500um, as the width of the trench 410 can be 1um, 10um, 50um, 100um, 200um or 400 um. The depth and width of the trench can be set according to the thickness of the actual planarization layer, and the larger the thickness of the actual planarization layer, the larger the depth or width of the corresponding trench.
Since the trench is obtained by etching the insulating layer 400 using a patterning process, in order to prevent the etching process from affecting the buffer layer 200 under the insulating layer 400, the TFT array substrate further includes a polysilicon layer 420, as shown in fig. 2, the polysilicon layer 420 includes a plurality of polysilicon film blocks disposed at the bottom of the trench 410; before the insulating layer is deposited, a polysilicon film block is deposited in the corresponding area of the groove by adopting a composition process, so that the depth of the groove is limited, and the buffer layer can not be damaged by the preparation process of the groove.
The projection of the trench on the first substrate 100 falls into the projection of the poly-si film block on the first substrate 100, i.e. the poly-si film block is larger than the width of the trench 410.
In some embodiments, the polysilicon layer has a thickness between 20nm and 100 nm.
Other embodiments of the present invention further provide a display panel, including the above TFT array substrate.
According to some examples of the invention, the display panel further comprises a circuit driving device, the circuit driving device comprising:
a second substrate (900) is provided on the substrate,
a driving circuit disposed at one side of the second substrate 900;
a second pad layer 800 including a plurality of second pads disposed on the other side of the second substrate 900, each of the second pads being led out from an electrode of the driving circuit;
and an anisotropic conductive film layer 700 through which the driving chip and the TFT array substrate are packaged.
The material of the anisotropic conductive film layer may be a non-conductive material (epoxy resin, acrylate, etc.) mixed with the conductive particles 710 (conductive gold particles, conductive silver particles, etc.). The utility model discloses a second pad of circuit driver device and TFT array substrate's first pad realize the electricity through the conductive particle realization electricity of anisotropic conductive film layer and are connected.
The utility model discloses a circuit drive device can include power drive chip, TFT control chip, TFT line data driver chip etc..
The utility model discloses a first base plate and second base plate can be flexible, also can be rigid, and flexible base plate or apron can be the structure that has individual layer or multilayer flexible membrane, and the flexible membrane can adopt flexible substrate materials such as polyimide (polyimide, PI), polyethylene terephthalate (PET), polybutylene naphthalate (PBN) or polycarbonate, also can be materials such as metal foil. The multilayer structure may be a multilayer PI film, or a multilayer PET film, or a multilayer film structure having PI films and PET alternately stacked.
The utility model discloses a second pad of circuit driver and TFT array substrate's first pad is through exerting pressure to first base plate and second base plate, because the insulating layer at first pad edge is provided with slot 410, make the planarization layer of the edge of first pad highly be not more than first pad, at this moment, bonding pressure between first base plate and the second base plate can concentrate on first pad and second pad, reduced effectively between first pad and the second pad because the pressure is not enough can cause the bad or fatal electric contact failure even between the two. The utility model discloses a display panel has greatly improved the electric connection performance of circuit driver and TFT array substrate, has ensured drive signal's reliability, has improved display panel's yield.
In order to further improve the electrical connection performance of the first and second pads, i.e., the circuit driving devices, to the TFT array substrate, in some embodiments, the TFT array substrate may further include a second electrode layer 320 including a plurality of second electrodes, as shown in fig. 3; the second electrode layer 320 is disposed on a side of the first electrode layer 310 facing away from the first substrate 100; projection of the second electrode on the first substrate 100 the projection of the first electrode on the first substrate 100 overlaps; the first electrode, the second electrode and the first pad are electrically connected to each other. In this embodiment, the second electrode can effectively increase the thickness at the first electrode, thereby reducing the distance between the first pad and the second pad, increasing the bonding pressure between the two, and improving the electrical contact performance between the two.
Preferably, the thickness of the second electrode layer 320 is between 200nm and 500 nm.
In order to further improve the electrical connection performance between the first pad and the second pad, i.e., the circuit driving device, and the TFT array substrate, in other embodiments, the TFT array substrate may further include a functional layer 330 including a plurality of functional blocks; this functional layer 330 may be composed of a non-conductive material, and the projection of the functional block on the first substrate 100 overlaps the projection of the first electrode on the first substrate 100; the first pad is electrically connected to the first electrode through contact holes respectively penetrating the insulating layer 400 and the functional block. As such, the functional layer 330 may effectively increase the thickness at the first electrode, thereby reducing the distance between the first pad and the second pad, increasing the bonding pressure therebetween, and thus improving the electrical contact performance between the two.
In some embodiments, the functional layer 330 is between 200nm and 500nm thick.
The utility model discloses do not exclude the embodiment that has second electrode layer and functional layer simultaneously.
To sum up, the utility model provides a TFT array substrate reaches display panel including it, wherein, TFT array substrate sets up the slot through insulating layer 400 at to make the planarization layer can not cover first pad, reduce the planarization layer and be used for the difference in height of the first pad of electricity connection, have the utility model discloses a TFT array substrate's display panel has reduced because the planarization layer among the TFT array substrate leads to the electrical contact failure with the difference in height of first pad, has greatly improved the electric connection performance of circuit driver and TFT array substrate, has ensured drive signal's reliability, has improved display panel's yield.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the apparatus claims may also be implemented by one unit or means in software or hardware. It is to be understood that the terms "lower" or "upper", "downward" or "upward" and the like are used to describe features of the exemplary embodiments with reference to the positions of such features as displayed in the figures; the terms first, second, etc. are used to denote names, but not any particular order.
Claims (11)
1. A TFT array substrate, comprising:
the circuit board comprises a first substrate and a circuit layer arranged on one side of the first substrate;
the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer and a planarization layer;
the first electrode layer comprises a plurality of first electrodes which are arranged on one side of the first substrate and are electrodes of the thin film transistor;
the insulating layer is arranged on one side, away from the first substrate, of the first electrode layer;
the first bonding pad layer comprises a plurality of first bonding pads and is arranged on one side of the insulating layer, which is far away from the first electrode layer;
the first pad is electrically connected with the first electrode through contact holes respectively penetrating through the insulating layer;
the planarization layer is arranged on one side, away from the first electrode layer, of the insulating layer;
the insulating layer is provided with a plurality of grooves, and the projection of each groove on the first substrate covers the projection of the edge of the first pad on the first substrate.
2. The TFT array substrate of claim 1, wherein the trench has a depth of between 50nm and 500 nm.
3. The TFT array substrate of claim 1, wherein the trench has a width between 1um and 500 um.
4. The TFT array substrate of claim 1, further comprising a polysilicon layer comprising a plurality of polysilicon film blocks;
the projection of the groove on the first substrate falls into the projection of the polycrystalline silicon film block on the first substrate.
5. The TFT array substrate of claim 4, wherein the polysilicon layer has a thickness of between 20nm and 100 nm.
6. The TFT array substrate of claim 1, further comprising a second electrode layer comprising a plurality of second electrodes;
the second electrode layer is arranged on one side, away from the first substrate, of the first electrode layer;
projection of the second electrode on the first substrate the projection of the first electrode on the first substrate overlaps;
the first electrode, the second electrode and the first pad are electrically connected to each other.
7. The TFT array substrate of claim 6, wherein the second electrode layer has a thickness between 200nm and 500 nm.
8. The TFT array substrate of claim 1, further comprising a functional layer comprising a plurality of functional blocks;
the projection of the functional block on the first substrate overlaps the projection of the first electrode on the first substrate;
the first pad is electrically connected to the first electrode through contact holes respectively penetrating the insulating layer and the functional block.
9. The TFT array substrate of claim 8, wherein the functional layer has a thickness of between 200nm and 500 nm.
10. A display panel comprising the TFT array substrate according to any one of claims 1 to 9.
11. The display panel according to claim 10, further comprising a circuit driving device, the circuit driving device comprising:
a second substrate;
a driving circuit disposed at one side of the second substrate;
the second bonding pad layer comprises a plurality of second bonding pads and is arranged on the other side of the second substrate, and each second bonding pad is led out from one electrode of the driving circuit;
and the second bonding pad of the circuit driving device and the first bonding pad of the TFT array substrate are electrically connected through the conductive particles of the anisotropic conductive film layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022837227.5U CN213483274U (en) | 2020-12-01 | 2020-12-01 | TFT array substrate and display panel comprising same |
| US17/524,295 US11978743B2 (en) | 2020-12-01 | 2021-11-11 | TFT array substrate and display panel including the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022837227.5U CN213483274U (en) | 2020-12-01 | 2020-12-01 | TFT array substrate and display panel comprising same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582221A (en) * | 2020-12-01 | 2022-06-03 | 上海和辉光电股份有限公司 | TFT array substrate and display panel comprising same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582221A (en) * | 2020-12-01 | 2022-06-03 | 上海和辉光电股份有限公司 | TFT array substrate and display panel comprising same |
| CN114582221B (en) * | 2020-12-01 | 2024-08-23 | 上海和辉光电股份有限公司 | TFT array substrate and display panel comprising same |
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