CN115497880A

CN115497880A - Preparation method of array substrate and display panel

Info

Publication number: CN115497880A
Application number: CN202211142696.2A
Authority: CN
Inventors: 蒲洋; 康报虹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-09-20
Filing date: 2022-09-20
Publication date: 2022-12-20

Abstract

The application belongs to the technical field of display, and particularly relates to a preparation method of an array substrate and a display panel, wherein the preparation method of the array substrate comprises the following steps: providing a substrate base plate, wherein the substrate base plate comprises a display area and a binding area; sequentially forming a driving layer and a planarization layer in the display area, wherein the driving layer comprises a plurality of transistors, the planarization layer is provided with through holes exposing a first pole of the transistors, and the first pole is a source electrode or a drain electrode; sequentially forming a binding pin and a protective layer wrapping the binding pin in the binding region; after the protective layer is formed, an anode is formed on the planarization layer of the display region, and the anode is connected to the first electrode of the transistor through the via hole. According to the scheme, the protective layer which completely covers the bound pins is formed in the binding area, so that the bound pins can be protected from reacting with etching liquid in the anode etching process, adjacent bound pins are guaranteed to be disconnected from each other, short circuit between adjacent bound pins is avoided, and the display effect of the display panel is guaranteed.

Description

Preparation method of array substrate and display panel

Technical Field

The application belongs to the technical field of display, and particularly relates to a preparation method of an array substrate and a display panel.

Background

In recent years, organic Light-Emitting Diode (OLED) displays have been receiving attention from the industry due to their excellent performance. Compared with a liquid crystal Display (LCD for short) which currently occupies a major market, the OLED Display has a series of advantages of light weight, small thickness, low power consumption, bright color, fast response speed, wide viewing angle, capability of realizing soft Display and the like.

Bonding is an important step in the process of manufacturing an OLED display, and refers to a process of connecting and conducting Bonding pins in a Bonding region of an OLED Panel (Panel) and a driver Integrated Circuit (IC), a Flexible Printed Circuit (FPC) or a touch control (touch) IC according to a certain work flow in the production process of the OLED display. However, in the anodic etching process, metal ions in the etching solution are easily replaced by metal and gather between adjacent binding pins, so that short circuit occurs between the binding pins, and abnormal display is caused.

Disclosure of Invention

The application aims to provide a preparation method of an array substrate and a display panel, which can protect a binding pin in an anode etching process, ensure normal work of the binding pin and improve display effect.

The application provides a preparation method of an array substrate in a first aspect, which comprises the following steps:

providing a substrate base plate, wherein the substrate base plate comprises a display area and a binding area;

sequentially forming a driving layer and a planarization layer in the display area, wherein the driving layer comprises a plurality of transistors, the planarization layer is provided with through holes exposing first poles of the transistors, and the first poles are source electrodes or drain electrodes;

sequentially forming a binding pin and a protective layer wrapping the binding pin in the binding region;

after forming the protective layer, an anode is formed on the planarization layer of the display region, the anode being connected to the first electrode of the transistor through the via hole.

In an exemplary embodiment of the present application, after forming an anode on the planarization layer of the display region, the method of manufacturing the array substrate further includes:

and removing the protective layer on the binding pins to expose the binding pins.

In an exemplary embodiment of the present application, the protection layer includes a first protection layer, wherein the first protection layer covering the bonding pins is formed within the bonding region before the planarization layer is formed in the display region.

In an exemplary embodiment of the present application, the first protective layer wraps the binding pins.

In one exemplary embodiment of the present application, the first protective layer includes:

the top protection part is positioned on one side of the binding pins, which is far away from the substrate base plate;

the side protection part is formed on the driving layer and arranged around the binding pins, the side protection part is connected with the top protection part, and the surface, far away from the substrate base plate, of the side protection part is lower than the surface, far away from the substrate base plate, of the top protection part.

In an exemplary embodiment of the present application, the bonding pins are provided in plurality and spaced apart from each other;

the first protection layer is made of gallium nitride, the first protection layer is arranged in a plurality of adjacent protection layers, the first protection layer and the adjacent protection layers are mutually disconnected, and the first protection layer and the binding pins are arranged in a one-to-one correspondence mode.

In an exemplary embodiment of the present application, the protective layer further includes a second protective layer, which is different from the first protective layer in material, wherein,

after forming the first protective layer, forming the second protective layer within the bonding region, the second protective layer wrapping at least the top protective portion.

In one exemplary embodiment of the present application, an orthogonal projection of the second protective layer on the underlying base is located within an orthogonal projection of the first protective layer on the underlying base such that a side surface of the side protective portion is exposed.

In an exemplary embodiment of the present application, the second protective layer and the planarization layer are disposed in the same layer and spaced apart from each other; and/or

The binding pin and the source electrode and the drain electrode of the transistor are arranged on the same layer; and/or

The anode is of an indium tin oxide, silver or indium tin oxide sandwich structure.

In a second aspect, the present application provides a display panel, which includes a cathode, a light-emitting layer, and the array substrate manufactured by the manufacturing method described in any one of the above, where the light-emitting layer is disposed between the cathode and the anode.

The scheme of the application has the following beneficial effects:

according to the preparation method of the array substrate, the protection layer which completely covers the binding pins is formed in the binding area, so that the binding pins can be protected from reacting with etching liquid in the anodic etching process, the etching liquid is prevented from separating out metal between adjacent binding pins, the adjacent pins are guaranteed to be disconnected with each other, and the adjacent binding pins are prevented from being connected to generate short circuit; in addition, this application scheme still includes display panel, can avoid effectively binding the short circuit that takes place between the pin through the protective layer, guarantees to bind the normal work of pin to guarantee display panel's display effect.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a substrate base plate according to a first embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a process for forming a source, a drain and a bonding pin according to an embodiment of the present application;

fig. 4 is a schematic structural diagram illustrating a buffer layer provided in an embodiment of the present application and disposed on the substrate;

fig. 5 is a schematic structural diagram illustrating an active layer disposed on a buffer layer according to an embodiment of the present application;

fig. 6 is a schematic structural diagram illustrating a gate insulating layer disposed on a buffer layer according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram illustrating a gate electrode disposed on a gate insulating layer according to an embodiment of the present application;

fig. 8 is a schematic structural diagram illustrating a first insulating layer formed on a gate insulating layer according to a first embodiment of the present application;

FIG. 9 is a schematic diagram illustrating a first recessed hole and a second recessed hole formed therein according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram illustrating the formation of a source, a drain and a bonding pin according to an embodiment of the present application;

fig. 11 is a schematic diagram illustrating a flow structure for forming a protection layer according to an embodiment of the present application;

fig. 12 is a schematic structural diagram illustrating a first protection layer formed on a bonding pin according to an embodiment of the present application;

fig. 13 is a schematic structural diagram illustrating a planarization layer formed in a display region and a binding region according to the first embodiment or the second embodiment of the present application;

fig. 14 is a schematic structural view illustrating formation of an anode on a display region according to the first embodiment or the second embodiment of the present application;

FIG. 15 is a schematic diagram illustrating a process for removing a protection layer according to an embodiment of the present application;

FIG. 16 is a schematic diagram illustrating a structure for removing a protection layer according to a first embodiment of the present application;

FIG. 17 is a schematic structural diagram of a display area and a binding area according to an embodiment of the present application;

fig. 18 shows a schematic structural diagram of a cathode, a light-emitting layer, and an anode provided in example two of the present application.

Description of reference numerals:

10. an array substrate; 10a, a via hole; 10b, a first groove hole; 10c, a second groove hole; 101. a substrate base plate; 101a, a display area; 101b, a binding area; 102. a planarization layer; 1031. a source electrode; 1032. a drain electrode; 104. a buffer layer; 105. an active layer; 106. a gate insulating layer; 107. a gate electrode; 108. a first insulating layer; 109. binding pins; 110. a protective layer; 1101. a first protective layer; 1102. a second protective layer; 20. an anode; 30. a cathode; 40. and a light emitting layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

In the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral parts thereof; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

Example one

An embodiment of the present application provides a method for manufacturing an array substrate 10, as shown in fig. 1, which includes the following steps:

step S100: referring to fig. 2, a base substrate 101 is provided, the base substrate 101 including a display region 101a and a binding region 101b.

For example, the shape of the base substrate 101 may be circular, square, or oval, and the like, and the shape is not particularly limited; the base substrate 101 may be made of organic glass, resin, quartz, metal, or the like, and the material thereof is not particularly limited.

Step S200: a driving layer including a plurality of transistors and a planarization layer 102 having a via hole 10a exposing a first electrode of the transistor, which is a source electrode 1031 or a drain electrode 1032, are sequentially formed in the display region 101 a.

The driving layer comprises a plurality of transistors arranged in an array, each transistor comprises a first pole and a second pole, and the first pole and the second pole are arranged at intervals and are in lap joint with the active layer 105; for example, the first pole may be the drain 1032, the second pole may be the source 1031; of course, in different embodiments, the first pole may also be the source 1031, and the second pole may be the drain 1032.

In the present embodiment, the first pole represents the drain 1032, and the second pole represents the source 1031.

Specifically, the step of sequentially forming the transistors in the display region 101a includes the following steps, as shown in fig. 3:

in step S201, referring to fig. 4, a buffer layer 104 is formed on the substrate 101 in the display region 101a and the bonding region 101b, and the buffer layer 104 may be made of silicon nitride (SiNx) or silicon oxide (SiOx).

Step S202, referring to fig. 5, forming an active layer 105 on the buffer layer 104 of the display region 101 a; the active layer 105 is made of polycrystalline silicon (Poly-Si);

step S203, referring to fig. 6, a gate insulating layer 106 is formed on the buffer layer 104 in the display region 101a and the binding region 101b, and the gate insulating layer 106 completely covers the active layer 105; the gate insulating layer 106 is made of silicon nitride (SiNx), silicon oxide (SiOx), or the like.

In step S204, referring to fig. 7, a gate electrode 107 is formed on the gate insulating layer 106 of the display region 101 a.

Illustratively, a first metal layer is coated on the gate insulating layer 106 and patterned (e.g., irradiated and etched) to form a gate electrode 107 on the gate insulating layer 106, wherein the gate electrode 107 is used for controlling the transistor to be turned on and off. The first metal layer may be made of a metal material such as aluminum (Al), copper (Cu), molybdenum (Mo), or the like.

Step S205, referring to fig. 8, forming a first insulating layer 108 on the gate insulating layer 106 of the display region 101a and the binding region 101b, and the first insulating layer 108 located in the display region 101a completely covers the gate electrode 107; the first insulating layer 108 may be made of the same material as the gate insulating layer 106, such as, but not limited to, silicon nitride (SiNx) and silicon oxide (SiOx).

Step S206, referring to fig. 9, of patterning the first insulating layer 108 and the gate insulating layer 106 in the display region 101a to form a first recess hole 10b and a second recess hole 10c to expose a portion of the active layer 105;

illustratively, the first insulating layer 108 and the gate insulating layer 106 are subjected to light irradiation and etching patterning processes to form a first groove hole 10b and a second groove hole 10c, which respectively expose portions of the active layer 105, at both left and right sides of the gate electrode 107.

Step S207, referring to fig. 10, coats a second metal layer in the display area 101a, and performs patterning (illumination and etching) on the second metal layer to form a corresponding pattern.

Illustratively, when a second metal layer is coated in the display region 101a, the metal in the second metal layer flows into the first recess hole 10b and the second recess hole 10c, overlaps the active layer 105, and forms the source 1031 and the drain 1032 of the transistor through a patterning process.

The second metal layer may have a titanium (Ti)/aluminum (Al)/titanium (Ti) sandwich structure, in which Al is easily oxidized and Ti is not easily oxidized, so that addition of Ti on both sides of Al can prevent oxidation of Al.

It is worth mentioning that the transistor in the embodiment of the present application is of a top gate type; although a bottom gate type may be used in other embodiments. It is understood that the gate electrode 107 is positioned below the active layer 105 when the bottom gate type is employed.

In step S300, referring to fig. 1 and 10, a bonding pin 109 and a protection layer 110 wrapping the bonding pin 109 are sequentially formed in the bonding region 101b.

Illustratively, a plurality of bonding pins 109 which are not adjacent to each other are obtained through patterning the second metal layer in the process of step S207, that is, the bonding pins 109 are disposed on the same layer as the source 1031 and the drain 1032 of the transistor; one end of the bonding pin 109 is used for connecting and conducting with a pin of a driver integrated circuit (AI for short) through an anisotropic conductive adhesive, and the other end is used for connecting signal lines such as a data line (Date) and a scan line (Gate).

The term "layer-by-layer arrangement" refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then performing a patterning process once using the same mask plate. That is, one mask (also called as a photomask) is corresponding to one patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. Thereby simplifying the manufacturing process, saving the manufacturing cost and improving the production efficiency.

In addition, a protective layer 110 is formed on the first insulating layer 108, and the protective layer 110 wraps the bonding pins 109, so as to prevent oxidation-reduction reaction between the etching solution of the anode 20 and the bonding pins 109 from replacing metal, ensure mutual disconnection between adjacent bonding pins 109, ensure no short circuit between the bonding pins 109, and further ensure a normal information transmission function of the bonding pins 109.

It is worth mentioning that the protection layer 110 in the bonding region 101b may be formed before the anode 20 is formed on the planarization layer 102 in the display region 101a, so as to better protect the bonding pins 109.

In addition, the protective layer 110 may have one or more layers, so as to protect the bonding pin 109 well, and prevent the etching solution from reacting.

When the protective layer 110 has a one-layer structure, the protective layer 110 wraps and binds the pins 109, and the protective layer 110 is made of a material that does not react with the etching solution of the anode 20, which may be specifically designed according to different embodiments.

When the protective layer 110 has a two-layer structure, it may be specifically implemented as follows:

illustratively, the protection layer 110 in the bonding region 101b includes a first protection layer 1101 and a second protection layer 1102, and forming the protection layer 110 in the bonding region 101b includes the steps of:

in step S301, referring to fig. 11 and 12, a first protection layer 1101 wrapping the bonding pins 109 is formed on the first insulating layer 108.

Alternatively, the first insulating layer 108 is coated with a Metal Organic Chemical Vapor Deposition (MOCVD), and patterned by photolithography and etching to form a first protection layer 1101 that surrounds the bonding pins 109.

In step S302, referring to fig. 13, after the first protection layer 1101 is formed, a second protection layer 1102 is formed in the bonding region 101b, and the second protection layer 1102 wraps at least the top protection portion.

Note that the first protective layer 1101 and the second protective layer 1102 are made of different materials; illustratively, the first protection layer 1101 employs gallium nitride (GaN).

In addition, the second protection layer 1102 in the binding region 101b and the second protection layer 1102 in the display region 101a may be disposed in the same layer, that is, the second protection layer 1102 is made of the same material as the planarization layer 102, and the disposition of the same layer is the same as the above description, which is not repeated herein.

It is to be understood that the second protection layer 1102 in the binding region 101b is formed by the same mask process (light irradiation and etching formation) as the planarization layer 102 in the display region 101 a.

In this way, the first protection layer 1101 wraps the outside of the bonding pins 109, so that the bonding pins 109 can be well prevented from reacting with the etching solution of the anode 20, thereby avoiding short circuit between the bonding pins 109 and ensuring the signal transmission efficiency of the bonding pins 109. In addition, the first protection layer 1101 can be protected by the second protection layer 1102, so that the first protection layer 1101 is prevented from being etched by the etching solution of the anode 20, and thus the bonding pins 109 can be better protected. In addition, by fabricating the planarization layer 102 and the second protection layer 1102, the process is reduced, and the manufacturing cost is reduced.

It should be noted that, referring to fig. 12, the first protection layer 1101 and the second protection layer 1102 are disposed in one-to-one correspondence with the bonding pins 109; and the longitudinal cross-section of first protective layer 1101 over bonding pins 109 can be arch-bridge shaped or step-shaped.

Illustratively, the longitudinal section of the first protection layer 1101 is stepped, and the first protection layer 1101 includes a top protection portion (not shown in the figure) and a side protection portion (not shown in the figure); two sides of the first protection layer 1101 are side protection portions, and the middle portion is a top protection portion, that is, the top protection portion is located on one side of the bonding pin 109 away from the base substrate 101, the side protection portions are formed on the driving layer and are arranged around the bonding pin 109, and the surface of the side protection portion away from the base substrate 101 is lower than the surface of the top protection portion away from the base substrate 101.

In this way, the first protection layer 1101 has a step-shaped structure, so that the coverage width of the bottom of the first protection layer 1101 can be increased, and the etching liquid of the anode 20 can be prevented from etching the first protection layer 1101, thereby preventing the bonding pins 109 from leaking out, and better protecting the bonding pins 109.

It should be noted that the side protection part and the top protection part are connected and integrally formed to better protect the bonding pin 109.

In addition, the second protection layer 1102 may partially wrap the top protection portion or completely wrap the top protection portion, and two ends of the second protection layer 1102 are respectively overlapped on the side protection portions at two sides. The second protective layer 1102 may overlap with the edge position of the side protective portion, or the orthographic projection of the second protective layer 1102 on the base substrate 101 may be smaller than the orthographic projection of the first protective layer 1101 on the base substrate 101, that is, the second protective layer 1102 may not overlap with the edge position of the side protective portion.

It is understood that, referring to fig. 13, the orthographic projection of the second protection layer 1102 on the base substrate 101 is smaller than the orthographic projection of the first protection layer 1101 on the base substrate 101, and the second protection layer 1102 can be prevented from directly contacting the first insulating layer 108, so that the second protection layer 1102 in the bonding region 101b can be more conveniently peeled off.

In step S400, referring to fig. 1 and 14, after the protective layer 110 is formed, an anode 20 is formed on the planarization layer 102 of the display region 101a, and the anode 20 is connected to the first electrode of the transistor through the via hole 10 a.

Illustratively, a film is formed on the planarization layer 102 by a physical vapor deposition method (PVD), and the anode 20 is formed by photolithography and wet etching; the anode 20 may be an ITO (indium tin oxide), ag (silver), ITO (indium tin oxide) sandwich structure, ag (silver) is easily oxidized, and ITO (indium tin oxide) is added on the upper and lower sides of Ag for protection, thereby effectively preventing oxidation of Ag.

It can be understood that, in the wet etching process of the anode 20, the binding pin 109 can prevent aluminum (Al) from being exposed in the etching solution due to the protection of the protective layer 110, so that the aluminum (Al) does not provide electrons to the etching solution, and Ag + (silver ions) in the etching solution of the anode 20 can be prevented from acting on the aluminum in the binding pin 109 to generate silver (Ag) precipitation.

Further, referring to fig. 15, the method for manufacturing the array substrate 10 further includes the following steps:

in step S500, referring to fig. 16 and 17, the protection layer 110 on the bonding pins 109 is removed, so that the bonding pins 109 are exposed.

Illustratively, the first protective layer 1101 is irradiated with a 266nm/248nm laser, and the first and second

protective layers

1101 and 1102 on the bonding pins 109 are removed to expose the bonding pins 109 for bonding with the driving integrated circuit.

The first protection layer 1101 may be made of a material that is easily decomposed by laser, such as gallium nitride (GaN), gallium oxide (GaO), and the like; therefore, the protective layer 110 on the binding pin 109 can be better removed, the removal is more convenient and convenient, the binding pin 109 is not easy to damage, and the transmission of information is ensured.

It is understood that when the first protective layer 1101 is irradiated with laser light, the first protective layer 1101 and the second protective layer 1102 on the bonding pins 109 are simultaneously peeled off. Therefore, one process can be saved, and the production and manufacturing cost can be saved.

In addition, gallium nitride (GaN) or gallium oxide (GaO) forms conductive metal gallium after being decomposed by laser, and short circuit occurs between adjacent bonding pins 109 when cleaning is incomplete; therefore, in order to avoid short-circuiting between the bonding pins 109 caused by residual gallium metal, the first and second

protective layers

1101 and 1102 on each bonding pin 109 are disconnected from each other.

In addition to the laser irradiation for removing the protection layer 110, the first protection layer 1101 may be removed by laser irradiation after the second protection layer 1102 on the first protection layer 1101 is removed by exposure and development. In this way, when the second protection layer 1102 is removed, the bonding pins 109 can be protected by the first protection layer 1101, and the bonding pins 109 can be prevented from being damaged.

Note that the protective layer 110 has two structures, namely, a first protective layer 1101 and a second protective layer 1102, which are mainly based on: if only the second protection layer 1102 or other materials are used for protection, the cured second protection layer 1102 or other materials cannot be removed directly by a developing method, and need to be removed by photoresist coating, exposure, and dry etching, and the dry etching method has low selectivity, so that the difficulty in removing the second protection layer 1102 or other materials at the bonding position is high, and the bonding pin 109 is damaged to some extent when the second protection layer 1102 or other materials at the bonding position are removed by dry etching. If only the first protection layer 1101 is used, the etching solution may partially etch the first protection layer 1101, so that the bonding pins 109 are exposed, and the bonding pins 109 are shorted. Therefore, based on the above two considerations, the embodiment of the present application protects the bonding pins 109 by combining the first protection layer 1101 and the second protection layer 1102.

In addition, after the first protection layer 1101 and the second protection layer 1102 are removed by laser irradiation, the protection layer 110 remaining on the bonding pins 109 is removed by cleaning, so as to avoid affecting the normal operation of the bonding pins 109.

It should be noted that, in this embodiment, the array substrate 10 adopts a low-temperature polysilicon LTPS-TFT driving backplane; of course, in different embodiments, the array substrate 10 may also adopt other driving back plates, and the preparation method thereof is the same as that of the embodiment of the present application and is not described herein again.

Example two

A second embodiment of the present application provides a display panel, which is an Organic Light-Emitting Diode (OLED) display panel; the organic light emitting diode display panel is in a top emission mode.

Referring to fig. 18, the organic light emitting diode display panel includes a cathode 30, a light emitting layer 40 and the array substrate 10 manufactured by the manufacturing method in the first embodiment, wherein the light emitting layer 40 is located between the cathode 30 and the anode 20; under the driving of an external voltage, electrons injected from the cathode 30 and holes injected from the two anodes 20 are combined in the light emitting layer 40 to form electron-hole pairs at a bound energy level, i.e., excitons, which are excited by radiation to emit photons, thereby generating visible light, and the display panel can further realize display.

As shown in fig. 13 and 14, the protective layer 110 is formed between the anodes 20, so as to protect the bonding pins 109 in the bonding region 101b, prevent short circuit between the bonding pins 109, ensure normal transmission of the bonding pins 109, ensure normal generation of holes in the anodes 20, further ensure normal generation of visible light in the light emitting layer 40, and ensure display effect of the display panel.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present application have been shown and described, it is understood that the above embodiments are illustrative and should not be construed as limiting the present application and that various changes, modifications, substitutions and alterations can be made therein by those skilled in the art within the scope of the present application, and therefore all changes and modifications that come within the meaning of the claims and the description of the invention are to be embraced therein.

Claims

1. A preparation method of an array substrate is characterized by comprising the following steps:

2. The method of claim 1, wherein after forming an anode on the planarization layer of the display region, the method further comprises:

3. The method for manufacturing an array substrate of claim 1, wherein the protection layer comprises a first protection layer, and wherein the first protection layer covering the bonding pins is formed in the bonding region before the planarization layer is formed in the display region.

4. The method for manufacturing the array substrate according to claim 3, wherein the first protective layer covers the bonding pins.

5. The method for preparing the array substrate of claim 4, wherein the first protective layer comprises:

6. The method for manufacturing the array substrate according to claim 5, wherein the bonding pins are arranged in a plurality and spaced from each other;

7. The method of claim 5, wherein the passivation layer further comprises a second passivation layer, the second passivation layer is made of a different material than the first passivation layer, wherein,

8. The method for manufacturing an array substrate according to claim 7, wherein an orthogonal projection of the second protective layer on the underlying substrate is located within an orthogonal projection of the first protective layer on the underlying substrate, so that a side surface of the side protective portion is exposed.

9. The method for manufacturing the array substrate according to claim 7, wherein the second protection layer and the planarization layer are disposed in the same layer and spaced apart from each other; and/or

10. A display panel comprising a cathode, a light-emitting layer and an array substrate manufactured by the method according to any one of claims 1 to 9, wherein the light-emitting layer is disposed between the cathode and the anode.