CN110890323A - Source-drain layer lead structure, preparation method thereof, array substrate and display panel - Google Patents
Source-drain layer lead structure, preparation method thereof, array substrate and display panel Download PDFInfo
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- CN110890323A CN110890323A CN201911184156.9A CN201911184156A CN110890323A CN 110890323 A CN110890323 A CN 110890323A CN 201911184156 A CN201911184156 A CN 201911184156A CN 110890323 A CN110890323 A CN 110890323A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
The disclosure provides a source-drain layer lead structure, a preparation method thereof, an array substrate and a display panel, and belongs to the technical field of display. The source drain layer lead structure is formed on one side of a substrate; the source drain layer lead structure comprises a first metal layer and a second metal layer, wherein the first metal layer is arranged on one side of the substrate; the second metal layer covers the side face of the first metal layer and the surface of the first metal layer far away from the substrate; the second metal layer has higher tolerance to acidic etching liquid than the first metal layer. The source drain layer lead structure provided by the disclosure can improve the yield of the display panel.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to a source-drain layer lead structure, a preparation method thereof, an array substrate and a display panel.
Background
Organic light emitting display devices (OLEDs) have the advantages of self-luminescence, wide color gamut, high contrast, low power consumption, thinness, foldability, etc., and are considered to be the most promising display technology in the future. In the process of fabricating the organic light emitting display device, Dark spots and continuously increasing Dark spots (GDS) are important defects in the panel and module stages, respectively, which limits the yield improvement of the organic light emitting display device.
The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a source/drain layer lead structure, a method for manufacturing the same, an array substrate and a display panel, which improve the yield of the display panel.
In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:
according to a first aspect of the present disclosure, a source/drain layer lead structure is provided, which is formed on one side of a substrate; the source drain layer lead structure comprises:
the first metal layer is arranged on one side of the substrate base plate;
the second metal layer covers the side face of the first metal layer and the surface of the first metal layer, which is far away from the substrate base plate;
the second metal layer has higher tolerance to acidic etching liquid than the first metal layer.
In an exemplary embodiment of the present disclosure, the acidic etching solution includes nitric acid and silver nitrate.
In one exemplary embodiment of the present disclosure, the material of the first metal layer includes aluminum or copper; and/or the material of the second metal layer is titanium or molybdenum.
In an exemplary embodiment of the present disclosure, the source drain layer lead structure further includes:
the third metal layer is arranged between the first metal layer and the substrate base plate; the third metal layer has higher tolerance to acidic etching solution than the first metal layer.
According to a second aspect of the present disclosure, there is provided an array substrate including:
a substrate base plate;
the driving circuit layer is arranged on one side of the substrate and is provided with a source drain layer lead, and the source drain layer lead adopts the source drain layer lead structure;
and the pixel electrode layer is arranged on one side of the driving circuit layer, which is far away from the substrate base plate.
In one exemplary embodiment of the present disclosure, the pixel electrode layer includes silver.
According to a third aspect of the present disclosure, a display panel is provided, which includes the array substrate.
According to a fourth aspect of the present disclosure, a method for manufacturing a source/drain layer lead structure is provided, including:
forming a first metal layer on one side of a substrate;
forming a second metal layer on one side of the first metal layer, which is far away from the substrate base plate, and enabling the second metal layer to cover the side face of the first metal layer and the surface of the first metal layer, which is far away from the substrate base plate; the second metal layer has higher tolerance to acidic etching liquid than the first metal layer.
In one exemplary embodiment of the present disclosure, the first metal layer includes aluminum or copper; the second metal layer is made of titanium or molybdenum.
In an exemplary embodiment of the present disclosure, the acidic etching liquid includes nitric acid and silver nitrate.
In the source-drain layer lead structure, the manufacturing method thereof, the array substrate and the display panel, the surface and the side surface of the first metal layer are covered by the second metal layer, and the second metal layer can better resist the corrosion of the acidic etching liquid, so that the first metal layer can be prevented from being corroded by the acidic etching liquid, and the yield of the array substrate using the source-drain layer lead structure can be improved.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a schematic diagram of a process in which a source-drain layer lead is corroded by an etching solution in the related art.
Fig. 2 is a schematic structural diagram of a source/drain layer lead structure according to an embodiment of the disclosure.
Fig. 3 is a schematic structural diagram of forming a first metallic material layer according to an embodiment of the disclosure.
Fig. 4 is a schematic structural diagram of patterning a first metallic material layer according to an embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of forming a second metallic material layer according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of exposing the second photoresist layer by using a second mask according to the embodiment of the disclosure.
Fig. 7 is a schematic structural diagram of developing the second photoresist layer according to an embodiment of the present disclosure.
Fig. 8 is a schematic structural diagram of exposing the second photoresist layer by using the first mask according to the embodiment of the disclosure.
Fig. 9 is a schematic structural diagram of a source/drain layer lead structure according to an embodiment of the disclosure.
Fig. 10 is a schematic structural diagram of forming a first metallic material layer according to an embodiment of the present disclosure.
Fig. 11 is a schematic structural diagram of patterning a first metallic material layer according to an embodiment of the present disclosure.
Fig. 12 is a schematic structural diagram of forming a second metallic material layer according to an embodiment of the present disclosure.
Fig. 13 is a schematic structural diagram of exposing the second photoresist layer by using a second mask according to the embodiment of the disclosure.
Fig. 14 is a schematic structural view of developing the second photoresist layer according to an embodiment of the present disclosure.
Fig. 15 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure.
Fig. 16 is a schematic flow chart of a manufacturing method of a source-drain layer lead structure according to an embodiment of the present disclosure.
The reference numerals of the main elements in the figures are explained as follows:
110. a first metal layer; 111. a first metal material layer; 120. a second metal layer; 121. a second metal material layer; 130. a third metal layer; 131. a third metal material layer; 140. a fourth metal layer; 141. a fourth metallic material layer; 200. a substrate base plate; 301. a buffer layer; 302. an active layer; 303. a first gate insulating layer; 304. a first gate layer; 305. a second gate insulating layer; 306. a second gate layer; 307. an interlayer dielectric layer; 308. a source drain metal layer; 309. a planarization layer; 401. a pixel electrode layer; 402. a pixel defining layer; 403. an organic light emitting layer; 404. a common electrode layer; 405. a silicon oxynitride layer; 406. an organic protective layer; 407. an inorganic protective layer; 501. a second photoresist layer; 502. a first mask plate; 503. and a second mask plate.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.
In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.
When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.
In the related art, as shown in fig. 1, the source/drain layer lead may adopt a sandwich structure of a titanium layer 901, an aluminum layer 902, and a titanium layer 903, and the pixel electrode layer may include silver; however, in the subsequent process of patterning the pixel electrode layer, the aluminum layer 902 of the source/drain layer leads in the peripheral region may be corroded by the etching solution. The side corrosion of the aluminum layer 902 will reduce the encapsulation effect of the encapsulation layer, and will easily form water and oxygen channels to generate GDS (continuously increasing dark spots). The suspended titanium layer 903 is prone to drop to form a titanium line, which causes a short circuit between the source and drain layer leads. Moreover, the etching liquid generates silver nitrate when etching silver, silver nitrate reacts with aluminum to generate silver particles, and the silver particles easily fall onto the pixel electrode along with the movement of the liquid, so that short circuit is easily caused between the pixel electrode and the common electrode layer of the array substrate, and the OLED device fails to work and generates dark spots.
In the related art, various attempts have been made to improve the problem of corrosion of the aluminum layer by the etching solution. In one attempt, a planarization layer of the array substrate may be formed using a half exposure process such that the planarization layer exposes surfaces of the source and drain layer leads of the peripheral region and covers sides of the source and drain layer leads of the peripheral region. However, it is difficult to accurately control the exposure amount, and if the exposure amount is too large, the side surface of the aluminum layer is exposed, and if the exposure amount is too small, the surface of the source/drain layer lead cannot be effectively exposed. In another attempt, a passivation layer (PVX) may be formed on a side of the source-drain layer leads away from the substrate, the passivation layer exposing a surface of the source-drain layer leads of the peripheral region and covering a side surface thereof, wherein the passivation layer may be silicon nitride. However, dry etching is required for patterning the passivation layer, the concentration and energy of etching ion gas need to be controlled very precisely in the etching process, if the etching amount is too low, the surface of the source/drain layer lead in the peripheral region is not sufficiently exposed, and if the etching amount is too large, the titanium layer on the surface is easily etched to expose the aluminum layer. These attempts have made it difficult to efficiently improve the corrosion of the aluminum layer by the etching liquid.
In the embodiment of the present disclosure, a source/drain layer lead structure is provided, as shown in fig. 2 and 9, the source/drain layer lead structure is formed on one side of a substrate 200; further, the source/drain layer lead structure may be formed on the side of the interlayer dielectric layer 307 of the array substrate away from the substrate 200. The source drain layer lead structure includes a first metal layer 110 and a second metal layer 120, wherein,
the first metal layer 110 is disposed on one side of the substrate base 200; the second metal layer 120 covers the side of the first metal layer 110 and the surface of the first metal layer 110 away from the substrate 200; the second metal layer 120 has a greater resistance to the acidic etchant than the first metal layer 110.
According to the source-drain layer lead structure, the surface and the side face of the source-drain layer lead structure are both the second metal layer 120, so that the corrosion of acidic etching liquid can be better resisted, the first metal layer 110 is prevented from being exposed and corroded by the acidic etching liquid, and the yield of the array substrate using the source-drain layer lead structure can be improved.
Each component of the array substrate provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings:
in the embodiment of the present disclosure, as shown in fig. 2 and 9, the first metal layer 110 includes a first surface close to the substrate base 200, a second surface far from the substrate, and a side surface connecting the first surface and the second surface. The first surface of the first metal layer 110 is protected by other film structures supporting the first metal layer 110 due to the side close to the substrate 200, and therefore, will not contact with the etching solution in the subsequent process. The second metal layer 120 covers the second surface and the side surface of the first metal layer 110, so that the first metal layer 110 can be prevented from being corroded, and various defects caused by corrosion of the first metal layer 110 can be avoided.
The first metal layer 110 may be a metal with good conductivity, so as to improve the conductivity of the source/drain layer lead structure and reduce the sheet resistance of the source/drain layer lead structure. The first metal layer 110 may also be made of a metal with a lower cost, so as to reduce the material cost of the source/drain layer lead structure. Alternatively, the material of the first metal layer 110 may include aluminum or copper, which may be a simple metal or an alloy. In one embodiment of the present disclosure, the material of the first metal layer 110 is aluminum.
The second metal layer 120 may be made of a metal capable of withstanding an acidic etching solution, and particularly, may be made of a metal capable of withstanding an etching solution used in patterning a pixel electrode layer of the array substrate. It is understood that the second electrode layer can withstand the etching liquid, which means that it can withstand the etching liquid under normal use conditions. For example, the material of the second metal layer 120 is not corroded by the etching solution when the pixel electrode layer is patterned.
In the embodiment of the present disclosure, the second metal layer 120 is able to withstand the acidic etching solution, and not that the second metal layer 120 is not changed at all when in contact with the acidic etching solution, but that it is not completely corroded by the acidic etching solution, or that it is able to form a suitable structure to prevent the acidic etching solution from further corroding the second metal layer 120. For example, when the second metal layer 120 contacts the acidic etching solution, a dense protective film, such as a dense metal oxide film, may be formed on the surface of the second metal layer 120 to prevent the second metal layer 120 from further reacting with the acidic etching solution.
Alternatively, the material of the second metal layer 120 may be titanium, molybdenum, or an alloy thereof. In one embodiment of the present disclosure, the material of the second metal layer 120 is titanium.
Alternatively, as shown in fig. 2 and fig. 9, the orthographic projection of the first metal layer 110 on the substrate base plate 200 is located in the orthographic projection of the second metal layer 120 on the substrate base plate 200, so as to ensure that the second metal layer 120 completely covers the first metal layer 110.
Alternatively, the acidic etching liquid may comprise nitric acid, in particular such that the etching liquid is present as dilute nitric acid. Further, a metal salt formed when the pixel electrode layer is patterned is also dissolved in the acidic etching solution. For example, the acidic etching solution may be a dilute nitric acid solution, and when the pixel electrode layer is patterned, the nitric acid may react with silver to generate silver nitrate, and the silver nitrate is dissolved in the acidic etching solution. The material of the second metal layer 120 can withstand dilute nitric acid and silver nitrate, thereby protecting the first metal layer 110.
In the source-drain layer lead structure provided by the present disclosure, the first metal layer 110 and the second metal layer 120 may be formed by two photolithography processes, respectively. For example, the first and second metal layers 110 and 120 may be formed by:
in step S110, as shown in fig. 3 and 10, a first metal material layer 111 is formed on one side of the base substrate 200.
In step S120, a first photoresist layer is formed on a side of the first metal material layer 111 away from the substrate 200.
Step S130, exposing the first photoresist layer by using the first mask.
Step S140, developing to realize patterning of the first photoresist layer.
Step S150, etching the first metal material layer 111 to implement patterning of the first metal material layer 111.
Step S160, as shown in fig. 4 and 11, the first photoresist layer is removed, and the patterned first metal material layer 111 is exposed, so as to obtain the exposed first metal layer 110.
Step S210, as shown in fig. 5 and 12, a second metal material layer 121 is formed on a side of the first metal layer 110 away from the substrate 200, and the second metal material layer 121 covers a side of the first metal layer 110 away from the substrate 200 and a side surface of the first metal layer 110.
In step S220, as shown in fig. 6 and 13, a second photoresist layer 501 is formed on a side of the second metal material layer 121 away from the base substrate 200.
In step S230, as shown in fig. 6 and 13, the second photoresist layer 501 is exposed by using a second mask 503.
In step S240, as shown in fig. 7 and 14, the second photoresist layer 501 is patterned by developing.
In step S250, the second metal material layer 121 is etched to implement patterning of the second metal material layer 121.
In step S260, as shown in fig. 2 and 9, the second photoresist layer 501 is removed, and the patterned second metal material layer 121 is exposed, so as to obtain the exposed second metal layer 120.
In an embodiment of the present disclosure, the second mask 503 may be different from the first mask. For example, the positions of the exposure holes of the first mask plate and the second mask plate may be the same and correspond to each other, but the size of the exposure hole of the second mask plate 503 is smaller than the size of the exposure hole of the corresponding first mask plate 502, so as to ensure that the patterned second photoresist layer 501 can completely cover the first metal layer 110, and further ensure that the second metal layer 120 covers the first metal layer 110. In the embodiment, the second metal layer 120 is prepared by using a new mask, the preparation process is simple and convenient, and the process parameters are easy to determine and are not harsh.
In another embodiment of the present disclosure, as shown in fig. 8, the second mask 503 may be the same mask as the first mask 502. In this way, when exposing the second photoresist layer 501, the exposure amount needs to be precisely adjusted, so that the orthographic projection of the developed second photoresist layer 501 on the base substrate 200 completely covers the first metal layer 110.
Optionally, as shown in fig. 2 and fig. 9, the source-drain layer lead structure may further include a third metal layer 130, where the third metal layer 130 is disposed on a side of the first metal layer 110 close to the substrate base 200, so as to further protect the first metal layer 110. Optionally, the first metal layer 110 is disposed on a surface of the third metal layer 130 away from the substrate 200, and an orthographic projection of the first metal layer 110 on the substrate 200 is orthographic-coincident with an orthographic projection of the third metal layer 130 on the substrate 200.
The material of the third metal layer 130 may be the same as or different from that of the second metal layer 120, and the disclosure is not particularly limited thereto.
In one embodiment of the present disclosure, the third metal layer 130 may be patterned in the same photolithography process as the first metal layer 110. For example, as shown in fig. 3 and 10, before the step S110, a third metal material layer 131 may be formed on one side of the substrate base plate 200; in step S110, a first metal material layer 111 may be formed on the surface of the third metal material layer 131 away from the base substrate 200; as shown in fig. 4 and 11, in step S150, the first metal material layer 111 and the third metal material layer 131 may be etched at the same time, so as to implement patterning of the first metal material layer 111 and the third metal material layer 131, and obtain the first metal layer 110 and the third metal layer 130 at the same time.
In another embodiment of the present disclosure, as shown in fig. 2, the source-drain layer lead structure may further include a fourth metal layer 140, where the fourth metal layer 140 is sandwiched between the surface of the first metal layer 110 away from the substrate base plate 200 and the second metal layer 120. The material of the fourth metal layer 140 may be the same as or different from that of the second metal layer 120, which is not limited in this disclosure.
Alternatively, the fourth metal layer 140 may be patterned in the same photolithography process as the first metal layer 110. For example, as shown in fig. 3, before the step S120, a fourth metal material layer 141 may be formed on a side of the first metal material layer 111 away from the substrate base plate 200; in step S120, a first photoresist layer may be formed on a side of the fourth metal material layer 141 away from the base substrate 200. As shown in fig. 4, in step S150, the first metal material layer 111 and the fourth metal material layer 141 may be etched at the same time, so as to implement patterning of the first metal material layer 111 and the fourth metal material layer 141, and obtain the first metal layer 110 and the fourth metal layer 140 at the same time.
The embodiment of the disclosure also provides an array substrate, which includes any one of the source/drain layer lead structures described in the above source/drain layer lead structure embodiment. The array substrate may be an OLED array substrate, an LCD array substrate, or other types of array substrates. Since the array substrate has any one of the source/drain layer lead structures described in the source/drain layer lead structure embodiments, the same beneficial effects are achieved, and details are not repeated in the present disclosure.
Optionally, the array substrate provided by the present disclosure may include a substrate base 200, a driving circuit layer disposed on one side of the substrate base 200, and a pixel electrode layer disposed on one side of the driving circuit layer away from the substrate base 200. The driving circuit layer is provided with a source drain layer lead, and the source drain layer lead adopts the source drain layer lead structure described by the source drain layer lead structure. The pixel electrode layer may include pixel electrodes arranged in an array. Optionally, the pixel electrode layer is obtained by patterning the pixel electrode material layer through a wet etching process.
Because the side surface of the source drain layer lead of the array substrate is covered with the second metal layer 120, the etching liquid can not corrode the first metal layer 110 when the pixel electrode layer is patterned, various defects of the array substrate caused by the reaction of the first metal layer 110 and the etching liquid are avoided, and the yield of the array substrate is improved.
Alternatively, the pixel electrode layer may include a reflective layer and an electrode layer stacked in this order, wherein the reflective layer is disposed on a surface of the electrode layer close to the base substrate 200. The material of the reflective layer may include silver in order to achieve light blocking and light reflection; the material of the electrode layer may be a metal oxide, for example, ITO (indium tin oxide).
In the following, an implementation of the array substrate is exemplarily provided to further explain and explain the structure, the principle and the effect of the array substrate of the present disclosure.
As shown in fig. 15, the exemplary array substrate may include a substrate 200, a buffer layer 301, an active layer 302, a first gate insulating layer 303, a first gate layer 304, a second gate insulating layer 305, a second gate layer 306, an interlayer dielectric layer 307, a source-drain metal layer 308, a planarization layer 309, a pixel electrode layer 401, a pixel defining layer 402, an organic light emitting layer 403, a common electrode layer 404, a silicon oxynitride layer 405, an organic protective layer 406, and an inorganic protective layer 407. Wherein the content of the first and second substances,
a Buffer layer (Buffer)301 is provided on one side of the base substrate 200.
The active layer 302 is disposed on a side of the buffer layer 301 away from the substrate 200, and an active region of the thin film transistor may be formed.
The first gate insulating layer 303 is disposed on a side of the active layer 302 away from the substrate 200, and covers at least a portion of the active layer 302, particularly the active region of the thin film transistor.
The first gate layer 304 is disposed on a side of the first gate insulating layer 303 away from the substrate base 200, and may be formed with a gate of a thin film transistor.
The second gate insulating layer 305 is disposed on a side of the first gate layer 304 away from the substrate 200, covering the first gate layer 304.
The second gate layer 306 is provided on a side of the second gate insulating layer 305 away from the substrate base 200.
An interlayer dielectric layer (ILD)307 is disposed on a side of the second gate layer 306 away from the substrate 200, covering the second gate layer 306.
The source-drain metal layer 308 is arranged on one side of the interlayer dielectric layer 307 far away from the substrate base plate 200, and a source electrode, a drain electrode and a source-drain layer lead of the thin film transistor are formed; the source electrode and the drain electrode are electrically connected with the active region of the thin film transistor through the metalized through hole respectively; the source-drain metal layer 308 has the structure described in the above source-drain layer lead structure.
A planarization layer 309 is disposed on a side of the source-drain metal layer 308 away from the substrate 200 for providing a planarized surface for the pixel electrode. The planarization layer 309 covers the display region of the array substrate and exposes the peripheral region of the array substrate, i.e., exposes the source/drain metal layer 308 of the peripheral region of the array substrate. Since the first metal layer 110 of the source-drain metal layer 308, which is easily corroded, is covered by the second metal layer 120 which is resistant to the acidic etching solution, the source-drain metal layer 308 can exist stably in the peripheral region without further protection of a passivation layer or a planarization layer 309, and the yield of the array substrate is not influenced by corrosion.
The pixel electrode layer 401 is arranged on one side of the planarization layer 309 away from the substrate 200, the pixel electrode layer 401 is provided with a plurality of pixel electrodes distributed in an array, and any pixel electrode is electrically connected with the source-drain metal layer 308 through a metalized via hole, especially electrically connected with a drain electrode of a corresponding thin film transistor; any one of the pixel electrodes is provided with a light emitting region. A pixel electrode material layer covering the planarization layer 309 may be formed in the display region by using an open mask; the pixel electrode material layer is patterned, and during the patterning process, the pixel electrode material layer may be etched by using an acidic etching solution to form a pixel electrode layer 401. Since the source-drain metal layer 308 adopts the structure described in the above-mentioned source-drain layer lead structure embodiment, it is not corroded by the acidic etching solution.
The pixel defining layer 402 is arranged on one side of the pixel electrode layer 401 away from the substrate 200; the pixel defining layer 402 exposes the light emitting region of the pixel electrode and covers the other region.
The organic light emitting layer 403 is disposed on a side of the pixel defining layer 402 away from the substrate 200, and covers the light emitting region of each pixel electrode; in which the organic light emitting layer 403 is in contact with the pixel electrode, and electroluminescence can be realized under the control of the pixel electrode.
The common electrode layer 404 is provided on a side of the organic light emitting layer 403 remote from the base substrate 200.
The silicon oxynitride layer 405 is disposed on a side of the common electrode layer 404 away from the substrate 200 to block water and oxygen.
An organic protective layer 406 is disposed on the side of the silicon oxynitride layer 405 away from the substrate 200 to balance the stress of the mirror array substrate and provide a planarized surface.
The inorganic protective layer 407 is arranged on the side of the organic protective layer 406 away from the substrate base plate 200; the material of the inorganic protective layer 407 is silicon nitride.
In the exemplary array substrate, the buffer layer 301, the active layer 302, the first gate insulating layer 303, the first gate layer 304, the second gate insulating layer 305, the second gate layer 306, the interlayer dielectric layer 307, the source-drain metal layer 308, and the planarization layer 309, which are sequentially stacked, may form a driving circuit layer of the array substrate; the pixel electrode layer 401, the pixel defining layer 402, the organic light emitting layer 403 and the common electrode layer 404, which are sequentially stacked, may form a light emitting layer of the array substrate; the silicon oxynitride layer 405, the organic protective layer 406, and the inorganic protective layer 407, which are sequentially stacked, may form an encapsulation layer of the array substrate.
Embodiments of the present disclosure also provide a display panel including any one of the array substrates described in the above array substrate embodiments. The display panel may be an OLED display panel, an LCD display panel, or other type of display panel. Since the display panel has any one of the array substrates described in the above embodiments of the array substrate, the display panel has the same beneficial effects, and the details of the disclosure are not repeated herein.
The embodiment of the present disclosure further provides a method for manufacturing a source/drain layer lead structure, where the source/drain layer lead structure may be formed on one side of the substrate 200, and particularly may be formed on one side of the interlayer dielectric layer 307 of the array substrate, which is far away from the substrate 200. As shown in fig. 16, the method for manufacturing the source/drain layer lead structure includes:
step S310, forming a first metal layer 110 on one side of a substrate 200;
step S320, forming a second metal layer 120 on a side of the first metal layer 110 away from the substrate 200, and enabling the second metal layer 120 to cover a side surface of the first metal layer 110 and a surface of the first metal layer 110 away from the substrate 200; the second metal layer 120 has a greater resistance to the acidic etchant than the first metal layer 110.
The method for manufacturing the source/drain layer lead structure provided by the disclosure can be used for manufacturing any one of the source/drain layer lead structures described in the source/drain layer lead structure embodiments, so that the source/drain layer lead structure has the same or similar technical effects, and the details of the source/drain layer lead structure are not repeated herein.
Optionally, the first metal layer 110 comprises aluminum or copper; the material of the second metal layer 120 is titanium or molybdenum.
Optionally, the acidic etching solution comprises nitric acid and silver nitrate.
The principle, effect and other details of the method for manufacturing the source/drain layer lead structure have been described in detail in the source/drain layer lead structure embodiment, or can be reasonably derived according to the details described in the source/drain layer lead structure embodiment, and the disclosure is not repeated herein.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.
Claims (10)
1. A source-drain layer lead structure is formed on one side of a substrate; the source drain layer lead structure is characterized by comprising:
the first metal layer is arranged on one side of the substrate base plate;
the second metal layer covers the side face of the first metal layer and the surface of the first metal layer, which is far away from the substrate base plate;
the second metal layer has higher tolerance to acidic etching liquid than the first metal layer.
2. The source-drain layer lead structure according to claim 1, wherein the acidic etching solution comprises nitric acid and silver nitrate.
3. The source-drain layer lead structure according to claim 1, wherein the material of the first metal layer comprises aluminum or copper; and/or the material of the second metal layer is titanium or molybdenum.
4. The source drain layer lead structure of claim 1, further comprising:
the third metal layer is arranged between the first metal layer and the substrate base plate; the third metal layer has higher tolerance to acidic etching solution than the first metal layer.
5. An array substrate, comprising:
a substrate base plate;
the driving circuit layer is arranged on one side of the substrate and is provided with a source drain layer lead, and the source drain layer lead adopts a source drain layer lead structure as claimed in any one of claims 1-4;
and the pixel electrode layer is arranged on one side of the driving circuit layer, which is far away from the substrate base plate.
6. The array substrate of claim 5, wherein the pixel electrode layer comprises silver.
7. A display panel comprising the array substrate according to claim 5 or 6.
8. A preparation method of a source-drain layer lead structure is characterized by comprising the following steps:
forming a first metal layer on one side of a substrate;
forming a second metal layer on one side of the first metal layer, which is far away from the substrate base plate, and enabling the second metal layer to cover the side face of the first metal layer and the surface of the first metal layer, which is far away from the substrate base plate; the second metal layer has higher tolerance to acidic etching liquid than the first metal layer.
9. The method for manufacturing a source-drain layer lead structure according to claim 8, wherein the first metal layer comprises aluminum or copper; the second metal layer is made of titanium or molybdenum.
10. The method for manufacturing the source-drain layer lead structure according to claim 8, wherein the acidic etching solution comprises nitric acid and silver nitrate.
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