CN110690171A - Manufacturing method of array substrate, array substrate and display panel - Google Patents
Manufacturing method of array substrate, array substrate and display panel Download PDFInfo
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- CN110690171A CN110690171A CN201911013980.8A CN201911013980A CN110690171A CN 110690171 A CN110690171 A CN 110690171A CN 201911013980 A CN201911013980 A CN 201911013980A CN 110690171 A CN110690171 A CN 110690171A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention provides a manufacturing method of an array substrate, the array substrate and a display panel. The manufacturing method of the array substrate comprises the following steps: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a gate insulating layer, a metal oxide semiconductor layer and photoresist on a substrate base plate on which a gate is formed, and forming a first photoresist pattern having a completely removed region of the photoresist on the photoresist through a patterning process, wherein the completely removed region of the photoresist corresponds to a region where a source electrode and a drain electrode are to be formed; depositing a metal layer in the completely removed region of the photoresist by electroplating to form a source electrode and a drain electrode, respectively; stripping the photoresist; and carrying out a second photoetching process to form a metal oxide semiconductor pattern on the metal oxide semiconductor layer. The invention can improve the performance of the TFT device, thereby improving the reliability of the array substrate.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a manufacturing method of an array substrate, the array substrate and a display panel.
Background
A Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, no radiation, and the like, and occupies a leading position in the current flat panel Display market. In order to realize high-resolution display, the size of a Thin Film Transistor (TFT) device, which is a main driving element in a TFT-LCD, needs to be "miniaturized", and the realization of a Back Channel Etching (BCE) structure is the key to "miniaturization" of the size of the TFT device. In addition, the BCE-TFT is simple in manufacturing process and low in cost. More importantly, the definition precision of the channel size is high, and the miniaturization of the device size is easy to realize.
In the manufacturing process of the existing array substrate adopting back channel etching, a source drain metal layer is deposited on a metal oxide semiconductor pattern and a grid electrode insulating layer, and after the source drain metal layer is subjected to patterned etching by utilizing a one-time etching process, a source electrode, a drain electrode and a channel positioned between the source electrode and the drain electrode are obtained, namely, part of the source drain metal layer on the upper side of the metal oxide semiconductor pattern is removed by the one-time etching process, so that a channel structure is manufactured. In the etching process of forming the source electrode and the drain electrode, the metal oxide semiconductor pattern is gradually exposed along with the etching and is in direct contact with an etching medium.
In the manufacturing process, the metal oxide semiconductor patterns at the channel positions of the source electrode and the drain electrode are directly contacted with the etching medium, so that the metal oxide semiconductor patterns are easily damaged to generate by-products, the performance of the TFT device is reduced, and the reliability of the array substrate is poor.
Disclosure of Invention
The invention provides a manufacturing method of an array substrate, the array substrate and a display panel, which can avoid damage to a metal oxide semiconductor layer at a channel position and improve the reliability of the array substrate.
In a first aspect, the present invention provides a method for manufacturing an array substrate, including: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a gate insulating layer, a metal oxide semiconductor layer and photoresist on a substrate base plate on which a gate is formed, and forming a first photoresist pattern having a completely removed region of the photoresist on the photoresist through a patterning process, wherein the completely removed region of the photoresist corresponds to a region where a source electrode and a drain electrode are to be formed; depositing a metal layer in the completely removed region of the photoresist by electroplating to form a source electrode and a drain electrode, respectively; stripping the photoresist; and carrying out a second photoetching process to form a metal oxide semiconductor pattern on the metal oxide semiconductor layer.
In a second aspect, the present invention provides an array substrate, including: the grid electrode is arranged on the substrate base plate, the grid electrode insulating layer covers the grid electrode and the substrate base plate, the metal oxide semiconductor pattern covers part of the grid electrode insulating layer and is located above the grid electrode, the source electrode and the drain electrode are both arranged on the metal oxide semiconductor pattern, a channel region is arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode are formed through an electroplating process.
In a third aspect, the present invention provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate
The invention discloses a manufacturing method of an array substrate, the array substrate and a display panel. As described above, in the method of fabricating the array substrate, after depositing the metal oxide semiconductor layer on the gate insulating layer, the metal oxide semiconductor layer is not immediately patterned, but a photoresist is deposited on the metal oxide semiconductor layer and patterned to form a first photoresist pattern having a completely removed region of the photoresist, a metal layer is deposited in the completely removed region of the photoresist by electroplating to form the source and drain electrodes, respectively, and the metal oxide semiconductor layer is patterned after forming the source and drain electrodes to form the metal oxide semiconductor pattern, such that, in the process of forming the source and drain electrodes by electroplating, a region corresponding to a channel in the metal oxide semiconductor layer is protected by the photoresist without being damaged, and in the process of patterning the metal oxide semiconductor pattern after forming the source and drain electrodes, the channel part is protected by using photoresist in a corresponding photoetching process as a mask, and compared with the prior art that a metal oxide semiconductor layer at the position of the channel is directly contacted with an etching medium, zero damage to the channel is realized in the whole manufacturing process. Therefore, the performance of the TFT device can be improved, and the reliability of the array substrate can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate in a first state in a manufacturing method of the array substrate according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of the array substrate in a second state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4 is a schematic structural diagram of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 5 is a schematic structural diagram of the array substrate in a fourth state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 6 is a schematic structural diagram of the array substrate in a fifth state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 7 is a schematic structural diagram of the array substrate in a sixth state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 8 is a schematic structural diagram of the array substrate in a seventh state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 9 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;
FIG. 10 is a performance test chart of a TFT on an array substrate according to the prior art;
fig. 11 is a performance test chart of a thin film transistor on an array substrate according to a second embodiment of the present invention;
fig. 12 is a graph illustrating the results of a corrosion test on an array substrate according to the related art;
fig. 13 is a schematic diagram illustrating a result of an array substrate after a corrosion test according to a second embodiment of the present invention.
Reference numerals:
1-a substrate base plate; 2-a grid; 3-a gate insulating layer; 50-a metal oxide semiconductor layer; 5-metal oxide semiconductor pattern; 6-photoresist; 61-completely removed region of photoresist; a 7-source electrode; 8-a drain electrode; 81-metal buffer layer; 82-a metal body layer; 9-a metal oxide protective layer; 91-a conductive via; 92-pixel electrodes.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 1 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the present invention, as shown in fig. 1, the manufacturing method of an array substrate according to the embodiment includes:
and S10, depositing a gate metal layer on the substrate base plate, and carrying out a first photoetching process to form a gate on the substrate base plate.
Fig. 2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and referring to fig. 2, a gate metal layer is first deposited on the substrate 1, specifically, the gate metal layer is deposited by sputtering or thermal evaporation, the gate metal layer may be selected from W, Cu, Ti, Ta, Mo, and other metals or alloys, and the gate metal layer composed of multiple layers of metals may also meet the requirement. Next, a first photolithography process is performed on the gate metal layer to form a gate 2 in the switching region of the array substrate. In addition, in practice, the array substrate includes a plurality of sub-pixel regions defined by scan lines and data lines, and each sub-pixel region is provided with a thin film transistor device, for convenience of description, in the drawings of the present application, a schematic diagram of manufacturing only one of the sub-pixel regions is drawn, it can be understood that the array substrate includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate of the present application, the forming of the gate 2 on the substrate 1 specifically means forming the gate 2 in the region of the array substrate corresponding to each sub-pixel region. Similarly, the source electrode 7, the drain electrode 8, and the metal oxide semiconductor layer 50 are not described in detail here.
S20, sequentially depositing a gate insulating layer 3, a metal oxide semiconductor layer 50, and a photoresist on the substrate 1 on which the gate electrode 2 is formed, and forming a first photoresist pattern on the photoresist through a patterning process, wherein the first photoresist pattern has a completely removed region 61 of the photoresist, and the completely removed region 61 of the photoresist corresponds to a region where the source electrode 7 and the drain electrode 8 are to be formed.
Fig. 3 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and referring to fig. 3, on the basis of the array substrate in the first state, a gate insulating layer 3 is deposited by a plasma enhanced chemical vapor deposition method, a metal oxide semiconductor layer 50 is deposited by sputtering or thermal evaporation, then a whole layer of photoresist 6 is coated on the metal oxide semiconductor layer 50, and a first photoresist pattern is formed on the photoresist by a patterning process, the first photoresist pattern includes a completely removed region 61 of the photoresist, the completely removed region 61 of the photoresist corresponds to a region where a source electrode 7 and a drain electrode 8 are to be formed, and at this time, the array substrate is in the second state as shown in fig. 3.
The gate insulating layer 3 may be an oxide, a nitride, or an oxynitride. The gate insulating layer 3 may be a single layer or a multilayer, and a double layer of SiN is preferably usedxAnd SiOxFilm, in contact with the underlying substrate 1 is SiNxOn which is SiOxIn contact with the metal oxide semiconductor layer 50.
The metal oxide semiconductor layer 50 may be Indium Gallium Zinc Oxide (IGZO), or Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, which may be amorphous metal oxides or polycrystalline metal oxides.
Among them, Photoresist (PR) is an organic compound, and is classified into a positive photoresist and a negative photoresist according to the relationship between the crosslinking reaction in the photoresist and ultraviolet rays. For positive photoresist, the photoresist in the area irradiated by ultraviolet light is subjected to crosslinking decomposition reaction, and the part can be dissolved in a developing solution; for a negative photoresist, the photoresist undergoes a cross-linking reaction in the areas irradiated with ultraviolet light, which is difficult to dissolve in a developer. For convenience of explanation, the positive photoresist will be described as an example. The patterning process is a technique of removing a part of the complete material layer to form a desired structure on the remaining part of the complete material layer, and may generally include an exposure process and a development process, and specifically, optionally, the forming a first photoresist pattern on the photoresist by the patterning process specifically includes: a first photoresist pattern is formed on the photoresist by performing an exposure process and a development process on the photoresist.
The exposure process specifically refers to transferring the pattern on the mask onto the photoresist, and specifically in this embodiment, the light-transmitting portion of the mask corresponds to the region where the source electrode 7 and the drain electrode 8 are to be formed, so that the photoresist corresponding to the light-transmitting portion of the mask on the photoresist is irradiated by ultraviolet light to generate a cross-linking decomposition reaction, and the rest of the photoresist does not generate the cross-linking decomposition reaction. The developing process is a process of dissolving the photoresist irradiated with ultraviolet rays into a developing solution after exposure. Specifically, in the present embodiment, a portion of the photoresist in which the cross-linking decomposition reaction occurs corresponds to a region where the source electrode 7 and the drain electrode 8 are to be formed, and the portion of the photoresist is dissolved in a developing solution to form a completely removed region 61 of the photoresist, thereby forming a first photoresist pattern on the photoresist. Thus, the first photoresist pattern includes a completely removed region 61 of the photoresist corresponding to a region where the source electrode 7 and the drain electrode 8 are to be formed, and the remaining portion of the first photoresist pattern may be a completely remaining region of the photoresist or a partially remaining region of the photoresist.
S30, a metal layer is deposited in the completely removed region 61 of the photoresist by electroplating to form the source and drain electrodes 7 and 8, respectively.
Fig. 4 is a schematic structural diagram of the array substrate in the third state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and referring to fig. 4, a metal layer is deposited in the completely removed area 61 of the photoresist by electroplating on the basis of the array substrate in the second state. Electroplating is a process of plating other metals or alloys on the surface of a conductive material by utilizing the electrolysis principle, and during electroplating, plating metal or other insoluble materials are used as an anode, a matrix to be plated is used as a cathode, and cations of the plating metal are reduced on the surface of a workpiece to be plated to form a plating layer. Specifically, in the present embodiment, the metal oxide semiconductor layer 50 is connected to the cathode of the electrolytic cell, the target to be plated with metal is connected to the anode of the electrolytic cell, the cathode and the anode of the electrolytic cell are connected through the electrolytic solution containing the metal ions to be plated, and a current is applied between the cathode and the anode of the electrolytic cell, and the plating is performed for a predetermined period of time, and since only a portion corresponding to the completely removed region in the metal oxide semiconductor layer 50 is exposed to the electrolytic solution, the metal layer is formed in the completely removed region 61 of the photoresist to form the source electrode 7 and the drain electrode 8. In this process, since the plated metal is formed in the completely removed region 61 of the photoresist, the shapes of the source electrode 7 and the drain electrode 8 depend on the shape of the completely removed region 61 of the photoresist, that is, the shapes of the source electrode and the drain electrode are formed by using the photoresist, which solves the problem that the shapes of the source electrode and the drain electrode 8 cannot be accurately controlled when the source electrode and the drain electrode 8 are formed by using a photolithography process in the prior art.
And S40, stripping the photoresist.
Fig. 5 is a schematic structural diagram of the array substrate in the fourth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and referring to fig. 5, the photoresist is stripped off on the basis of the array substrate in the third state, and the source electrode 7 and the drain electrode 8 are formed on the metal oxide semiconductor layer 50.
The photoresist stripping process (Stripper) is a process of removing the photoresist using a dry or wet process. The stripping process has two modes of dry stripping and wet stripping. After the above-described photoresist stripping process, the photoresist may be removed to expose the source and drain electrodes 7 and 8.
And S50, performing a second photolithography process to form a metal oxide semiconductor pattern 5 on the metal oxide semiconductor layer 50.
Fig. 6 is a schematic structural diagram of the array substrate in the fifth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and referring to fig. 6, a second photolithography process is performed on the basis of the array substrate in the fourth state, so that the metal oxide semiconductor layer 50 forms the metal oxide semiconductor pattern 5.
As described above, in the method of fabricating the array substrate of the present embodiment, after the metal oxide semiconductor layer 50 is deposited on the gate insulating layer 3, the metal oxide semiconductor layer 50 is not immediately patterned, but a photoresist is deposited on the metal oxide semiconductor layer 50 and patterned to form a first photoresist pattern having the completely removed region 61 of the photoresist, a metal layer is deposited in the completely removed region 61 of the photoresist by electroplating to form the source electrode 7 and the drain electrode 8, respectively, and the metal oxide semiconductor layer 50 is patterned after the source electrode 7 and the drain electrode 8 are formed to form the metal oxide semiconductor pattern, so that the region corresponding to the channel in the metal oxide semiconductor layer 50 is protected by the photoresist and is not damaged during the electroplating to form the source electrode 7 and the drain electrode 8, and the source electrode 7, In the process of patterning the metal oxide semiconductor pattern after the drain 8 is formed, the channel part is protected by using photoresist in a corresponding photoetching process as a mask, and compared with the prior art that the metal oxide semiconductor layer 50 at the position of the channel is directly contacted with an etching medium, zero damage to the channel is realized in the whole manufacturing process. Therefore, the performance of the TFT device can be improved, and the reliability of the array substrate can be improved.
Further, a metal layer is deposited in the completely removed region 61 of the photoresist by electroplating to form the source electrode 7 and the drain electrode 8, which specifically includes:
performing a first electroplating process to form a metal buffer layer 81 in the completely removed region 61 of the photoresist; and performing a second electroplating process to form a metal body layer 82 on the metal buffer layer 81 to form the source electrode 7 and the drain electrode 8, respectively, wherein the metal contained in the metal buffer layer 81 and the metal body layer 82 are different.
That is, the source electrode 7 and the drain electrode 8 are both formed of two layers of metal, the metal buffer layer 81 is first formed in the completely removed region 61 of the photoresist, the metal buffer layer 81 has good conductivity, and at the same time, the adhesion between the metal body layer 82 of the source electrode 7 and the drain electrode and the metal oxide semiconductor layer 50 can be increased, and the thickness of the metal buffer layer 81 can be set to be equal toFurther, alternatively, the plating solution of the first plating process may include at least one of Mo (molybdenum) ions, W (tungsten) ions, and Ti (titanium) ions, that is, the metal buffer layer 81 may include at least one of metal Mo, metal W, and metal Ti.
After the metal buffer layer 81 is fabricated, a metal body layer 82 is formed on the metal buffer layer 81 by a second electroplating process, and the source electrode 7 and the drain electrode 8 are collectively formed by the metal buffer layer 81 and the metal body layer 82. Alternatively, the plating solution of the second plating process contains Cu ions, i.e., the metal body layer 82 may contain metallic Cu. The metal buffer layer 81 includes at least one of metal Mo, metal W, and metal Ti, and the metal body layer 82 includes metal Cu, but other types of metals may be selected for the metal buffer layer 81 and the metal body layer 82, as long as the metal buffer layer 81 can increase the adhesion between the metal body layer 82 and the metal oxide semiconductor layer 50.
The electroplating process will be described below by taking the second electroplating process as an example, and the first electroplating process is similar to the second electroplating process and will not be described herein again.
Specifically, the electrolytic solution containing Cu ions may be, for example, CuSO4And (3) solution. In the electroplating process of the present invention, the metal oxide semiconductor layer 50 (metal buffer layer 81) is used as a cathode for electroplating, and copper ions are deposited on the metal buffer layer 81 of the completely removed photoresist region 61 under the action of current to form a Cu metal layer. And the other parts are positioned below the photoresist and protected by the photoresist, so that the Cu metal layer cannot be electroplated, and the Cu metal layer can be accurately formed at the parts where the source electrode 7 and the drain electrode 8 are to be formed.
Further, optionally, the thickness of the metal buffer layer 81 needs to be smaller than that of the metal body layer 82. The control of the thickness of the metal buffer layer 81 and the metal body layer 82 can be controlled by adjusting the solution concentration of the electrolytic solution, the current density, and the plating time period during the plating process. Preferably, the thickness of the metal buffer layer 81 is one tenth of the thickness of the metal body layer 82, so that the metal buffer layer 81 can ensure that the resistance of the whole source electrode 7 and the whole drain electrode 8 is not affected, and the metal body layer 82 can be well buffered and protected.
Further, fig. 7 is a schematic structural diagram of the array substrate in a sixth state in the manufacturing method of the array substrate according to the first embodiment of the present invention; fig. 8 is a schematic structural diagram of the array substrate in a seventh state in the manufacturing method of the array substrate according to the first embodiment of the present invention. Referring to fig. 7 and 8, after forming the metal oxide semiconductor layer 50 into the metal oxide semiconductor pattern 5, the method further includes: on the basis of the array substrate in the fifth state, the metal oxide protection layer 9 is deposited, and a third photolithography process is performed to form the conductive via 91 on the region of the metal oxide protection layer 9 above the drain electrode 8. And depositing a transparent conductive film on the basis of the array substrate in the sixth state, and performing a fourth photolithography process to form a pixel electrode 92 on the transparent conductive film, wherein the pixel electrode 92 is electrically connected to the drain electrode 8 via a conductive via 91.
The metal oxide protective layer 9 is deposited by a plasma enhanced chemical vapor deposition method, and the metal oxide protective layer 9 may be an oxide or an oxynitride. A conductive via 91 is formed just above the drain 8 to expose the drain 8.
In addition, a transparent conductive film is deposited by sputtering or thermal evaporation, and the transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO, or other transparent metal oxides. A transparent conductive film is used to form the pixel electrode 92, and a portion of the transparent conductive film is deposited in the conductive via 91 to electrically connect the pixel electrode 92 and the drain electrode 8.
In this embodiment, the method for manufacturing the array substrate includes: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a gate insulating layer, a metal oxide semiconductor layer and photoresist on a substrate base plate on which a gate is formed, and forming a first photoresist pattern on the photoresist through a composition process, wherein the first photoresist pattern comprises a completely removed region of the photoresist, and the completely removed region of the photoresist corresponds to a region where a source electrode and a drain electrode are to be formed; depositing a metal layer in the completely removed region of the photoresist by electroplating to form a source electrode and a drain electrode, respectively; stripping the photoresist; and carrying out a second photoetching process to form a metal oxide semiconductor pattern on the metal oxide semiconductor layer. As described above, in the method for manufacturing an array substrate of this embodiment, in the process of forming the source electrode and the drain electrode by electroplating, the region corresponding to the channel in the metal oxide semiconductor layer is protected by the photoresist and is not damaged, and in the process of patterning the metal oxide semiconductor pattern after the source electrode and the drain electrode are formed, the channel portion is protected by the photoresist in the corresponding photolithography process as a mask. Therefore, the performance of the TFT device can be improved, and the reliability of the array substrate can be improved.
Example two
Fig. 9 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention, and as shown in fig. 9, the array substrate of the present embodiment includes: the semiconductor device comprises a substrate base plate 1, a grid electrode 2, a grid electrode insulating layer 3, a metal oxide semiconductor pattern 5, a source electrode 7 and a drain electrode 8, wherein the grid electrode 2 is arranged on the substrate base plate 1, the grid electrode insulating layer 3 covers the grid electrode 2 and the substrate base plate 1, the metal oxide semiconductor pattern 5 covers part of the grid electrode insulating layer 3 and is located above the grid electrode 2, the source electrode 7 and the drain electrode 8 are arranged on the metal oxide semiconductor pattern 5, a channel region is arranged between the source electrode 7 and the drain electrode 8, and the source electrode 7 and the drain electrode 8 are formed through an electroplating process.
Specifically, the metal of the gate 2 may be W, Cu, Ti, Ta, Mo, or other metal or alloy, and the gate 2 may be composed of a single layer of metal or multiple layers of metal.
The gate insulating layer 3 may be made of an oxide, nitride, or oxynitride, the gate insulating layer 3 may be a single layer or a multilayer, and a double layer of SiN is preferably usedxAnd SiOxFilm, in contact with the underlying substrate 1 is SiNxOn which is SiOxIn contact with the metal oxide semiconductor layer 50.
The metal oxide semiconductor layer 50 may be Indium Gallium Zinc Oxide (IGZO), or Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides; the above metal oxide may be an amorphous metal oxide and may be a polycrystalline metal oxide.
In the array substrate of the present embodiment, since the source electrode 7 and the drain electrode 8 are formed by the plating process, compared with the source electrode 7 and the drain electrode 8 formed by etching in the photolithography process in the prior art, since the channel portion is not directly contacted with the etching medium, zero damage of the channel is achieved. Therefore, the performance of the TFT device can be improved, and the reliability of the array substrate can be improved.
In the present application, the thickness, the material, the process, and the like of each metal layer or film layer are examples, and the present invention is not limited thereto, and other thicknesses and materials may be selected. The array substrate provided in this embodiment can be manufactured by the manufacturing method of the array substrate described in the first embodiment, wherein the manufacturing method of the array substrate is described in detail in the first embodiment, and thus, the details are not described herein again.
Further, the source electrode 7 and the drain electrode 8 each include a metal buffer layer 81 and a metal body layer 82, the metal buffer layer 81 has good conductivity, and at the same time, the metal body layer 82 of the source electrode 7 and the drain electrode and the metal oxide semiconductor layer 50 can be attached to each other, and the metal buffer layer 81 can have a thickness of
The metal buffer layer 81 is made of at least one of Mo, W, and Ti, and the metal bulk layer 82 is made of Cu to reduce the resistance of the source electrode 7 and the drain electrode 8 as much as possible. Of course, as described in the method for manufacturing the array substrate in the first embodiment, the metal buffer layer 81 and the metal body layer 82 may be formed by two electroplating processes.
In addition, the thickness of the metal buffer layer 81 needs to be smaller than the thickness of the metal body layer 82. Preferably, the thickness of the metal buffer layer 81 is one tenth of the thickness of the metal body layer 82, so that the metal buffer layer 81 can not affect the resistance of the whole source electrode 7 and the whole drain electrode 8, and can buffer and protect the metal body layer 82 well.
On the basis of the above embodiment, in this embodiment, the array substrate further includes: a metal oxide protective layer 9, a conductive via 91, and a pixel electrode 92; the metal oxide protective layer 9 covers the gate insulating layer 3, the source electrode 7, the channel region and the drain electrode 8, the pixel electrode 92 covers the metal oxide protective layer 9, a conductive via 91 is disposed on the metal oxide protective layer 9, and the pixel electrode 92 is electrically connected to the drain electrode 8 through the conductive via 91.
The metal oxide protective layer 9 may be an oxide or an oxynitride.
The pixel electrode 92 is a transparent conductive film, which may be ITO or IZO, or other transparent metal oxides.
The performance of the array substrate of the present embodiment is verified through experiments. Fig. 10 is a performance test chart of a thin film transistor on an array substrate in the prior art, and fig. 11 is a performance test chart of a thin film transistor on an array substrate according to a second embodiment of the present invention. In the thin film transistor transfer characteristic curves of fig. 10 and fig. 11, in the array substrate of this embodiment of fig. 11, when the voltages of the source 7 and the gate 2 of the thin film transistor are reversely biased, the leakage current can be significantly reduced, so that it can be seen that the performance of the thin film transistor in the array substrate of this embodiment is better. In addition, fig. 12 is a schematic view of a result of a corrosion test of the array substrate in the related art; fig. 13 is a schematic diagram illustrating a result of an array substrate after a corrosion test according to a second embodiment of the present invention. Comparing the two results, it can be seen that the thin film transistor of the array substrate of the prior art shown in fig. 12 has a serious corrosion to the metal oxide semiconductor pattern, whereas the thin film transistor of the array substrate of the present embodiment shown in fig. 13 has no corrosion to the metal oxide semiconductor pattern.
In this embodiment, the array substrate includes a substrate, a gate insulating layer, a metal oxide semiconductor pattern, a source and a drain, the gate is disposed on the substrate, the gate insulating layer covers the gate and the substrate, the metal oxide semiconductor pattern covers part of the gate insulating layer and is located above the gate, the source and the drain are both disposed on the metal oxide semiconductor pattern, and a channel region is disposed between the source and the drain, wherein the source and the drain are formed by an electroplating process. Because the source electrode and the drain electrode are formed through the electroplating process, compared with the source electrode and the drain electrode which are formed through etching in the photoetching process in the prior art, the zero damage of the channel is realized because the channel part is not directly contacted with the etching medium. Therefore, the performance of the TFT device can be improved, and the reliability of the array substrate can be improved.
EXAMPLE III
The present embodiment provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate of the second embodiment, where the liquid crystal layer is sandwiched between the color film substrate and the array substrate. The specific structure and function of the array substrate have been described in detail in the second embodiment, and thus are not described herein again
Another aspect of this embodiment further provides a display device, including the display panel, where the display device may be a flexible display device, and in this embodiment, the display device may be an electronic paper, a tablet computer, or a liquid crystal display.
In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", and the like, are used to indicate an orientation or positional relationship based on that shown in the drawings, merely to facilitate the description of the invention and to simplify the description, and do not indicate or imply that the position or element referred to must have a particular orientation, be of particular construction and operation, and thus, are not to be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; may be mechanically coupled, may be electrically coupled or may be in communication with each other; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
depositing a grid metal layer on a substrate, and carrying out a first photoetching process to form a grid on the substrate;
sequentially depositing a gate insulating layer, a metal oxide semiconductor layer and photoresist on a substrate base plate on which the gate is formed, and forming a first photoresist pattern with a completely removed region of the photoresist on the photoresist through a composition process, wherein the completely removed region of the photoresist corresponds to a region where a source electrode and a drain electrode are to be formed;
depositing a metal layer in the completely removed region of the photoresist by electroplating to form the source electrode and the drain electrode, respectively;
stripping the photoresist;
and carrying out a second photoetching process to form a metal oxide semiconductor pattern on the metal oxide semiconductor layer.
2. The method for manufacturing the array substrate according to claim 1, wherein the depositing a metal layer in the completely removed region of the photoresist by electroplating to form the source electrode and the drain electrode respectively comprises:
carrying out a first electroplating process to form a metal buffer layer in the completely removed region of the photoresist;
and performing a second electroplating process to form a metal body layer on the metal buffer layer so as to form a source electrode and a drain electrode respectively, wherein the metal buffer layer and the metal body layer contain different metals.
3. The method for manufacturing the array substrate of claim 2, wherein the plating solution of the first electroplating process comprises at least one of molybdenum ions, tungsten ions and titanium ions, and the plating solution of the second electroplating process comprises copper ions.
4. The method of claim 2, wherein the metal buffer layer has a thickness less than that of the metal body layer.
5. The method for manufacturing the array substrate according to any one of claims 1 to 4, further comprising, after the performing the second photolithography process to form the metal oxide semiconductor layer into the metal oxide semiconductor pattern:
depositing a metal oxide protective layer, and carrying out a third photoetching process to form a conductive through hole in the region of the metal oxide protective layer above the drain electrode;
and depositing a transparent conductive film, and performing a fourth photoetching process to enable the transparent conductive film to form a pixel electrode, and enabling the pixel electrode to be electrically connected with the drain electrode through the conductive via hole.
6. The method for manufacturing the array substrate according to any one of claims 1 to 4, wherein the forming a first photoresist pattern on the photoresist through a patterning process specifically comprises:
forming the first photoresist pattern on the photoresist by performing an exposure process and a development process on the photoresist.
7. The array substrate is characterized by comprising a substrate, a grid insulating layer, a metal oxide semiconductor pattern, a source electrode and a drain electrode, wherein the grid is arranged on the substrate, the grid insulating layer covers the grid and the substrate, the metal oxide semiconductor pattern covers part of the grid insulating layer and is positioned above the grid, the source electrode and the drain electrode are both arranged on the metal oxide semiconductor pattern, a channel region is arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode are formed through an electroplating process.
8. The array substrate of claim 7, wherein the source electrode and the drain electrode each comprise a metal buffer layer and a metal bulk layer, the metal buffer layer is made of at least one of molybdenum, tungsten and titanium, the metal bulk layer is made of copper, and/or the metal buffer layer and the metal bulk layer are formed by two electroplating processes respectively.
9. The array substrate of claim 8, wherein the metal buffer layer has a thickness less than a thickness of the metal body layer.
10. A display panel, comprising a color filter substrate, a liquid crystal layer and the array substrate of any one of claims 7 to 9, wherein the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.
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| CN112002752A (en) * | 2020-07-27 | 2020-11-27 | 北海惠科光电技术有限公司 | Preparation method of source-drain electrode, preparation method of array substrate and display mechanism |
| CN112002753A (en) * | 2020-07-27 | 2020-11-27 | 北海惠科光电技术有限公司 | Grid unit and preparation method thereof, preparation method of array substrate and display mechanism |
| CN112309970A (en) * | 2020-10-30 | 2021-02-02 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate and array substrate |
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