CN111653687A - Array substrate and preparation method thereof - Google Patents

Array substrate and preparation method thereof Download PDF

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Publication number
CN111653687A
CN111653687A CN202010603766.4A CN202010603766A CN111653687A CN 111653687 A CN111653687 A CN 111653687A CN 202010603766 A CN202010603766 A CN 202010603766A CN 111653687 A CN111653687 A CN 111653687A
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layer
metal
substrate
array substrate
isolation layer
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张盼龙
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Yungu Guan Technology Co Ltd
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Yungu Guan Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The application provides an array substrate and a preparation method thereof. The array substrate includes: a substrate, a metal isolation layer and a protective layer. Wherein the substrate comprises a display area and a non-display area; the metal isolation layer is positioned in the non-display area and encloses to form an opening area; the protective layer at least covers the side wall of the metal isolation layer. Because the protective layer at least coats the side wall of the metal isolation layer, the situation that the etching solution and the side wall of the metal isolation layer have a displacement reaction in the subsequent process of etching the electrode layer can be avoided, the situation that the metal particles generated by the displacement reaction influence the normal work of the array substrate is avoided, and the display failure caused by the metal particles generated by the displacement reaction is avoided.

Description

Array substrate and preparation method thereof
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
With the rapid development of electronic devices, the requirements of users on screen occupation ratio are higher and higher, and the comprehensive screen display of the electronic devices receives more and more attention in the industry.
In the conventional art, the screen ratio is generally increased by forming holes in the display panel. The opening area of the display panel can be provided with a camera, a receiver, an infrared sensor and the like.
However, the conventional hole forming technology easily causes poor display of the display panel.
Disclosure of Invention
In view of the above, it is necessary to provide an array substrate and a method for manufacturing the same, which are directed to the problem in the conventional technology that the display panel is prone to poor display due to the holes.
An aspect of the present application provides an array substrate, including: a substrate including a display region and a non-display region; the metal isolation layer is positioned in the non-display area and forms an opening area in an enclosing mode; and the protective layer at least coats the side wall of the metal isolation layer.
In one embodiment, the protective layer includes at least one of an organic film layer and an inorganic film layer. Embodiments of a protective layer are provided.
In one embodiment, the protective layer has a thickness in a range of 200 to 400 angstroms. On the basis of protecting the metal isolation layer, the raw material can be saved.
In one embodiment, the material of the protective layer comprises indium tin oxide. One possible embodiment of a protective layer is provided.
In one embodiment, the metal isolation layer comprises a first metal layer and a second metal layer which are stacked, the second metal layer is positioned on one side of the first metal layer far away from the substrate, and the material of the first metal layer comprises aluminum; the protective layer at least covers the side wall of the first metal layer. The protective layer is only required to coat the side wall of the first metal layer, so that the manufacturing process can be effectively simplified on the basis of saving raw materials.
In one embodiment, a longitudinal section of the first metal layer in a direction perpendicular to the substrate is rectangular or trapezoidal. One possible embodiment of the first metal layer is provided.
In one embodiment, the protective layer surrounds the substrate to completely cover the metal isolation layer. The protective layer in this embodiment can completely protect the metal isolation layer.
Another aspect of the present application provides a method for manufacturing an array substrate, including: providing a substrate, wherein the substrate comprises a display area and a non-display area; forming a metal isolation layer in the non-display area, wherein the metal isolation layer surrounds to form an opening area; and forming a protective layer, wherein the protective layer at least covers the side wall of the metal isolation layer.
In one embodiment, the forming a protection layer, the protection layer covering at least a sidewall of the metal isolation layer, includes: and forming a protective layer, wherein the protective layer and the substrate are enclosed so as to completely cover the metal isolation layer.
In one embodiment, the forming a protection layer, the protection layer covering at least a sidewall of the metal isolation layer, includes: forming an indium tin oxide film, wherein the indium tin oxide film and the substrate surround to coat the metal isolation layer; etching the indium tin oxide film, and removing the indium tin oxide film covered on the surface of the metal isolation layer, which is far away from the substrate; and baking the indium tin oxide film to form a protective layer with a polycrystalline structure.
The application provides an array substrate and a preparation method thereof, wherein the array substrate comprises: a substrate, a metal isolation layer and a protective layer. Wherein the substrate comprises a display area and a non-display area; the metal isolation layer is positioned in the non-display area and encloses to form an opening area; the protective layer at least covers the side wall of the metal isolation layer. Because the protective layer at least covers the side wall of the metal isolation layer, the replacement reaction between the etching solution and the side wall of the metal isolation layer in the subsequent process of etching the electrode layer formed on the substrate can be avoided, so that the influence of metal particles generated by the replacement reaction on the normal work of the array substrate is avoided, and the problem of poor display caused by the metal particles generated by the replacement reaction is avoided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure;
FIG. 3 is a schematic view of a method for fabricating an array substrate according to an embodiment of the present disclosure;
FIG. 4 is a schematic view of the substrate and the metal isolation layer in one embodiment of the present application;
FIG. 5 is a schematic view of a method for fabricating an array substrate according to another embodiment of the present disclosure;
FIG. 6 is a schematic view of a method for fabricating an array substrate according to another embodiment of the present disclosure;
FIG. 7 is a schematic view of a method for fabricating an array substrate according to still another embodiment of the present disclosure;
FIG. 8 is a schematic view of the position relationship of a substrate and a metal isolation layer according to another embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application;
FIG. 10 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure;
FIG. 11 is a schematic cross-sectional view of an array substrate according to another embodiment of the present application;
FIG. 12 is a schematic cross-sectional view of an array substrate according to still another embodiment of the present application;
fig. 13 is a schematic cross-sectional view of an array substrate according to still another embodiment of the present application.
Wherein, the meanings represented by the reference numerals of the figures are respectively as follows:
10. an array substrate; 100. a substrate; 102. a display area; 104. a non-display area; 106. an opening area; 110. a conductive layer; 120. a metal isolation layer; 1202. a first side wall; 1204. a second side wall; 122. a first metal layer; 124. a second metal layer; 126. a third metal layer; 130. a protective layer; 1301. an indium tin oxide film; 140. and an electrode layer.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are for convenience of description and simplicity of description only, and are not to be construed as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
The display panel generally includes an array substrate, light emitting pixels on the array substrate, and an encapsulation layer for encapsulating the light emitting pixels. The array substrate is used for driving the light-emitting pixels to emit light. The display panel can be provided with an opening area, and a camera, an earphone, an infrared sensor and the like can be arranged in the opening area.
In the conventional technology, the preparation process of the array substrate of the display panel having the opening area generally includes: forming a conductive layer and a metal isolation layer on the substrate, and isolating an opening area by the metal isolation layer; and forming an electrode layer on the conductive layer, and etching the side walls of the electrode layer and the metal isolation layer simultaneously to form the array substrate. The inventor finds out in the process of realizing the conventional technology that: due to the different materials of the electrode layer and the metal isolation layer, a displacement reaction may occur during the process of simultaneously etching the sidewalls of the electrode layer and the metal isolation layer. The displacement reaction may generate metal particles that may affect the normal light emission of the light-emitting pixel.
In view of the above problems, the present application provides an array substrate and a method for manufacturing the array substrate, which can be used to manufacture a display panel, as follows.
In one embodiment, the present application provides an array substrate 10. As shown in fig. 1, the array substrate 10 includes a substrate 100, a metal isolation layer 120, and a protective layer 130.
Specifically, the substrate 100 is used to carry other devices of the array substrate 10. The substrate 100 may be made using a flexible material, such as a polyimide film; rigid materials such as clear glass may also be used for fabrication. In this embodiment, the substrate 100 includes a display region 102 and a non-display region 104 that are adjacent. After the array substrate 10 is fabricated into a display panel, the display area 102 is used for light emitting display, and the non-display area 104 may be used for placing devices such as a camera, an infrared sensor, or a receiver. The location of the display area 102 and the non-display area 104 may be as shown in fig. 4.
The metal isolation layer 120 is located in the non-display region 104, and the metal isolation layer 120 encloses the opening region 106. In other words, the metal isolation layer 120 is located between the opening region 106 and the display region 102, thereby spacing the opening region 106 from the display region 102. The locations of the display area 102, the open area 106 and the metal isolation layer 120 may be as shown in fig. 4.
The protective layer 130 at least covers the sidewall of the metal isolation layer 120 to prevent the etching solution from generating a displacement reaction with the sidewall of the metal isolation layer 120 in the subsequent process. Here, the guard bar 130 may be made of a non-metal material.
When the electrode layer 140 is formed on the array substrate 10 and is etched, the etching solution does not generate a displacement reaction with the sidewall of the metal isolation layer 120 to generate metal particles, so that the metal particles can be prevented from affecting the normal operation of the array substrate 10. When the array substrate 10 is used for manufacturing a display panel, poor display of the display panel caused by the existence of metal particles can be avoided.
In one embodiment, the protection layer 130 covers only the sidewalls of the metal isolation layer 120. In another embodiment, the passivation layer 130 surrounds the substrate 100 and completely covers the metal isolation layer 120. Specifically, the protective layer 130 may completely cover the metal isolation layer 120. In the embodiment where the passivation layer 130 completely covers the metal isolation layer 120, the metal isolation layer 120 is formed on the substrate 100, and the passivation layer 130 covers the metal isolation layer 120 and surrounds the substrate 100, so that the metal isolation layer 120 is completely isolated from air, in other words, the passivation layer 130 completely covers the metal isolation layer 120. Thereby effectively preventing the subsequent replacement reaction between the etching solution for etching the electrode layer 140 and the metal isolation layer 120. It is appreciated that the protection layer 130 may only cover the sidewalls of the metal isolation layer 120. The setting can be performed according to actual conditions, and is not specifically limited herein.
Further, as shown in fig. 2, the array substrate 10 may further include a conductive layer 110 and an electrode layer 140 on the conductive layer 110.
The conductive layer 110 is located in the display region 102. The conductive layer 110 typically includes several driver circuits. When the array substrate 10 is manufactured into a display panel, each driving circuit is used for driving one light-emitting pixel to emit light. Each of the driving circuits generally includes a plurality of TFTs (Thin Film transistors) and a capacitor. When the display panel works, the driving circuit can output driving current for driving the light-emitting pixels.
The electrode layer 140 covers the conductive layer 110. The electrode layer 140 includes a plurality of etched anodes, each of which is connected to a driving circuit. When the array substrate 10 is fabricated into a display panel, each anode is used to output a driving current to one light emitting pixel.
In one embodiment, in the array substrate 10, the protection layer 130 includes at least one of an organic film layer and an inorganic film layer. In other embodiments, the material of the protection layer 130 may also be indium tin oxide. Specifically, the protective layer 130 should be insoluble in the etching solution used to etch the electrode layer 140. Generally, the etching solution may be at least one of oxalic acid, acetic acid, and nitric acid. The etching solution can be prepared by mixing oxalic acid, acetic acid and nitric acid in a certain proportion. The electrode layer 140 is typically a metal layer and an etching solution is used to etch the metal layer. Therefore, the protection layer 130 may be an organic film layer or an inorganic film layer that is insoluble in the etching solution, may be a composite film structure of the organic film layer and the inorganic film layer, and may be indium tin oxide.
In one embodiment, the thickness of the protection layer 130 of the array substrate 10 ranges from 200 angstroms to 400 angstroms. It is understood that the thickness of the protection layer 130 refers to a vertical distance from the surface of the protection layer 130 far away from the metal isolation layer 120 to the surface of the protection layer 130 close to the metal isolation layer 120. The thickness of the protection layer 130 may be 200 angstroms, 400 angstroms, 250 angstroms, 300 angstroms, or 350 angstroms.
In one embodiment, the sidewalls of the metal isolation layer 120 of the array substrate 10 include a first sidewall 1202 and a second sidewall 1204. Referring to fig. 8 and fig. 9, the first sidewall 1202 is a sidewall of the metal isolation layer 120 near the display region 102, and the second sidewall 1204 encloses the opening region 106. Or in other words, the first sidewall 1202 encloses the second sidewall 1204 and forms the open area 106 together with the second sidewall 1204.
In one embodiment, as shown in fig. 2, the metal isolation layer 120 of the array substrate 10 includes a first metal layer 122 and a second metal layer 124 which are stacked. The second metal layer 124 is located on a side of the first metal layer 122 away from the substrate 100. The passivation layer 130 covers at least the sidewalls of the first metal layer 122. The first metal layer 122 may be a metal with more active metal properties, such as metal aluminum; the second metal layer 124 may be a metal with stable metal properties, such as metallic titanium.
Further, the longitudinal section of the first metal layer 122 is rectangular or trapezoidal.
In one embodiment, the metal isolation layer 120 of the array substrate 10 further includes a third metal layer 126. The third metal layer 126 is located between the first metal layer 122 and the substrate 100, as can be seen in fig. 12. The material of the third metal layer 126 may be the same as that of the second metal layer 124, and is a metal with stable metal properties, such as metallic titanium.
In an embodiment, the present application further provides a method for manufacturing an array substrate, a schematic structural flow diagram of which is shown in fig. 3, including the following steps:
s100, a substrate 100 is provided, the substrate 100 includes a display region 102 and a non-display region 104.
Specifically, the substrate 100 is used to carry other devices of the array substrate 10. The substrate 100 may be made using a flexible material, such as a polyimide film; rigid materials such as clear glass may also be used for fabrication. As is known from the above description, the array substrate 10 prepared by the preparation method of the present application needs to have the opening region 106 where a camera or the like can be placed. Based on this, in the present embodiment, the substrate 100 is divided into a display region 102 and a non-display region 104. The display area 102 and the non-display area 104 are contiguous. After the array substrate 10 is fabricated into a display panel, the display area 102 is used for light emitting display, and the non-display area 104 may be used for placing a camera or an infrared sensor, a receiver, and the like. The location of the display area 102 and the non-display area 104 may be as shown in fig. 4.
S200, a metal isolation layer 120 is formed in the non-display region 104, and the metal isolation layer 120 encloses to form an opening region 106.
A metal isolation layer 120 is formed in the non-display region 104. The metal isolation layer 120 encloses the opening region 106. In other words, the metal isolation layer 120 is located between the opening region 106 and the display region 102, thereby spacing the opening region 106 from the display region 102. The locations of the display area 102, the open area 106 and the metal isolation layer 120 may be as shown in fig. 4. The metal isolation layer 120 of the non-display area 104 is used to isolate the display area 102 from the opening area 106. The opening area 106 of the non-display area 104 is used for placing a camera or an infrared sensor, a receiver and the like.
S300, forming a passivation layer 130, wherein the passivation layer 130 at least covers the sidewall of the metal isolation layer 120.
Specifically, in step S200, a metal isolation layer 120 has been formed on the substrate 100. The metal isolation layer 120 defines the opening region 106. In this step, a protection layer 130 is also formed on the metal isolation layer 120 to cover at least the sidewalls of the metal isolation layer 120. The protection layer 130 can prevent the etching solution from generating a displacement reaction with the sidewall of the metal isolation layer 120 in the subsequent process. Generally, the passivation layer 130 may be a non-metal material.
In the method for manufacturing the array substrate, the metal isolation layer 120 is formed on the substrate 100, and then the protective layer 130 at least covers the sidewall of the metal isolation layer 120. Therefore, according to the preparation method of the array substrate, when the electrode layer 140 is etched subsequently, the etching solution and the side wall of the metal isolation layer 120 are prevented from generating a displacement reaction to generate metal particles, so that the metal particles are prevented from influencing the normal operation of the array substrate 10. When the array substrate 10 prepared by the preparation method is used for preparing a display panel, poor display of the display panel caused by the existence of metal particles can be avoided.
Further, as shown in fig. 5, in step S200, the method may further include: a conductive layer 110 is formed in the display region 102.
Specifically, the conductive layer 110 is formed in the display region 102. The conductive layer 110 typically includes several driver circuits. When the array substrate 10 is manufactured into a display panel, each driving circuit is used for driving one light-emitting pixel to emit light. Each driver circuit typically includes a number of TFTs and capacitors. When the display panel works, the driving circuit can output driving current for driving the light-emitting pixels. And will not be described in detail.
Further, as shown in fig. 5, after step S300, the method may further include: s400, forming an electrode layer 140 covering the conductive layer 110, and etching the electrode layer 140 to obtain the array substrate 10.
Specifically, as known from the above description, the conductive layer 110 includes a plurality of driving circuits, and each driving circuit can drive one light-emitting pixel to emit light. Step S400 is used to prepare the anode between the driving circuit and the light emitting pixel. At this time, an electrode layer 140 covering the conductive layer 110 is prepared on the conductive layer 110, and the electrode layer 140 is etched to obtain a plurality of anodes, each of which is connected to a driving circuit. In the process of etching the electrode layer 140, since the protective layer 130 covers the sidewall of the metal isolation layer 120, the etching solution and the sidewall of the metal isolation layer 120 are prevented from generating a displacement reaction to generate metal particles, so that the metal particles are prevented from affecting the normal operation of the array substrate 10. When the array substrate 10 prepared by the preparation method is used for preparing a display panel, poor display of the display panel caused by the existence of metal particles can be avoided.
As is known from the above description, the passivation layer 130 formed in the step S300 at least covers the sidewalls of the metal isolation layer 120. The following describes a method for manufacturing the array substrate according to the present application from the two cases that the protective layer 130 completely covers the metal isolation layer 120 and the protective layer 130 only covers the sidewall of the metal isolation layer 120.
For the case where the protective layer 130 completely covers the metal isolation layer 120:
in an embodiment, as shown in fig. 6, the step S300 of the method for manufacturing an array substrate of the present application includes:
a protection layer 130 is formed, and the protection layer 130 surrounds the substrate 100 to completely cover the metal isolation layer 120.
Specifically, in the present embodiment, the metal isolation layer 120 is formed on the substrate 100. The passivation layer 130 covers the metal isolation layer 120 and surrounds the substrate 100, so that the metal isolation layer 120 is completely isolated from air. In other words, the protective layer 130 completely covers the metal isolation layer 120, so as to prevent the replacement reaction between the etching solution for etching the electrode layer 140 and the metal isolation layer 120 in step S400.
Further, the protective layer 130 includes at least one of an organic film layer and an inorganic film layer.
For the case where the protection layer 130 only covers the sidewalls of the metal isolation layer 120:
in another embodiment, as shown in fig. 7, the step S300 of the method for manufacturing an array substrate of the present application includes:
s310, forming an Indium Tin Oxide (ITO) film 1301, wherein the ITO film 1301 surrounds the substrate 100 to cover the metal isolation layer 120.
Specifically, after step S200, i.e., after the conductive layer 110 and the metal isolation layer 120 are formed on the substrate 100, the indium tin oxide film 1301 is formed on the surface of the metal isolation layer 120. The ito film 1301 covers the metal isolation layer 120 and surrounds the substrate 100, thereby isolating the metal isolation layer 120 from air. In other words, the indium tin oxide film 1301 completely covers the metal isolation layer 120.
S320, etching the ito film 1301, and removing the ito film 1301 covering the surface of the metal isolation layer 120 away from the substrate 100.
The idea of this embodiment is: the ito film 1301 completely covering the metal isolation layer 120 is formed, and then the ito film 1301 is etched to obtain the passivation layer 130 covering only the sidewall of the metal isolation layer 120. The material of the passivation layer 130 is an indium tin oxide film. Therefore, in this step, the ito film 1301 may be etched through an etching process to remove the ito film 1301 covered on the surface of the metal isolation layer 120 away from the substrate 100, so that the protection layer 130 only covers the sidewalls of the metal isolation layer 120. The indium tin oxide film 1301 is a semiconductor film. When the ito film 1301 is used to form the protection layer 130, the protection layer 130 only covers the sidewalls of the metal isolation layer 120, so as to prevent the protection layer 130 from short circuit during the operation of the array substrate 10.
It should be understood that, in the present embodiment, the material of the protection layer 130 is an indium tin oxide film, and therefore, the indium tin oxide film is not dissolved in the etching solution for etching the electrode layer 140.
In a specific embodiment, when the indium tin oxide film 1301 is etched through an etching process, the indium tin oxide film 1301 can be etched through a yellow etching process.
In another embodiment, the indium tin oxide film 1301 can also be etched by an etching solution. At this time, the etching solution used for etching the indium tin oxide film 1301 should not etch the metal isolation layer 120, so as to avoid the process of etching the indium tin oxide film 1301 from damaging the metal isolation layer 120.
In an embodiment, when the protection layer 130 is made of the ito film 1301, the method for manufacturing the array substrate of the present application may further include, after the step S320:
s330, baking the indium tin oxide film 1301 to form the protective layer 130 with a polycrystalline structure.
That is, after the indium tin oxide film 1301 is etched to remove the indium tin oxide film 1301 covering the surface of the metal isolation layer 120 away from the substrate 100, the indium tin oxide film 1301 can be baked to polycrystallize the indium tin oxide. The indium tin oxide of the polycrystalline structure is not etched by the etching solution formed by combining oxalic acid, acetic acid and nitric acid, and the replacement reaction between the etching solution and the side wall of the metal isolation layer 120 can be avoided.
Specifically, when the passivation layer 130 is made of the ito film 1301, the ito film may be baked at 250 degrees c for more than half an hour, so that the ito film has a polycrystalline structure.
It should be understood that, in the above embodiment, for the case that the protection layer 130 only covers the sidewalls of the metal isolation layer 120, only the specific embodiment that the protection layer 130 is made of the indium tin oxide film 1301 is described. However, this does not mean that the passivation layer 130 only covers the sidewalls of the metal isolation layer 120, and the material of the passivation layer 130 can be only indium tin oxide. In fact, when the protection layer 130 is an organic film or an inorganic film, it may only cover the sidewalls of the metal isolation layer 120. The present invention is directed to the above embodiments, when a semiconductor material such as indium tin oxide is used as the protection layer 130, the protection layer 130 only covers the sidewall of the metal isolation layer 120, so as to reduce the risk of short circuit caused by the protection layer 130.
In one embodiment, in the method for manufacturing the array substrate of the present application, the thickness of the protective layer 130 ranges from 200 a to 400 a.
In one embodiment, as shown in fig. 8 and 9, in the method for manufacturing an array substrate of the present application, the sidewalls of the metal isolation layer 120 include a first sidewall 1202 and a second sidewall 1204, wherein the first sidewall 1202 encloses the second sidewall 1204, and forms the opening region 106 together with the second sidewall 1204.
Specifically, in the present embodiment, the metal isolation layer 120 is located in the non-display region 104 of the substrate 100 and includes a first sidewall 1202 and a second sidewall 1204. The first sidewall 1202 of the metal isolation layer 120 is closer to the display region 102, and the second sidewall 1204 encloses the opening region 106.
In one embodiment, as shown in fig. 10 or 11, the metal isolation layer 120 includes a first metal layer 122 and a second metal layer 124 that are stacked. The second metal layer 124 is located on a side of the first metal layer 122 away from the substrate 100, and the protective layer 130 covers at least a sidewall of the first metal layer 122.
Specifically, the metal isolation layer 120 includes a first metal layer 122 and a second metal layer 124 that are stacked. The first metal layer 122 may be a metal with more active metal properties, such as metal aluminum; the second metal layer 124 may be a metal with stable metal properties, such as metallic titanium. Thus, the forming of the metal isolation layer 120 in the non-display region 104 in the step S200 may specifically include:
s210, a first metal layer 122 is formed on the non-display region 104 of the substrate 100.
S220, a second metal layer 124 is formed on the first metal layer 122 to cover the first metal layer 122.
Here, the coverage of the second metal layer 124 may be the same as that of the first metal layer 122. In other words, an orthographic projection of the second metal layer 124 on the substrate 100 overlaps with an orthographic projection of the first metal layer 122 on the substrate 100. As is known from the above description, the metal isolation layer 120 encloses the non-display region 104 to form the opening region 106. Therefore, the first metal layer 122 and the second metal layer 124 should also surround the non-display region 104 and together form the opening region 106.
S230, performing a lateral etching on the first metal layer 122 to make the coverage of the first metal layer 122 on the substrate 100 fall within the coverage of the second metal layer 124 on the substrate 100, thereby forming the metal isolation layer 120.
Side etching refers to etching the first metal layer 122 from the sidewall of the first metal layer 122. Since the material of the first metal layer 122 may be aluminum metal, the first metal layer 122 may also be etched by using an etching solution. The etching solution for etching the first metal layer 122 may also be a mixed solution of oxalic acid, acetic acid, and nitric acid. Here, when the first metal layer 122 is etched, the first metal layer 122 may be etched from only one sidewall of the first metal layer 122, or the first metal layer 122 may be etched from both sidewalls of the first metal layer 122. After the first metal layer 122 is etched, the metal isolation layer 120 is formed.
When the first metal layer 122 is etched from only one sidewall of the first metal layer 122, the sidewall of the opening region 106 may be formed by surrounding the first metal layer 122, i.e., the second sidewall 1204 of the first metal layer 122. Fig. 10 shows a schematic diagram of etching the first metal layer 122 from one sidewall of the first metal layer 122 and cladding with the protective layer 130. At this time, the longitudinal section of the first metal layer 122 may be trapezoidal. When the first metal layer 122 is etched from both sidewalls of the first metal layer 122, i.e., when the first metal layer 122 is etched from the first sidewall 1202 and the second sidewall 1204 of the first metal layer 122, respectively, the longitudinal section of the first metal layer 122 may have an inverted trapezoid shape or a rectangular shape. Fig. 11 shows a schematic diagram of etching the first metal layer 122 from both sidewalls of the first metal layer 122 and cladding with the protective layer 130.
In the present application, the passivation layer 130 covers at least the sidewall of the first metal layer 122.
As known from the above description, the first metal layer 122 is a metal with relatively active metal properties, such as metal aluminum. The second metal layer 124 is a metal with relatively stable metal properties, such as metallic titanium. The electrode layer 140 needs to be etched to form a plurality of anodes, so the electrode layer 140 can also be a metal with more active metal properties, such as metallic silver. As such, the etching solution does not damage the second metal layer 124 when the etching solution is used to etch the first metal layer 122. Therefore, when the electrode layer 140 is etched, the metal property of the second metal layer 124 is relatively stable, and the protective layer 130 can only cover the sidewall of the first metal layer 122, so that the occurrence of the displacement reaction can be avoided.
Further, as shown in fig. 12 or fig. 13, in the method for manufacturing an array substrate of the present application, the metal isolation layer 120 further includes a third metal layer 126. The third metal layer 126 is located between the first metal layer 122 and the substrate 100.
Specifically, the metal isolation layer 120 includes a third metal layer 126, a first metal layer 122, and a second metal layer 124, which are stacked. The material of the third metal layer 126 may be the same as that of the second metal layer 124, and is a metal with stable metal properties, such as metallic titanium. In this way, the step S200 of forming the metal isolation layer 120 in the non-display region 104 may further include, before the step S210:
s201, a third metal layer 126 is formed on the non-display region 104 of the substrate 100.
Here, the coverage of the third metal layer 126 may be the same as that of the second metal layer 124. In other words, the orthographic projection of the third metal layer 126 on the substrate 100 overlaps the orthographic projection of the second metal layer 124 on the substrate 100. As is known from the above description, the metal isolation layer 120 encloses the non-display region 104 to form the opening region 106. Therefore, the third metal layer 126 should also surround the opening region 106 in the non-display region 104.
In this case, step S210 may specifically be: the first metal layer 122 is formed on the surface of the third metal layer 126 away from the substrate 100. For the rest, reference is made to the above description and no further description is given. When the metal isolation layer 120 includes the stacked third metal layer 126, the first metal layer 122, and the second metal layer 124, "side-etching the first metal layer 122" in the step S230, the first metal layer 122 may be etched from only one sidewall of the first metal layer 122, or the first metal layer 122 may be etched from two sidewalls of the first metal layer 122. Fig. 12 shows a schematic diagram in which the first metal layer 122 is etched from both sidewalls of the first metal layer 122, and the sidewalls of the first metal layer 122 are coated with the protective layer 130. Fig. 13 shows a schematic diagram in which the first metal layer 122 is etched from both sidewalls of the first metal layer 122, and the outer surface of the metal isolation layer 120 is coated with the protective layer 130.
In one embodiment, the present application further provides a display panel including the array substrate 10 as described in any one of the above embodiments.
Specifically, the display panel includes an array substrate 10, light emitting pixels on the array substrate 10, and an encapsulation layer for encapsulating the light emitting pixels. Wherein, this array substrate 10 includes: a substrate 100 including a display region 102 and a non-display region 104; a conductive layer 110 in the display region 102; a metal isolation layer 120 located in the non-display region 104, wherein the metal isolation layer 120 encloses to form an opening region 106; a passivation layer 130 at least covering the sidewall of the metal isolation layer 120; and an electrode layer 140 covering the conductive layer 110.
In an embodiment, the present application further provides a display device, which includes the display panel in the above embodiments, and details are not repeated.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. An array substrate, comprising:
a substrate including a display region and a non-display region;
the metal isolation layer is positioned in the non-display area and forms an opening area in an enclosing mode;
and the protective layer at least coats the side wall of the metal isolation layer.
2. The array substrate of claim 1, wherein the protective layer comprises at least one of an organic film layer and an inorganic film layer.
3. The array substrate of claim 1 or 2, wherein the protective layer has a thickness ranging from 200 to 400 angstroms.
4. The array substrate of claim 1, wherein the material of the protective layer comprises indium tin oxide.
5. The array substrate of claim 1, wherein the metal isolation layer comprises a first metal layer and a second metal layer which are stacked, the second metal layer is located on the side of the first metal layer away from the substrate, and the material of the first metal layer comprises aluminum;
the protective layer at least covers the side wall of the first metal layer.
6. The array substrate of claim 5, wherein the first metal layer has a rectangular or trapezoidal longitudinal cross-section in a direction perpendicular to the substrate.
7. The array substrate of claim 5, wherein the protective layer surrounds the substrate to completely cover the metal isolation layer.
8. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a display area and a non-display area;
forming a metal isolation layer in the non-display area, wherein the metal isolation layer surrounds to form an opening area;
and forming a protective layer, wherein the protective layer at least covers the side wall of the metal isolation layer.
9. The method for manufacturing an array substrate according to claim 8, wherein the forming a protection layer, the protection layer covering at least a sidewall of the metal isolation layer, comprises:
and forming a protective layer, wherein the protective layer and the substrate are enclosed so as to completely cover the metal isolation layer.
10. The method for manufacturing an array substrate according to claim 8, wherein the forming a protection layer, the protection layer covering at least a sidewall of the metal isolation layer, comprises:
forming an indium tin oxide film, wherein the indium tin oxide film and the substrate surround to coat the metal isolation layer;
etching the indium tin oxide film, and removing the indium tin oxide film covered on the surface of the metal isolation layer, which is far away from the substrate;
and baking the indium tin oxide film to form a protective layer with a polycrystalline structure.
CN202010603766.4A 2020-06-29 2020-06-29 Array substrate and preparation method thereof Pending CN111653687A (en)

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