CN110112205B

CN110112205B - Display substrate, manufacturing method thereof and organic light emitting diode display device

Info

Publication number: CN110112205B
Application number: CN201910524464.5A
Authority: CN
Inventors: 田宏伟; 牛亚男; 李栋; 刘明; 刘政
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-06-18
Filing date: 2019-06-18
Publication date: 2021-04-09
Anticipated expiration: 2039-06-18
Also published as: WO2020253336A1; CN110112205A

Abstract

The disclosure relates to a display substrate, a method of manufacturing the same, and an organic light emitting diode display device. The display substrate includes: the array substrate comprises a display area, wherein the display area comprises a pixel area and a non-pixel area surrounding the pixel area; the convex structure is positioned on the array substrate along a first direction and is positioned in the non-pixel area, and the first direction is the light emergent direction of the display substrate or the opposite direction of the light emergent direction; the first metal layer is positioned on the convex structure along the first direction and is in conductive connection with the working voltage end; the first planarization layer is positioned on the array substrate along a first direction; a plurality of functional layers and cathode layers sequentially disposed on the first planarizing layer along a first direction; wherein the cathode layer is electrically connected to the first metal layer through the via hole.

Description

Display substrate, manufacturing method thereof and organic light emitting diode display device

Technical Field

The disclosure relates to a display substrate, a method of manufacturing the same, and an organic light emitting diode display device.

Background

Organic electroluminescent displays (OLEDs for short) are becoming the mainstream of the Display field by virtue of their excellent properties such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility, and can be widely applied to terminal products such as smart phones, tablet computers, televisions, and the like. Among them, flexible OLEDs are becoming mainstream products in OLEDs because they can meet the requirements of various special structures.

IR-drop (IR-drop) refers to the phenomenon of voltage drops or rises in the power and ground networks that occur in electrical circuits. With the development of flexible processes, an increase in display size, an increase in display resolution, a reduction in line width, and the like have a significant influence on IR-Drop. In order to secure the transmittance of the cathode electrode located in the pixel region, the cathode electrode in the related art is not generally formed thick, and the cathode electrode generally employs a current conduction path from the periphery to the center, which makes the resistance of the cathode electrode itself relatively larger, and the resistance has a greater influence on the IR-Drop as the display area increases. Based on the difference of the voltage and the current of different areas, the display brightness of each area is different, and the corresponding display effect has obvious difference, which affects the viewing experience of consumers.

In the related art, when a display circuit with a larger area is faced, an auxiliary cathode is often used to overcome the IR-Drop caused by the excessive cathode resistance.

Disclosure of Invention

In one aspect of the present disclosure, there is provided a display substrate including:

the array substrate comprises a display area, wherein the display area comprises a pixel area and a non-pixel area surrounding the pixel area;

the convex structure is positioned on the array substrate along a first direction and is positioned in the non-pixel region, and the first direction is the light emergent direction of the display substrate or the opposite direction of the light emergent direction;

the first metal layer is positioned on the convex structure along the first direction and is in conductive connection with a working voltage end;

a first planarization layer on the array substrate along the first direction;

a plurality of functional layers and a cathode layer sequentially disposed on the first planarizing layer along the first direction,

wherein the cathode layer is electrically connected to the first metal layer through a via.

In some embodiments, the via is disposed in at least one of the plurality of functional layers and the first planarization layer, and an orthographic projection of the via on the array substrate at least partially coincides with an orthographic projection of the protruding structure on the array substrate,

in some embodiments, the cathode layer is in direct contact with the first metal layer within the via.

In some embodiments, the plurality of functional layers comprises:

and the second metal layer is positioned on the first metal layer along the first direction, is electrically connected with the first metal layer and is in direct contact with the cathode layer through the through hole.

In some embodiments, the plurality of functional layers further comprises:

a pixel defining layer on the second metal layer along the first direction;

an organic light emitting layer on the pixel defining layer along the first direction;

wherein the via hole is disposed within the pixel defining layer and the organic light emitting layer.

In some embodiments, the display substrate further comprises:

and the anode layer is positioned on the first planarization layer along the first direction and is arranged on the same layer as the second metal layer.

In some embodiments, the maximum height of the protruding structure relative to the array substrate is 1200nm to 3000 nm.

In some embodiments, the array substrate includes:

a substrate; and

a thin film transistor on the substrate, the thin film transistor including a gate layer and a first source drain layer,

the first source drain layer and the first metal layer are arranged on the same layer.

In some embodiments, the display substrate further comprises:

a substrate;

the thin film transistor comprises a gate layer and a first source drain layer; and

the interlayer insulating layer is positioned between the grid layer and the first source drain layer;

wherein the protrusion structure is located on the interlayer insulating layer.

In some embodiments, the array substrate further includes a bending region, the bending region is provided with a groove and a filling material located in the groove, and the filling material is the same as the material of the protruding structure.

In some embodiments, the array substrate includes:

a substrate;

the thin film transistor comprises a gate layer, a second source drain layer and a first source drain layer;

the interlayer insulating layer is positioned between the grid layer and the second source drain layer; and

the second planarization layer is positioned on the interlayer insulating layer along the first direction and covers the second source drain layer;

the first source drain electrode layer and the protruding structure are located on the second planarization layer, and a source electrode and a drain electrode of the first source drain electrode layer are electrically connected with a source electrode and a drain electrode of the second source drain electrode layer respectively.

In some embodiments, the raised structures are the same material as the second planarizing layer.

In some embodiments, the display substrate comprises a plurality of raised structures on the second planarization layer; the array substrate comprises a bending area, the bending area is provided with a groove and filling materials located in the groove, one part of the plurality of protruding structures is the same as the second planarization layer in material, and the other part of the plurality of protruding structures is the same as the filling materials in material.

In one aspect of the present disclosure, there is provided a method of manufacturing a display substrate, including:

providing an array substrate comprising a display area, wherein the display area comprises a pixel area and a non-pixel area surrounding the pixel area;

forming a convex structure on a non-pixel region of the array substrate;

forming a first metal layer which is in conductive connection with a working voltage end on the protruding structure;

forming a first planarization layer on the array substrate;

sequentially forming a plurality of functional layers and cathode layers on the first planarization layer;

wherein, before forming the cathode layer, further comprising:

forming via holes in at least one of the plurality of functional layers and the first planarizing layer, such that the cathode layer is electrically connected to the first metal layer through the via holes.

In some embodiments, when the via hole is formed, an orthographic projection of the via hole on the array substrate is at least partially overlapped with an orthographic projection of the protruding structure on the array substrate.

In some embodiments, the operation of forming the first planarizing layer includes:

forming a planarization material layer on the array substrate, and enabling the planarization material layer to cover the first metal layer;

adjusting a first material thickness of a processing area of the planarization material layer to form the first planarization layer, wherein the first material thickness is smaller than a second material thickness of the planarization material layer, the second material thickness is located on the periphery of the processing area, and the processing area is at least a part of an orthographic projection of the protruding structure on the planarization material layer.

In some embodiments, the operation of forming the via hole comprises:

and forming via holes in the functional layers and the first planarization layer to expose the part of the first metal layer at the bottom of the via holes.

removing material of a processing area of the planarization material layer to expose the first metal layer, wherein the processing area is at least a part of the planarization material layer, which is located on an orthographic projection of the protruding structure on the planarization material layer.

In some embodiments, the operation of forming the plurality of functional layers comprises:

forming a second metal layer electrically connected to the first metal layer on the first metal layer;

forming a pixel defining layer on the second metal layer;

forming an organic light emitting layer on the pixel defining layer;

wherein the operation of forming the via hole comprises:

and forming via holes in the organic light emitting layer and the pixel defining layer, and exposing the part of the second metal layer at the bottom of the via holes, so that the cathode layer is directly contacted with the second metal layer through the via holes.

In some embodiments, the operation of forming the via hole comprises:

and forming the via holes in the functional layers, and exposing the parts of the first metal layers at the bottoms of the via holes.

In some embodiments, the method of manufacturing further comprises:

and forming an anode layer on the first planarization layer, wherein the anode layer and the second metal layer are formed by the same patterning process.

In some embodiments, the step of providing the array substrate comprises:

providing a substrate;

forming a thin film transistor on the substrate, wherein the thin film transistor comprises a gate layer and a first source drain layer,

the first source drain layer and the first metal layer are formed through the same composition process.

In some embodiments, the step of providing the array substrate comprises:

providing a substrate;

forming a thin film transistor on the substrate, wherein the thin film transistor comprises a grid layer and a first source drain layer;

when the thin film transistor is formed, an interlayer insulating layer is formed on the grid layer, and the protruding structure is formed on the interlayer insulating layer.

In some embodiments, the array substrate further includes a bending region, and the manufacturing method further includes:

forming a groove in the bending area;

filling a filling material into the groove;

wherein the protruding structure and the filling material are formed by the same patterning process.

In some embodiments, the operation of providing the array substrate includes:

providing a substrate;

forming a thin film transistor on the substrate, wherein the thin film transistor comprises a gate layer, a second source drain layer and a first source drain layer;

when a thin film transistor is formed, forming an interlayer insulating layer on the grid layer, forming a second source drain layer on the interlayer insulating layer, forming a second planarization layer on the interlayer insulating layer, and enabling the second planarization layer to cover the second source drain layer;

the protruding structure and the first source drain electrode layer are formed on the second planarization layer, and a source electrode and a drain electrode of the first source drain electrode layer are electrically connected with a source electrode and a drain electrode of the second source drain electrode layer respectively.

In some embodiments, the raised structures are formed by the same patterning process as the second planarizing layer.

In some embodiments, the operation of providing the array substrate includes:

providing a substrate;

wherein, the array substrate also comprises a bending area, and the manufacturing method also comprises the following steps:

forming a groove in the bending area;

filling a filling material into the groove;

wherein the operation of forming the protrusion structure comprises:

and forming a plurality of protruding structures on the second planarization layer, wherein one part of the plurality of protruding structures and the filling material are formed through the same patterning process, and the other part of the plurality of protruding structures and the second planarization layer are formed through the same patterning process.

In one aspect of the present disclosure, an organic light emitting diode display device is provided, which includes the aforementioned display substrate.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 is a schematic view of a display area and common electrode connections in one embodiment of a display substrate according to the present disclosure;

2-6 are respectively schematic structural diagrams of some embodiments of a display substrate according to the present disclosure;

FIG. 7 is a schematic flow chart diagram illustrating one embodiment of a method of fabricating a display substrate according to the present disclosure;

8-10 are schematic flow diagrams of a method of fabricating a display substrate according to some embodiments of the present disclosure, respectively, from a step of forming a first planarization layer to a step of forming a via;

FIG. 11 is a schematic flow chart illustrating a bending region process in one embodiment of a method of manufacturing a display substrate according to the present disclosure;

FIG. 12 is a schematic flow chart diagram illustrating another embodiment of a method of fabricating a display substrate according to the present disclosure;

fig. 13(a) -13 (k) are schematic diagrams of a manufacturing process according to one embodiment of a display substrate of the present disclosure.

It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.

All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In order to realize the auxiliary cathode, some related technologies remove the film layer under the cathode layer in the display area by laser or other methods, and then connect the cathode layer with a circuit having a lower resistance and electrically connected to the common electrode terminal, thereby reducing the IR-Drop caused by the excessive cathode resistance.

In the related art, it is necessary to remove a thick film layer under the cathode layer so as to expose a wiring required to be electrically connected to the cathode layer. Taking laser removal as an example, the thicker the film layer to be removed, the more film layer materials to be removed, which results in more products in the removal process, and the more products are liable to have adverse effects on the light emitting film layer for encapsulation and evaporation, thereby affecting the yield of the display substrate. On the other hand, when a film layer under the cathode layer is removed, a large step difference between the removed region and the non-removed region may be caused, a crack is easily generated when the cathode layer is formed, and the selection of the material of the cathode layer is also limited to some extent.

In view of this, embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and an organic light emitting diode display device, which can improve a climbing angle of a cathode layer at a via hole portion.

FIG. 1 is a schematic diagram of a display area and a common electrode connection according to one embodiment of a display substrate of the present disclosure.

Referring to fig. 1, in some embodiments, the display substrate includes an array substrate 30. The array substrate 30 may include a display region 10 and other regions implementing a non-display function. The display area 10 of the array substrate 30 may be provided with a plurality of pixel units to realize a display function. The display region 10 includes a pixel region 11 for disposing a pixel unit and a non-pixel region 12 surrounding the pixel region 11. The non-pixel region 12 may be used to define the range of the pixel region 11.

In the light emitting direction of the display substrate of fig. 1, a negative power signal layer 20 may be disposed at the periphery of the display region 10 of the array substrate 30, and the negative power signal layer 20 is electrically connected to the cathode layer of the display substrate and may be electrically connected to an operating voltage terminal (e.g., Vss) through a terminal 21.

In order to reduce the IR-Drop between the negative power signal layer 20 and the cathode of the pixel unit disposed in the display area 10, in some embodiments, the resistance of the negative power signal layer to the cathode layer may be reduced by using an auxiliary cathode, for example, a metal layer that is conductive to the operating voltage end is disposed in the display area 10 of the array substrate 30, and a plurality of vias 80 are disposed in the non-pixel area 12 to electrically connect the cathode layer and the metal layer below the vias. In this way, the resistance between the cathode of the pixel cell and the operating voltage terminal can be reduced, effectively reducing the IR Drop. The number and the arrangement position of the via holes 80 may be designed according to the pixel ratio, for example, the relationship between the number of the via holes 80 and the number of the pixels in the display area 10 is set to 1:4 to 1: 400. The adjacent via holes 80 may be arranged at intervals of 4-400 pixels. The plurality of via holes 80 may be arranged in a regular or irregular distribution according to the shape of the display area 10.

Fig. 2-6 are each a schematic structural diagram of some embodiments of a display substrate according to the present disclosure.

Referring to fig. 2-4, in some embodiments, a display substrate includes: the array substrate 30, the protrusion structure 40, the first metal layer 22, the first planarization layer 50, the plurality of functional layers, and the cathode layer 70. The protruding structure 40 is located on the array substrate 30 along a first direction (i.e., a vertical direction from bottom to top in fig. 2 to 4), and is located in the non-pixel region. The first direction may be a light emitting direction of the display substrate or a direction opposite to the light emitting direction of the display substrate. For example, for a display substrate of top emission type (i.e., emitting light from the cathode side), the first direction is the light emitting direction of the display substrate. In the case of a display substrate of the bottom emission type (i.e., light emitted from the anode side), the first direction is opposite to the light emission direction of the display substrate.

The protrusion structure 40 protrudes upward with respect to the array substrate 30. The shape of the raised structures 40 may be circular, oval, or polygonal. The material of the bump structure 40 may include at least one of silicon oxide, silicon nitride, and polyimide. Referring to fig. 1, the number of the protruding structures 40 may be determined according to the number of the vias 80 distributed in the display area, for example, the number of the protruding structures 40 is equal to or less than the number of the vias 80. The bump structures 40 may be arranged on the array substrate 30 along at least one second direction perpendicular to the first direction.

The maximum height h1 of the protrusion structure 40 relative to the array substrate may be determined according to one or more of the thickness of the first planarization layer on the array substrate 30, the thickness of the plurality of functional layers, and the climbing capability of the cathode layer, for example, h1 may be set to 1200nm to 3000 nm.

The first metal layer 22 is located on the protruding structure 40 along the first direction, and can be used as an auxiliary cathode to be electrically connected to the operating voltage terminal. Referring to fig. 2-4, the first metal layer 22 may also be located at the periphery of the protruding structure 40, integrally formed with the first metal layer 22 on the protruding structure 40.

A first planarizing layer 50 may be positioned on the array substrate 30 in a first direction for providing a planar surface for the formation of a plurality of functional layers. The composition of the various functional layers may vary in different embodiments. For example, in fig. 2, the plurality of functional layers include a pixel defining layer 61 and an organic light emitting layer 62. In fig. 3 and 4, the plurality of functional layers include a second metal layer 63, a pixel defining layer 61, and an organic light emitting layer 62. The organic light emitting layer 62 may include a light emitting function layer such as an electron injection layer, an electron blocking layer, an electron transport layer, a light emitting layer, a hole injection layer, a hole blocking layer, or a hole transport layer. The plurality of functional layers may also include functional layers that perform other functions, such as a touch sensor layer, etc. A plurality of functional layers and a cathode layer 70 may be sequentially disposed on the first planarization layer 50 in the first direction.

In order to electrically connect the cathode layer 70 with the first metal layer 22 thereunder, referring to fig. 2-4, in some embodiments vias 81, 82 or 83 are provided in at least one of the plurality of functional layers and the first planarizing layer 50. The cathode layer 70 is electrically connected to the first metal layer 22 through the via 81, 82 or 83, so as to reduce the resistance of the operating voltage terminal to the cathode layer by means of the auxiliary cathode.

The orthographic projection of the via 81, 82 or 83 on the array substrate 30 is at least partially overlapped with the orthographic projection of the protruding structure 40 on the array substrate 30, that is, the orthographic projection of the via 81, 82 or 83 on the array substrate 30 can be completely overlapped with the orthographic projection of the protruding structure 40 on the array substrate 30, or only partially overlapped. Here, the orthographic projection of the

vias

81, 82 and 83 on the array substrate 30 refers to the orthographic projection of the hole walls of the

vias

81, 82 and 83 on the array substrate 30 and the surrounding area. The orthographic projection of the protruding structure 40 on the array substrate 30 refers to the orthographic projection of the whole entity of the protruding structure 40 on the array substrate 30.

With this structure, at least a portion of the bottom of the via site can be formed above the bump structure 40, and accordingly, the height difference of the bottom with respect to the uppermost layer of the plurality of functional layers (e.g., the organic light emitting layer 62 in fig. 2) can be made relatively small. When the cathode layer 70 is formed, the height difference h2 between the via hole portion and the area around the via hole is relatively small, so that the climbing angle of the cathode layer at the via hole portion is improved, and the cathode layer is not easily broken at the via hole portion when formed.

In fig. 2, the via hole 81 penetrates the organic light emitting layer 62, the pixel defining layer 61, and the first planarizing layer 50 from top to bottom, so that the cathode layer 70 can be in direct contact with the first metal layer 22 within the via hole 81. Since the first metal layer 22 over the raised structure 40 is located at a higher position than the array substrate 30, when the first planarization layer 50 is formed, the material of the first planarization layer 50 over the raised structure 40 can be made thinner, or the planarization layer material over the raised structure 40 can be removed to expose the first metal layer 22.

In forming the first planarizing layer 50, if a smaller thickness of the planarizing layer material remains over the bump structures 40, after the functional layers are formed and before the cathode layer 70 is formed, the functional layers and the planarizing layer material over the bump structures 40 may be removed by laser or the like, so that the first metal layer 22 over the bump structures 40 is exposed at the bottom of the formed via holes 81.

In forming the first planarizing layer 50, if the planarizing layer material above the bump structures 40 has been removed, the via holes 81 may be formed by removing the functional layers by laser or the like after the formation of the functional layers is continued and before the cathode layer 70 is formed, so that the bottom of the via holes 81 expose the first metal layer 22 above the bump structures 40.

Compared with the related art that the thicker planarization layer material below the cathode layer needs to be removed after the organic light emitting layer is formed, some embodiments of the present disclosure reduce or remove the material above the protrusion structure when the first planarization layer 50 is formed, and after the organic light emitting layer is formed, the thickness of the planarization layer material that needs to be removed when the via hole is formed can be reduced, or the planarization layer material above the protrusion structure does not need to be removed, so that the product in the removing process can be reduced, the adverse effect of the product on the organic light emitting layer is reduced, and the yield of the display substrate is improved.

In fig. 3 and 4, the second metal layer 63 is located on the first metal layer 22 in the first direction and is electrically connected to the first metal layer 22. Referring to fig. 3, the second metal layer 63 may also be positioned on the first planarization layer 50 at the periphery of the first metal layer 22 and integrally formed with the second metal layer 63 on the first metal layer 22. In some embodiments, the display substrate further comprises an anode layer on the first planarizing layer 50 in the first direction, which can be used to form an anode of an OLED light emitting panel. The second metal layer 63 may be provided in the same layer as the anode layer. Thus, the second metal layer and the anode layer can be formed through the same patterning process when they are formed, so as to simplify the process. The second metal layer and the anode layer may be made of the same material, for example, a conductive material including a conductive oxide (e.g., indium tin oxide, indium zinc oxide, etc.) or a reflective metal (e.g., silver, aluminum, etc.). In fig. 3 and 4, the pixel defining layer 61 is on the second metal layer 63 along the first direction. The organic light emitting layer 62 is positioned on the pixel defining layer 61 in the first direction. The cathode layer 70 is positioned on the organic light emitting layer in the first direction. The material of the cathode layer may include at least one of Li, Ag, Ca, Al, Mg.

In fig. 3, a via 82 is disposed in the pixel defining layer 61 and the organic light emitting layer 62, and the cathode layer 70 is in direct contact with the second metal layer 63 through the via 82. The second metal layer 63 is reserved when the via hole is formed, so that on one hand, the thickness of the material below the cathode layer 60 which needs to be removed when the via hole is formed can be reduced, and the product generated in the removing process is reduced; on the other hand, when the material is removed, the first metal layer can be prevented from being removed by mistake, so that the reliability of the electric connection is improved.

In fig. 4, the via hole 83 is disposed in the second metal layer 63, the pixel defining layer 61 and the organic light emitting layer 62, and the cathode layer 70 is in direct contact with the first metal layer 22 through the via hole 83, which can further reduce the resistance between the cathode layer 70 and the first metal layer 22, thereby reducing the resistance between the cathode of the pixel unit and the operating voltage terminal, and effectively reducing the IR Drop.

Referring to fig. 5, in some embodiments, the array substrate includes a substrate 31 and a Thin Film Transistor (TFT) on the substrate 31. The thin film transistor includes a gate layer and a first source drain layer. The first Source Drain layer may be used to form a Source (Source pol) and a Drain (Drain pol) of the thin film transistor device. The thin film transistor may further include an active layer 91, and the source and drain

electrodes

94 and 95 of the first source and drain electrode layer are connected to the active layer 91. The first metal layer 22 may be disposed in the same layer as the first source-drain layer. In this way, the first metal layer 22 and the first source drain layer can be formed through the same patterning process when being formed, so as to simplify the processing procedure.

In fig. 5, the array substrate further includes a buffer layer 32, a gate insulating layer, an interlayer insulating layer 35, and the like. In a first direction from bottom to top, the buffer layer 32 of the array substrate is disposed on the substrate 31, the active layer 91 is disposed on the buffer layer 32, the first gate insulating layer 33 covers the active layer 91, the first gate layer 92 is disposed on the first gate insulating layer 33, the second gate insulating layer 34 covers the first gate layer 92, the second gate layer 93 is disposed on the second gate insulating layer 34, and the interlayer insulating layer 34 covers the second gate layer 93. In other embodiments, the thin film transistor may include a gate layer and a corresponding gate insulating layer.

The protrusion structure 40 in fig. 5 may be located on the surface of the interlayer insulating layer 35 in the first direction. The first source-drain layer may be also provided on the surface of the interlayer insulating layer 35, and the source electrode 94 and the drain electrode 95 in the first source-drain layer are connected to the active layer 91 through the interlayer insulating layer 35, the second gate insulating layer 34, and the first gate insulating layer 33. The source 94 and drain 95 in the first source drain layer may be provided in the same layer as the first metal layer 22. In addition, the source electrode 94 and the drain electrode 95 in the first source drain electrode layer may be formed of the same material as the first metal layer 22, for example, at least one of conductive materials such as molybdenum, copper, aluminum, gold, silver, or titanium, and may be formed through the same patterning process to save the process steps.

Referring to fig. 5, in some embodiments, the array substrate may further include a bending region 100 in addition to the display region 10, for realizing the flexibility of the display substrate. After the array substrate is formed, a groove penetrating the interlayer insulating layer 35, the second gate insulating layer 34, the first gate insulating layer 33 and the buffer layer 32 may be formed (for example, by an exposure-etching process) in the bending region 100, and the flexible substrate 31 is exposed at the bottom of the groove. The recess may be filled with a filling material 110, and the filling material 110 may be formed by the same patterning process as the protrusion structure 40. For example, in the substrate Bending (Pad-bonding) process, the convex structure 40 is formed while the Pad-bonding pattern is obtained by using a Halftone (Halftone) process. The filling material 110 and the protrusion structure 40 can both be made of polyimide, and the maximum height of the filling material 110 is 500-1200 nm, and the maximum height of the protrusion structure 40 is 1200-3000 nm, which is greater than the maximum height of the filling material relative to the array substrate.

Referring to fig. 6, in some embodiments, the array substrate includes a substrate 31, a thin film transistor, an interlayer insulating layer 35, and a second planarization layer 36. The thin film transistor comprises a grid layer, a second source drain layer and a first source drain layer. And the source electrode and the drain electrode of the second source drain electrode layer are respectively and electrically connected with the source electrode and the drain electrode of the first source drain electrode layer. The source and drain of the first source drain layer are both electrically connected to the active layer 91.

In fig. 6, the array substrate further includes a buffer layer 32, a gate insulating layer, and the like. In a first direction from bottom to top, the buffer layer 32 of the array substrate is disposed on the substrate 31, the active layer 91 is disposed on the buffer layer 32, the first gate insulating layer 33 covers the active layer 91, the first gate layer 92 is disposed on the first gate insulating layer 33, the second gate insulating layer 34 covers the first gate layer 92, the second gate layer 93 is disposed on the second gate insulating layer 34, and the interlayer insulating layer 34 covers the second gate layer 93. The buffer layer 32, the first gate insulating layer 33, the second gate insulating layer 34, the interlayer insulating layer 35, and the second planarizing layer 36 may be made of the same material or different materials. The material may include at least one of an oxide of silicon, a nitride of silicon, and polyimide. In other embodiments, the thin film transistor may include a gate layer and a corresponding gate insulating layer.

Referring to fig. 6, in some embodiments, the second source drain layer may be disposed on the interlayer insulating layer 35 along the first direction, i.e., the interlayer insulating layer 35 is located between the gate layer and the second source drain layer. The source electrode 94 'and the drain electrode 95' in the second source-drain electrode layer are connected to the active layer 91 through the interlayer insulating layer 35, the second gate insulating layer 34, and the first gate insulating layer 33. A second planarization layer 36 is located on the interlayer insulating layer 35 along the first direction and covers the second source and drain layers, and a protrusion structure 40' may be disposed on the second planarization layer 36. The bump structures 40' may be the same material as the second planarization layer 36. Accordingly, in order to simplify the process, the bump structure 40' may be formed through the same patterning process when the second planarization layer 36 is formed.

In fig. 6, a first source drain layer may be disposed on the second planarization layer 36, and a source 94 and a drain 95 of the first source drain layer are connected to a source 94 'and a drain 95' of the second source drain layer, respectively, through the second planarization layer 36. The source 94 and the drain 95 in the first source drain layer may be formed by the same patterning process as the first metal layer 22 to save the process steps.

Referring to fig. 5 and 6, in some embodiments, the material of the protrusion structure may be the same as the material of the portions in the display substrate. For example, the display substrate comprises a plurality of convex structures on the second planarization layer. The array substrate comprises a bending area, the bending area is provided with a groove and filling materials positioned in the groove, one part of the plurality of protruding structures is the same as the second planarization layer in material, and the other part of the plurality of protruding structures is the same as the filling materials in material.

Since the protruding structure may be made of the same material as the plurality of portions of the display substrate, the protruding structure may be formed through a process of manufacturing the corresponding portion of the display substrate, thereby reducing the number of manufacturing processes of the display substrate and improving the manufacturing efficiency. For example, for the plurality of protruding structures formed in the non-pixel region, a portion of the plurality of protruding structures and the filling material filled in the groove of the bending region may be formed through the same patterning process, and another portion of the plurality of protruding structures and the second planarization layer may be formed through the same patterning process.

FIG. 7 is a schematic flow chart diagram illustrating one embodiment of a method of fabricating a display substrate according to the present disclosure.

Referring to fig. 7, in some embodiments, a method of manufacturing a display substrate includes steps S100 to S700. In step S100, an array substrate including a display region including a pixel region and a non-pixel region surrounding the pixel region is provided. In step S200, a bump structure is formed on a non-pixel region of the array substrate. The maximum height of the protruding structure relative to the array substrate may be 1200nm to 3000 nm. In step S300, a first metal layer conductively connected to an operating voltage terminal is formed on the bump structure. In step S400, a first planarization layer is formed on the array substrate. In step S500, a plurality of functional layers are formed on the first planarization layer. In step S600, a via hole is formed in at least one of the plurality of functional layers and the first planarizing layer. When the via hole is formed, the orthographic projection of the via hole on the array substrate can be at least partially overlapped with the orthographic projection of the protruding structure on the array substrate. In step S700, a cathode layer is formed on the plurality of functional layers, and the cathode layer is electrically connected to the first metal layer through the via hole.

Fig. 8-10 are detailed flow diagrams from the step of forming the first planarizing layer to the step of forming the via hole, respectively, in some embodiments of a method of manufacturing a display substrate according to the present disclosure.

Referring to fig. 8, in some embodiments, step S400 may include step S410 and step S420. In step S410, a planarization material layer is formed on the array substrate and covers the first metal layer. In step S420, a first material thickness of a processing region of the planarization material layer is adjusted to form the first planarization layer, and the first material thickness is smaller than a second material thickness of the planarization material layer located at the periphery of the processing region. The processing area is at least a part of the planarization material layer, which is positioned on the orthographic projection of the convex structure on the planarization material layer.

After forming a plurality of functional layers in step S500, step S600 specifically includes step S610, forming via holes in the plurality of functional layers and the first planarizing layer to expose portions of the first metal layer at bottoms of the via holes. Since the material thickness of the processing region is adjusted to a smaller thickness in step S420, the material thickness to be removed in forming the via in step S610 is less and the product is less compared to the thicker planarization layer that needs to be removed in forming the via in the related art.

Referring to fig. 9, in some embodiments, step S400 may include step S410 and step S430. In step S410, a planarization material layer is formed on the array substrate and covers the first metal layer. In step S430, the material of the processing region of the planarization material layer is removed to expose the first metal layer. The processing area is at least a part of the planarization material layer, which is positioned on the orthographic projection of the convex structure on the planarization material layer.

After forming a plurality of functional layers in step S500, step S600 specifically includes step S620, forming via holes in the plurality of functional layers to expose portions of the first metal layer at the bottoms of the via holes. Since the material of the processing region is removed in step S430, compared to the thicker planarization layer that needs to be removed when forming the via in the related art, the first planarization layer does not need to be removed when forming the via in step S620, and therefore the material that needs to be removed has a smaller thickness and the product is less.

Referring to fig. 10, in some embodiments, step S400 may include step S410 and step S430. In step S410, a planarization material layer is formed on the array substrate and covers the first metal layer. In step S430, the material of the processing region of the planarization material layer is removed to expose the first metal layer. The processing area is at least a part of the planarization material layer, which is positioned on the orthographic projection of the convex structure on the planarization material layer.

In fig. 10, step S500 may specifically include step S510 to step S530. In step S510, a second metal layer electrically connected to the first metal layer is formed on the first metal layer. In step S520, a pixel defining layer is formed on the second metal layer. In step S530, an organic light emitting layer is formed on the pixel defining layer.

After forming the plurality of functional layers, step S600 specifically includes step S630, forming via holes in the organic light emitting layer and the pixel defining layer, and exposing a portion of the second metal layer located at the bottom of the via holes, so that the cathode layer directly contacts the second metal layer through the via holes.

Since the material of the processing region is removed in step S430, compared to the material of the thicker planarization layer that needs to be removed when forming the via hole in the related art, only the organic light emitting layer and the pixel defining layer need to be removed when forming the via hole in step S630, and the second metal layer and the first planarization layer do not need to be removed, so that the material that needs to be removed is less in thickness, and fewer products are generated. On the other hand, the first metal layer can be prevented from being removed by mistake when the material is removed, so that the reliability of the electric connection is improved.

In some embodiments, the step of providing the array substrate may include: providing a substrate, and forming a thin film transistor on the substrate, wherein the thin film transistor comprises a gate layer and a first source drain layer. The thin film transistor may further include an active layer, and the source and drain electrodes of the first source and drain electrode layer may be electrically connected to the active layer. The first source drain layer may be formed by the same patterning process as the first metal layer in the embodiments of fig. 8 to 10, so as to save the processing steps. In addition, in forming the thin film transistor, an interlayer insulating layer may be formed on the gate layer. The protrusion structure may be formed on the interlayer insulating layer.

In some embodiments, an anode layer may also be formed on the first planarization layer. The anode layer may be formed through the same patterning process as the second metal layer in the embodiment of fig. 9 and 10 to save the process steps.

FIG. 11 is a schematic flow chart illustrating a bending region process in one embodiment of a method of manufacturing a display substrate according to the present disclosure.

Referring to fig. 11, in some embodiments, the array substrate further includes a bending region. The manufacturing method may further include step S100' and step S700. In step S100', an array substrate including a display region and a bending region is provided, the display region including a pixel region and a non-pixel region surrounding the pixel region. Step S100' may be included in step S100. In step S700, a groove is formed in the bending region. Step S200 may include step S210 of filling the recess with a filling material and forming a protrusion structure on the non-pixel region of the array substrate through the same patterning process. Therefore, the convex structure can be formed simultaneously when the bending area is filled, and the working procedure is saved.

Fig. 12 is a schematic flow chart diagram of another embodiment of a method of manufacturing a display substrate according to the present disclosure.

Referring to fig. 12, in some embodiments, the operation of providing the array substrate may include: providing a substrate, and forming a thin film transistor on the substrate, wherein the thin film transistor comprises a gate layer, a second source drain layer and a first source drain layer. The thin film transistor may further include an active layer, and the source and drain electrodes of the second source and drain electrode layer may be electrically connected to the active layer. When the thin film transistor is formed, an interlayer insulating layer may be formed on the gate layer, the second source/drain layer may be formed on the interlayer insulating layer, and then a second planarizing layer may be formed on the interlayer insulating layer and may cover the second source/drain layer. The protruding structure and the first source drain electrode layer are formed on the second planarization layer, and a source electrode and a drain electrode of the first source drain electrode layer are electrically connected with a source electrode and a drain electrode of the second source drain electrode layer respectively. In order to save the process, the protrusion structure may be formed through the same patterning process as the second planarization layer. In other embodiments, the formation of the raised structures may also follow the formation of the second planarizing layer.

For example, in fig. 12, the step of providing the array substrate includes steps S110 to S190. In step S110, a substrate is provided, and a buffer layer is formed on the substrate. In step S120, an active layer is formed on the buffer layer. In step S130, a first gate insulating layer is covered on the active layer. In step S140, a first gate layer is formed on the first gate insulating layer. In step S150, a second gate insulating layer is covered on the first gate layer. In step S160, a second gate layer is formed on the second gate insulating layer. In step S170, an interlayer insulating layer is covered on the second gate layer. In step S180, a second source/drain layer is formed on the interlayer insulating layer, and a source and a drain in the second source/drain layer are connected to the active layer through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. In step S190, a second planarization layer is formed on the interlayer insulating layer, and the second planarization layer covers the second source/drain layer.

Step S200 may be independent of step S190, or may be combined with step S190, that is, when forming the second planarization layer, the raised structure located in the non-pixel region of the array substrate is formed through the same patterning process, so as to save the process. In other embodiments, when the non-pixel region forms a plurality of protruding structures, a portion of the plurality of protruding structures and the filling material are formed through the same patterning process, and another portion of the plurality of protruding structures and the second planarization layer are formed through the same patterning process.

A manufacturing process of an embodiment of the display substrate of the present disclosure will be described below with reference to fig. 13(a) to 13 (k). In fig. 13(a), a substrate 31 is provided. In fig. 13(b), a buffer layer 32 is formed on a substrate 31, and an active layer 91 is formed on the buffer layer 32. In fig. 13(c), the first gate insulating layer 33 is covered on the active layer 91, and the first gate insulating layer 33 is also covered on the buffer layer 32. Next, a first gate layer 92 is formed on the first gate insulating layer 33, and a second gate insulating layer is covered on the first gate layer 92, and the second gate insulating layer 34 is also covered on the first gate insulating layer 33. Then, a second gate layer 93 is formed on the second gate insulating layer 34, and an interlayer insulating layer 35 is covered on the second gate layer 93, the interlayer insulating layer 35 also covering the second gate insulating layer 34.

For a display substrate that needs to realize the bending function, the array substrate may include a display area and a bending area. In fig. 13(d), via holes a and B penetrating the interlayer insulating layer 35, the second gate insulating layer 34, and the first gate insulating layer 33 may be formed in the display region, and a groove C penetrating the interlayer insulating layer 35, the second gate insulating layer 34, the first gate insulating layer 33, and the buffer layer 32 may be formed in the bending region. The via A, B and the recess C may be formed in the same process or in different processes.

In fig. 13(e), the filling material 110 is filled into the groove C as a substrate bending pattern and the protrusion structure 40 is formed on the non-pixel region of the interlayer insulating layer 35 by a half-tone process. The filling material 110 and the protrusion structure 40 can both be made of polyimide, and the maximum height of the filling material 110 is 500-1200 nm and the maximum height of the protrusion structure 40 is 1200-3000 nm relative to the interlayer insulating layer 35.

In fig. 13(f), the first metal layer 22 and the first source-drain layer are formed on the interlayer insulating layer 35, and the first metal layer 22 is made to cover the bump structure 40. When the display substrate is formed, the first metal layer 22 can be electrically connected to the operating voltage terminal. Thus, the source electrode 94 and the drain electrode 95 in the first source drain electrode layer are electrically connected to the active layer 91 through the vias a and B, respectively, thereby forming a thin film transistor in the array substrate. The first metal layer 22 and the first source drain layer may be formed through the same patterning process. The first metal layer 22 may or may not cover the inflection regions.

In fig. 13(g), a planarization material layer 50 'is formed on the interlayer insulating layer 35 such that the planarization material layer 50' covers the first metal layer 22, the source electrode 94 and the drain electrode 95 of the first source drain layer. The planarizing material layer 50' may or may not cover the inflection regions. The planarization material layer 50' at different positions has different heights with respect to the interlayer insulating layer 35, wherein the region 51 at the upper side of the protrusion structure 40 is higher than other regions.

In fig. 13(h), the planarization material layer 50' is processed to form a more planar first planarization layer 50. In this process, the material of the processing region 51 of the planarization material layer 50' may be removed to expose the first metal layer 22.

In fig. 13(i), a second metal layer 63, a pixel defining layer 61, and an organic light emitting layer 62 are sequentially formed on the first planarizing layer 50. The second metal layer 63 covers the first metal layer 22, and is in direct contact with and electrically connected to the first metal layer 22. In forming the second metal layer 63, the anode layer may be formed through the same patterning process.

In fig. 13(j), a via hole D is formed at a portion of the pixel defining layer 61 and the organic light emitting layer 62 corresponding to the upper portion of the protrusion structure 40, and the second metal layer 63 at the bottom of the via hole D is exposed. In this case, the material to be removed when forming the via is thin, and the product is less.

In fig. 13(k), a cathode layer 70 is formed on the organic light emitting layer 62, and the cathode layer 70 can cover the sidewalls and the bottom of the via hole D, and is in direct contact and electrically connected with the second metal layer 63. The cathode layer 70 is thus able to establish an electrical connection with the operating voltage terminals via the second metal layer 63 and the first metal layer 22 above the respective raised structures 40, thereby performing the function of an auxiliary cathode.

The embodiments of the display substrate can be applied to an organic light emitting diode display device, and accordingly, the present disclosure also provides an organic light emitting diode display device including any of the embodiments of the display substrate. The organic light emitting diode display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, comprising:

a first planarization layer on the array substrate along the first direction;

the cathode layer is electrically connected with the first metal layer through a via hole, the array substrate further comprises a bending area, the bending area is provided with a groove and filling materials located in the groove, and the filling materials are the same as the materials of the protruding structures.

2. The display substrate of claim 1, wherein the via is disposed in at least one of the plurality of functional layers and the first planarizing layer, and an orthographic projection of the via on the array substrate at least partially coincides with an orthographic projection of the protruding structure on the array substrate.

3. The display substrate of claim 1, wherein the cathode layer is in direct contact with the first metal layer within the via.

4. The display substrate of claim 1, wherein the plurality of functional layers comprises:

5. The display substrate of claim 4, wherein the plurality of functional layers further comprises:

a pixel defining layer on the second metal layer along the first direction;

6. The display substrate of claim 4, further comprising:

7. The display substrate of claim 1, wherein a maximum height of the protrusion structure with respect to the array substrate is 1200nm to 3000 nm.

8. The display substrate of any one of claims 1 to 7, wherein the array substrate comprises:

a substrate; and

9. The display substrate according to any one of claims 1 to 7, further comprising:

a substrate;

wherein the protrusion structure is located on the interlayer insulating layer.

10. The display substrate of any one of claims 1 to 7, wherein the array substrate comprises:

a substrate;

11. The display substrate of claim 10, wherein the raised structures are the same material as the second planarizing layer.

12. The display substrate of claim 10, wherein the display substrate comprises a plurality of raised structures on the second planarization layer; a part of the plurality of protruding structures is the same as the material of the second planarization layer, and another part is the same as the material of the filling material.

13. A method of manufacturing a display substrate, comprising:

forming a convex structure on a non-pixel region of the array substrate;

forming a first planarization layer on the array substrate;

wherein, before forming the cathode layer, further comprising:

forming via holes in at least one of the plurality of functional layers and the first planarizing layer such that the cathode layer is electrically connected to the first metal layer through the via holes;

forming a groove in the bending area;

filling a filling material into the groove;

14. The manufacturing method according to claim 13, wherein when the via hole is formed, an orthographic projection of the via hole on the array substrate is at least partially overlapped with an orthographic projection of the protruding structure on the array substrate.

15. The manufacturing method of claim 13, wherein the operation of forming the first planarizing layer comprises:

16. The method of manufacturing of claim 15, wherein forming the via comprises:

17. The manufacturing method of claim 13, wherein the operation of forming the first planarizing layer comprises:

18. The manufacturing method according to claim 17, wherein the operation of forming the plurality of functional layers comprises:

forming a pixel defining layer on the second metal layer;

forming an organic light emitting layer on the pixel defining layer;

wherein the operation of forming the via hole comprises:

19. The method of manufacturing of claim 17, wherein forming the via comprises:

20. The manufacturing method according to claim 18, further comprising:

21. The method of manufacturing of any one of claims 13 to 20, wherein the step of providing the array substrate comprises:

providing a substrate;

22. The method of manufacturing of any one of claims 13 to 20, wherein the step of providing the array substrate comprises:

providing a substrate;

23. The method of manufacturing of any of claims 13 to 20, wherein providing the array substrate comprises:

providing a substrate;

24. The manufacturing method according to claim 23, wherein the convex structure is formed by the same patterning process as the second planarizing layer.

25. The method of manufacturing of any of claims 13 to 20, wherein providing the array substrate comprises:

providing a substrate;

wherein the operation of forming the protrusion structure comprises:

26. An organic light emitting diode display device comprising the display substrate according to any one of claims 1 to 12.