CN113488486A

CN113488486A - Array substrate manufacturing method and array substrate

Info

Publication number: CN113488486A
Application number: CN202110730557.0A
Authority: CN
Inventors: 陈发祥; 马应海; 邢汝博; 李骄阳
Original assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Current assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2021-10-08

Abstract

The application relates to a manufacturing method of an array substrate and the array substrate, wherein a barrier layer for providing an etching barrier in a subsequent process is formed in the same process for forming an active layer, the barrier layer and the barrier layer jointly form a semiconductor layer, then an inorganic layer covering the active layer and the barrier layer is formed, the inorganic layer is etched by taking the barrier layer as an end point to form a plurality of grooves, and an organic layer is deposited on one side of the inorganic layer far away from a substrate, so that the organic layer covers the inorganic layer while filling the grooves; the organic layer can provide a lower Young modulus for the array substrate than the inorganic layer, so that the flexibility of the array substrate manufactured by the manufacturing method is improved, and the array substrate is prevented from being broken due to the high Young modulus when being subjected to stress bending.

Description

Array substrate manufacturing method and array substrate

Technical Field

The invention relates to the technical field of display, in particular to a manufacturing method of an array substrate and the array substrate.

Background

An OLED (Organic light-emitting diode) display panel is widely popularized due to its advantages of low power consumption, high saturation, wide viewing angle, thin thickness, flexibility, and the like.

In the current trend, OLED display panels are being flexible. In the OLED display panel, the array substrate is generally made of an inorganic material, and when the inorganic film layer formed of the inorganic material is bent by stress, the inorganic film layer is broken due to a large young's modulus, which affects the flexibility of the array substrate.

Therefore, how to ensure the flexibility of the array substrate becomes a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of the above, it is necessary to provide a method for manufacturing an array substrate, which aims at the technical problem of how to ensure the flexibility of the array substrate, and further includes:

providing a substrate, and forming a semiconductor layer on one side of the substrate;

etching the semiconductor layer to form an active layer and a barrier layer which are arranged at intervals;

forming an inorganic layer covering the active layer and the barrier layer;

etching the inorganic layer along the direction towards the substrate by taking the barrier layer as an end point to form a plurality of grooves;

depositing an organic layer on the side of the inorganic layer far away from the substrate, so that the organic layer covers the inorganic layer while filling the groove;

the manufacturing method further includes:

and etching the inorganic layer along the direction towards the substrate to form a plurality of through holes by taking the barrier layer as an end point, and simultaneously etching the inorganic layer along the direction towards the substrate by taking the active layer as an end point to form a plurality of grooves.

In one embodiment, the step of forming the inorganic layer further comprises:

forming a first inorganic layer overlying the active layer and the barrier layer;

forming a first metal layer on one side of the first inorganic layer far away from the active layer;

injecting ions into the active layer through the first inorganic layer by using the first metal layer as a shield to form a source layer and a drain layer;

and forming a second inorganic layer on one side of the first metal layer, which is far away from the first inorganic layer, wherein the second inorganic layer covers the first metal layer.

In one embodiment, the step of forming the second inorganic layer further comprises:

forming a second metal layer on one side of the second inorganic layer far away from the first metal layer;

and a third inorganic layer is arranged on one side of the second metal layer far away from the second inorganic layer, and the third inorganic layer covers the second metal layer.

In one embodiment, the step of forming the third inorganic layer further comprises:

forming a third metal layer so that the third metal layer fills the groove and the through hole and covers the third inorganic layer;

etching the third metal layer, and reserving the third metal layer on the side of the source electrode layer away from the substrate and the side of the drain electrode layer away from the substrate to form a conductive pillar, wherein the conductive pillar fills the through hole and is at least partially arranged on the side of the third inorganic layer away from the substrate;

and depositing the organic layer, so that the organic layer fills the groove and covers the third inorganic layer and the third metal layer, and the surface of one side, close to the substrate, of the organic layer is coincided with the surface of one side, far away from the substrate, of the second barrier layer.

In the manufacturing method provided by the present application, the array substrate includes a thin film transistor and a storage capacitor, wherein:

the grid electrode of the thin film transistor is positioned on the first metal layer, the source electrode of the thin film transistor is positioned on the source electrode layer, and the drain electrode of the thin film transistor is positioned on the drain electrode layer; the first polar plate of the storage capacitor is positioned on the first metal layer, and the second polar plate of the storage capacitor is positioned on the second metal layer;

in the extending direction parallel to the plane of the substrate, the orthographic projection of the barrier layer on the substrate is positioned between the orthographic projection of the thin film transistor on the substrate and the orthographic projection of the storage capacitor on the substrate.

In the manufacturing method provided by the present application, the manufacturing method further includes:

and with the barrier layer as an end point, etching the inorganic layer along the direction towards the substrate to form a plurality of grooves, then carrying out hydrogenation treatment on the active layer, and depositing an organic layer on one side of the inorganic layer far away from the substrate, so that the inorganic layer is covered while the grooves are filled with the organic layer.

and carrying out hydrogenation treatment on the active layer, etching the inorganic layer along the direction towards the substrate by taking the barrier layer as an end point to form a plurality of grooves, and depositing an organic layer on one side of the inorganic layer far away from the substrate so as to fill the grooves with the organic layer and cover the inorganic layer at the same time.

The present application further provides an array substrate manufactured by the manufacturing method described in any one of the preceding embodiments, the array substrate including:

a substrate;

the semiconductor layer is arranged on one side of the substrate and comprises an active layer and a barrier layer which are arranged on the same layer, and the active layer and the barrier layer are arranged at intervals in the extending direction parallel to the plane of the substrate;

the inorganic layer is arranged on one side, far away from the substrate, of the active layer and the barrier layer, and the inorganic layer covers the active layer and the barrier layer;

the groove is formed in one side, away from the substrate, of the inorganic layer, and the bottom surface of the groove is overlapped with the surface, away from the substrate, of the barrier layer;

an organic layer filling the groove and covering the inorganic layer;

in the array substrate that this application still provided, still include:

the through hole is formed in one side, far away from the substrate, of the inorganic layer, and the bottom surface of the through hole coincides with the surface, far away from the substrate, of the active layer.

In one embodiment, the inorganic layer comprises a first inorganic layer disposed on a side of the semiconductor layer away from the substrate, and the first inorganic layer is disposed overlying the active layer and the barrier layer;

the first metal layer is arranged on one side of the first inorganic layer far away from the active layer, the orthographic projection of the first metal layer on the substrate does not overlap with the orthographic projection of the barrier layer on the substrate, and at least part of the orthographic projection of the first metal layer on the substrate falls within the range of the orthographic projection of the active layer on the substrate.

In one embodiment, the inorganic layer further comprises a second inorganic layer, the second inorganic layer is positioned on the side of the first inorganic layer far away from the semiconductor layer, and the second inorganic layer is arranged to cover the first metal layer;

the second metal layer is arranged on one side, far away from the first metal layer, of the second inorganic layer, the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate, and the orthographic projection of at least part of the second metal layer on the substrate covers the orthographic projection of the first metal layer on the substrate.

In one embodiment, the inorganic layer further comprises a third inorganic layer disposed on a side of the second metal layer remote from the second inorganic layer and covering the second metal layer;

the conductive posts fill the through holes and are at least partially located on one side, away from the substrate, of the third inorganic layer.

In one embodiment, the organic layer is disposed on a side of the third inorganic layer away from the substrate and sequentially penetrates through the third inorganic layer, the second inorganic layer and the first inorganic layer along a direction close to the substrate, and the organic layer covers the third inorganic layer and the conductive pillars;

in one embodiment, the array substrate includes a thin film transistor and a storage capacitor, wherein: the grid electrode of the thin film transistor is positioned on the first metal layer, the source electrode of the thin film transistor is positioned on the source electrode layer, and the drain electrode of the thin film transistor is positioned on the drain electrode layer; the first polar plate of the storage capacitor is positioned on the first metal layer, and the second polar plate of the storage capacitor is positioned on the second metal layer; in the extending direction parallel to the plane of the substrate, the orthographic projection of the barrier layer on the substrate is positioned between the orthographic projection of the thin film transistor on the substrate and the orthographic projection of the storage capacitor on the substrate.

According to the manufacturing method of the array substrate, the barrier layer for providing the etching barrier in the subsequent process is formed in the same process for forming the active layer, the barrier layer and the semiconductor layer jointly form the semiconductor layer, then the inorganic layer covering the active layer and the barrier layer is formed, the inorganic layer is etched by taking the barrier layer as an end point to form a plurality of grooves, and the organic layer is deposited on one side, far away from the substrate, of the inorganic layer, so that the organic layer covers the inorganic layer while filling the grooves; the organic layer can provide a lower Young modulus for the array substrate than the inorganic layer, so that the flexibility of the array substrate manufactured by the manufacturing method is improved, and the array substrate is prevented from being broken due to the high Young modulus when being subjected to stress bending.

Drawings

Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure;

fig. 2 is a schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 3 is another schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 4 is a further schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 5 is another schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 6 is a further schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 7 is another schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure;

fig. 8 is a further schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 9 is another schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 10 is a further schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 11 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure;

fig. 12 is another schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 13 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure;

fig. 14 is another schematic view illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of an array substrate according to an embodiment of the present application.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In view of the technical problems mentioned in the background art, the inventors found through research that, in an OLED display panel, an array substrate is generally made of an inorganic material, and an inorganic film layer formed of the inorganic material is broken due to a large young's modulus when the inorganic film layer is bent by a stress, which affects the flexibility of the array substrate.

In order to solve the above technical problem, the inventor provides a method for manufacturing an array substrate, please refer to fig. 1 to 11, wherein fig. 1 shows a schematic flow chart of a method for manufacturing an array substrate disclosed in an embodiment of the present application, which specifically includes:

s10: providing a substrate 100, and forming a semiconductor layer 200 on one side of the substrate 100;

in the embodiment of the present application, please refer to fig. 2, the substrate 100 includes a flexible substrate 101 and a buffer layer 102, wherein the flexible substrate 101 is formed on a carrier glass by coating, and the flexible substrate 101 is peeled off from the carrier glass after the array substrate is manufactured, so the carrier glass is not shown in fig. 2; after the flexible substrate 101 is formed, the buffer layer 102 is formed on one side of the flexible substrate 101, thereby forming the complete base 100.

It is understood that the substrate provided in the embodiments of the present application is the flexible substrate 101, and is made of organic materials, and the organic materials can be selected from one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyethersulfone, and polyetherimide.

The semiconductor layer 200 is formed on one side of the substrate 100, and the semiconductor layer 200 generally uses Amorphous Silicon (a-si) as a substrate, and the Amorphous Silicon is first subjected to a dehydrogenation process and then is crystallized by a Laser Annealing (ELA) process to form Polycrystalline Silicon (P-si) as the semiconductor layer 200.

In a preferred embodiment, the melting device applies a temperature of 450 degrees celsius to the polysilicon.

S20: etching the semiconductor layer 200 to form an active layer 201 and a barrier layer 202 which are arranged at intervals;

referring to fig. 3, since the semiconductor layer 200 is sensitive to gases such as carbon tetrafluoride and oxygen, the semiconductor layer 200 is coated with a photoresist and etched by a masking plate to form an active layer 201 of the thin film transistor and a barrier layer 202 for providing an etching barrier for a subsequent process. After the semiconductor layer 200 is etched, ions are implanted into the active layer 201, and the active layer 201 subjected to the ion implantation generates the property of a semiconductor due to the electrical change, so that the threshold voltage can be shifted to the positive direction when the ion implantation is performed and the thin film transistor is manufactured, and a channel layer is formed after the active layer 201 is subjected to the ion implantation.

As a preferred embodiment, the semiconductor layer 200 may be etched by dry etching, and the etching material may be a mixed gas of carbon tetrafluoride and oxygen; the implanted ions may be boron ions or phosphorus ions.

Wherein the active layer 201 and the barrier layer 202 are spaced apart in an extending direction parallel to the plane of the substrate 100.

S30: forming an inorganic layer 300, wherein the inorganic layer 300 is arranged to cover the active layer 201 and the barrier layer 202;

referring to fig. 4, the inorganic layer 300 is typically formed by depositing a silicon nitride or silicon oxide material, which may be Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD), and the present embodiment is not limited thereto. Since silicon nitride has a higher dielectric constant and better insulating properties than silicon oxide, in the present embodiment, silicon oxide is used as a material for manufacturing the inorganic layer 300.

The inorganic layer 300 covers the active layer 201 and the blocking layer 202, that is, the inorganic layer 300 completely covers one side of the active layer 201 and the blocking layer 202 away from the substrate 100 in a direction perpendicular to the substrate 100, and also covers two sides of the active layer 201 and the blocking layer 202 in a direction parallel to the substrate 100.

S40: etching the inorganic layer 300 along the direction toward the substrate 100 to form a plurality of grooves with the barrier layer 202 as an end point;

referring to fig. 5, in the embodiment of the present disclosure, the barrier layer 202 in the semiconductor layer 200 is used as an etching end point, and the inorganic layer 300 is etched to form a plurality of grooves, where a surface of the groove facing the substrate 100 coincides with a surface of the barrier layer 202 in the semiconductor layer 200 away from the substrate 100.

In this embodiment, the manner of etching the inorganic layer 300 may be dry etching or wet etching, which is not limited in this embodiment.

When the manner of etching the inorganic layer 300 is selected as dry etching, etching is generally performed using a gas in the form of plasma: when the CF4 system etching gas is adopted, the etching selection ratio of the etching gas to the inorganic layer 300 and the barrier layer 202 is 4: 1; when the CF2HF5 system etching gas is used, the etching selectivity of the etching gas to the inorganic layer 300 and the barrier layer 202 is 6: 1.

S50: depositing an organic layer 500 on the side of the inorganic layer 300 away from the substrate 100, so that the inorganic layer 300 is covered while the organic layer 500 fills the groove;

referring to fig. 6, an organic layer 500 is deposited on a side of the inorganic layer 300 away from the substrate 100, such that the organic layer 500 covers the inorganic layer 300 while filling the groove, and a surface of the organic layer 500 facing the substrate 100 coincides with a surface of the barrier layer 202 away from the substrate 100; in addition, the young's modulus of the organic layer 500 is smaller than that of the inorganic layer 300.

After the organic layer 500 completely covers the inorganic layer 300, the organic layer 500 is cured. The organic layer 500 in this embodiment is one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyethersulfone, and polyetherimide.

As can be seen from the above, in the method for manufacturing an array substrate according to the embodiment of the present disclosure, the groove communicating with the blocking layer 202 is formed on one side of the inorganic layer 300, and the organic layer 500 is used to fill the groove, so that the inorganic film layer formed of an inorganic material is prevented from being broken due to a large young's modulus when the inorganic film layer is subjected to stress bending, and the flexibility of the array substrate is not affected.

The inventors further studied and found that, when the organic layer 500 is used as an interlayer dielectric layer, but in a process of performing a hydrogenation treatment on the active layer 201 after the interlayer dielectric layer is manufactured, hydrogen ions enter the active layer 201 under a high temperature environment and are bonded with the hydrogen ions due to the lack of hydrogen bonds among atoms in the molecular structure of the organic layer 500 and the lack of high temperature resistance, on one hand, the hydrogen ions are difficult to enter the active layer through the organic layer 500 due to the lack of hydrogen bonds in the organic layer 500, and on the other hand, the temperature of the organic layer 500 is controlled to avoid melting of the organic material under the high temperature environment due to the low tolerance of the organic layer 500 to the high temperature, which may also affect the effect of the hydrogenation treatment on the active layer 201, and further may cause electrical problems such as threshold voltage drift.

In this regard, as a preferred embodiment, the organic layer 500 is cured to form a planarization layer, and since the organic layer 500 is usually in a gel or liquid state during manufacturing, after formation, the surface of the organic layer 500 away from the substrate 100 usually has an uneven topography, and the organic layer 500 is cured to serve as a planarization layer. The purpose of this arrangement is that, because processes such as hydrogenation treatment are usually required to be performed on the active layer before the planarization layer is formed, and the organic layer 500 is configured as the planarization layer in the array substrate due to the characteristics of the organic material such as no high temperature resistance and less hydrogen ions, it is helpful to avoid the deterioration of the original performance of the array substrate while the flexibility of the screen is improved by using the organic layer 500.

In the method for manufacturing an array substrate provided in the embodiment of the present application, please refer to fig. 7, the method may further include:

s41: etching the inorganic layer 300 along a direction toward the substrate 100 to form a plurality of through holes with the active layer 201 as an end point;

referring to fig. 5, in the embodiment of the present application, the barrier layer 202 is used as an end point, the inorganic layer 300 is etched along a direction toward the substrate 100 to form a plurality of grooves, and simultaneously, the active layer 201 in the semiconductor layer 200 is used as an end point, the inorganic layer 300 is etched to form a plurality of through holes, wherein a surface of one side of the groove, which faces the substrate 100, coincides with a surface of one side of the active layer 201 in the semiconductor layer 200, which is away from the substrate 100.

When the manner of etching the inorganic layer 300 is selected as dry etching, etching is generally performed using a gas in the form of plasma: when the CF4 system etching gas is adopted, the etching selection ratio of the etching gas to the inorganic layer 300 and the active layer 201 is 4: 1; when the CF2HF5 system etching gas is used, the etching selectivity of the etching gas to the inorganic layer 300 and the active layer 201 is 6: 1. .

In the method for manufacturing an array substrate provided in the embodiment of the present application, referring to fig. 8, step S30 further includes:

s31: forming a first inorganic layer 301, wherein the first inorganic layer 301 covers the active layer 201 and the barrier layer 202;

the first inorganic layer 301 is typically formed by depositing a silicon nitride or silicon oxide material, and the deposition method may be chemical vapor deposition or physical vapor deposition, which is not limited in the embodiments of the present invention. Since silicon nitride has a higher dielectric constant and better insulating properties than silicon oxide, in the present embodiment, silicon nitride is used as a material for manufacturing the first inorganic layer 301 as a preferred embodiment.

Here, the first inorganic layer 301 covers the active layer 201 and the blocking layer 202, in other words, the first inorganic layer 301 completely covers one side of the active layer 201 and the blocking layer 202 away from the substrate 100 in a direction perpendicular to the substrate 100, and also covers both sides of the active layer 201 and the blocking layer 202 in a direction parallel to the substrate 100.

S32: forming a first metal layer 401 on a side of the first inorganic layer 301 away from the active layer 201;

the first metal layer 401 is formed on the first inorganic layer 301 away from the active layer 201 by deposition or sputtering: usually, a metal layer covering the entire surface of the first inorganic layer 301 is formed on the side of the first inorganic layer 301 away from the active layer 201, and the metal layer covering the entire surface of the first inorganic layer 301 is etched by using a mask to form the first metal layer 401.

The orthographic projection of the first metal layer 401 on the substrate 100 does not overlap with the orthographic projection of the semiconductor layer 200 on the substrate 100, and at least part of the orthographic projection of the first metal layer 401 on the substrate 100 falls within the range of the orthographic projection of the active layer 201 on the substrate 100: a portion of the first metal layer 401, which has an orthographic projection on the substrate 100 falling within an orthographic projection range of the active layer 201 on the substrate 100, may serve as a gate electrode of the thin film transistor, and a portion of the first metal layer 401, which has an orthographic projection on the substrate 100 not falling within an orthographic projection range of the active layer 201 on the substrate 100, may serve as a first electrode of the storage capacitor.

As a preferred embodiment, the method for etching the first metal layer 401 may be dry etching, and the etching material may be one or more of sulfur hexafluoride, chlorine, oxygen, and the like.

S33: implanting ions into the active layer 201 through the first inorganic layer 301 to form a source layer 211 and a drain layer 212 using the first metal layer 401 as a mask;

since the orthographic projection of the first metal layer 401 on the substrate 100 does not overlap with the orthographic projection of the semiconductor layer 200 on the substrate 100, and, the orthographic projection of at least a part of the first metal layer 401 on the substrate 100 falls within the range of the orthographic projection of the active layer 201 on the substrate 100, thus, in a direction perpendicular to the substrate 100, there is a portion of the orthographic projection of the active layer 201 on the substrate 100 that is not covered by the orthographic projection of the first metal layer 401 on the substrate 100, and therefore, when the first metal layer 401 is used as a barrier, ions are implanted into the active layer 201, the ions can be implanted into the active layer 201 through the first inorganic layer 301, and the active layer 201 subjected to the ion implantation has electrical property change to generate semiconductor properties, therefore, the source layer 211 and the drain layer 212 of the thin film transistor can be used, the positions of the source layer 211 and the drain layer 212 in the horizontal direction can be arbitrarily selected, and the positional relationship in the drawings of the present application is merely an example.

Alternatively, the implanted ions may be boron ions or phosphorus ions.

It is understood that, when the recess with the active layer 201 as the end point is formed in step S40, the source layer 211 and the drain layer 212 are used as the end points of the etching, and the surface of the recess with the active layer 201 as the end point facing the substrate 100 coincides with the surface of the source layer 211/the drain layer 212 away from the substrate 100, so as to provide a receiving space for the subsequent injection of the conductive material.

S34: forming a second inorganic layer 302 on the side of the first metal layer 401 away from the first inorganic layer 301, wherein the second inorganic layer 302 is disposed to cover the first metal layer 401;

the second inorganic layer 302 is formed by depositing a silicon nitride or silicon oxide material, which may be chemical vapor deposition or physical vapor deposition, as the first inorganic layer 301, and the embodiment of the present invention is not limited thereto. Since silicon nitride has a higher dielectric constant and better insulation property than silicon oxide, in the present embodiment, silicon nitride is used as a material for manufacturing the second inorganic layer 302 as a preferred embodiment.

In other words, the second inorganic layer 302 completely covers one side of the first metal layer 401 away from the substrate 100 in a direction perpendicular to the substrate 100, and also covers two sides of the first metal layer 401 parallel to the substrate 100 in a direction.

In the method for manufacturing an array substrate according to the embodiment of the present application, referring to fig. 9, step S34 further includes:

s341: forming a second metal layer 402 on a side of the second inorganic layer 302 away from the first metal layer 401;

a second metal layer 402 is formed on the second inorganic layer 302 away from the first metal layer 401 by deposition or sputtering: in the same manner as the first metal layer 401, a metal covering the entire surface of the second inorganic layer 302 is formed on the side of the second inorganic layer 302 away from the first metal layer 401, and the metal covering the entire surface of the second inorganic layer 302 is etched by using a mask to form the second metal layer 402.

An orthogonal projection of the second metal layer 402 on the substrate 100 does not overlap an orthogonal projection of the semiconductor layer 200 on the substrate 100, and an orthogonal projection of at least a portion of the second metal layer 402 on the substrate 100 covers an orthogonal projection of the first metal layer 401 on the substrate 100, and the second metal layer 402 may serve as a second pole of the storage capacitor.

In a preferred embodiment, the second metal layer 402 is etched by dry etching, and the etching material may be one or more of sulfur hexafluoride, chlorine, oxygen, and the like.

S342: forming a third inorganic layer 303 on the side of the second metal layer 402 away from the second inorganic layer 302, the third inorganic layer 303 being disposed to cover the second metal layer 402;

the third inorganic layer 303 is a stacked structure and is formed by depositing a silicon nitride material and a silicon oxide material in an alternating order, and the deposition manner may be chemical vapor deposition or physical vapor deposition, which is not limited in the embodiment of the present application; meanwhile, the number of the silicon nitride material and the silicon oxide material stacked alternately in the third inorganic layer 303 is not limited in the embodiments of the present application.

In other words, the third inorganic layer 303 completely shields one side of the second metal layer 402, which is far from the second inorganic layer 302, which is far from the substrate 100 in the direction of the second metal layer 402, and wraps two sides of the second metal layer 402, which is parallel to the substrate 100 in the direction of the substrate 100, so that the inorganic material stack arranged in a stack can sufficiently resist water vapor, metal ions and oxygen while insulating the second metal layer 402, and can effectively avoid mechanical damage to the film structure from external force.

In the embodiment, the first inorganic layer 301 serves as a gate insulating layer for insulating the active layer 201 and the first metal layer 401, the second inorganic layer 302 serves as a capacitor dielectric layer for insulating the first metal layer 401 and the second metal layer 402, and the third inorganic layer 303 serves as an interlayer dielectric layer for insulating the second metal layer 402 and other layers on the side thereof away from the substrate 100.

In the method for manufacturing an array substrate according to the embodiment of the present application, referring to fig. 10, after step S50 is executed, the method further includes:

s51: forming a third metal layer 403 such that the third metal layer 403 fills the grooves and the via holes and covers the third inorganic layer 303;

forming a third metal layer 403 on the side of the third inorganic layer 303 away from the second metal layer 402, wherein the third metal layer can be formed by deposition or sputtering; the third metal layer 403 is formed such that the third metal layer 403 fills the grooves and the via holes and covers the third inorganic layer 303.

S52: etching the third metal layer 403, leaving the third metal layer 403 on the side of the source layer 211 away from the substrate 100 and the side of the drain layer 212 away from the substrate 100 to form a conductive pillar 413, where the conductive pillar 413 fills the through hole and the conductive pillar 413 is at least partially disposed on the side of the third inorganic layer 303 away from the substrate 100;

since the third metal layer 403 fills the groove and covers the third inorganic layer 303, and a surface of the third metal layer 403 facing the substrate 100 coincides with a surface of the source layer 211/the drain layer 212 facing away from the substrate 100, when the third metal layer 403 is etched, the third metal layer 403 remaining on a side of the source layer 211 away from the substrate 100 and/or a side of the drain layer 212 away from the substrate 100 may form a pillar-shaped conductive structure penetrating through the first inorganic layer 301, the second inorganic layer 302, and the third inorganic layer 303, which is referred to as a conductive pillar 413, where the conductive pillar 413 fills the through hole and the conductive pillar 413 is at least partially disposed on a side of the third inorganic layer 303 away from the substrate 100, so that an external power source may be connected to the source layer 211 of the thin film transistor through the conductive pillar 413 after the array substrate is formed, thereby achieving circuit conduction.

In a preferred embodiment, the third metal layer 403 is etched by dry etching, and the etching material may be one or more of sulfur hexafluoride, chlorine, oxygen, and the like.

S53: the organic layer 500 is deposited such that the organic layer 500 fills the recess and covers the third inorganic layer 303, the third metal layer 403, and the surface of the organic layer 500 facing the substrate 100 coincides with the surface of the second barrier layer 202 facing away from the substrate 100.

Depositing an organic layer 500 on the side of the third inorganic layer 303 far away from the substrate 100, so that the organic layer 500 fills the groove and covers the third inorganic layer 303 and the third metal layer 403, and the surface of the organic layer 500 facing the substrate 100 is coincided with the surface of the barrier layer 202 far away from the substrate 100; in addition, the young's modulus of the organic layer 500 is smaller than that of the inorganic layer.

After the organic layer 500 completely covers the third inorganic layer 303 and the third metal layer 403, the organic layer 500 is cured. The organic layer 500 in this embodiment is one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyethersulfone, and polyetherimide.

In this embodiment, the method for manufacturing the array substrate further includes forming film layers such as an anode layer, a pixel defining layer, and a supporting pillar on the side of the organic layer 500 away from the substrate 100.

Further, in the method for manufacturing an array substrate provided in the embodiment of the present application, referring to fig. 11 to 14, the method further includes:

s401: hydrotreating the active layer;

referring to fig. 11-12, after step S40 is performed, step S401 is performed, since during the process of melting and crystallizing amorphous silicon into polysilicon in the semiconductor layer 200, since atoms in the partial molecular structure of amorphous silicon are mostly connected by hydrogen bonds, the hydrogen content of amorphous silicon is high during melting, and hydrogen explosion may occur, thereby affecting the film thickness and corresponding performance of the active layer 201, and therefore, amorphous silicon is usually subjected to dehydrogenation before melting and crystallizing amorphous silicon. However, since dehydrogenation is performed in the pre-process, there are a lot of unbound or unsaturated bonds in the active layer 201, and dangling bonds and interface traps at the grain boundaries exist in the molecule, and in order to compensate for the above problems, hydrogenation of the active layer 201 is generally performed by releasing hydrogen gas by heating in a high temperature environment.

In the technical solution disclosed in this embodiment, since the plurality of grooves are formed on the side of the semiconductor layer 200 away from the substrate 100, when hydrogen is released in a high temperature environment, a part of hydrogen may seep out of the grooves, which is helpful for making the Subthreshold swing (Subthreshold swing) of the active layer 201 after the active layer 201 is made into a thin film transistor larger than that of the active layer 201 when the active layer 201 is fully hydrogenated, so that gray scale switching of the display panel on which the array substrate is mounted is more convenient.

Referring to fig. 13-14, step S401 can be performed before step S40, when step S401 is performed before step S40, hydrogen ions do not overflow the array substrate due to the existence of the grooves, and the hydrogen ions can enter the active layer 201 more fully; in other words, after the active layer 201 is hydrogenated, the inorganic layer 300 is etched using the semiconductor layer 200 as an end point to form a groove, so that the active layer 201 can absorb hydrogen ions more sufficiently during the hydrogenation, thereby improving the mobility of the active layer 201 and avoiding the threshold voltage drift phenomenon. Compared with the former scheme, the scheme can effectively improve the mobility of the active layer 201, improve the electrical property of the thin film transistor, avoid threshold voltage drift, and enable the display panel adopting the array substrate to have better display effect and better display uniformity under the power-on condition.

It is understood that, in the array substrate manufactured in the embodiment of the present application, the array substrate includes a thin film transistor and a storage capacitor, wherein a gate of the thin film transistor is located on the first metal layer 401, a source of the thin film transistor is located on the source layer 211, and a drain of the thin film transistor is located on the drain layer 212, in other words, the active layer 201 and the first metal layer 401 whose orthographic projection on the substrate 100 falls within a range of the orthographic projection of the active layer 201 on the substrate 100 together constitute the thin film transistor; the storage capacitor comprises a first plate and a second plate, wherein the first plate and the second plate are made of metal materials, and according to a capacitor definition formula, in a direction perpendicular to the substrate 100, a capacitor can be formed in an overlapped area of the first plate and the second plate, and the capacitor can be used as a storage capacitor, in the array substrate manufactured in the embodiment of the application, the first plate of the storage capacitor is located in the first metal layer 401, the second plate of the storage capacitor is located in the second metal layer 402, in other words, the first metal layer 401 and the second metal layer 402 jointly form the storage capacitor; in the extending direction parallel to the plane of the substrate 100, the orthographic projection of the barrier layer 202 on the substrate 100 is located between the orthographic projection of the thin film transistor on the substrate 100 and the orthographic projection of the storage capacitor on the substrate 100.

It should be added that the array substrate provided in the embodiments of the present application is a flexible substrate, and after the planarization layer formed by the organic layer 500 is formed, the array substrate provided in the embodiments of the present application can be endowed with better extensibility and bendability.

In summary, in the manufacturing method of the array substrate provided by the embodiment of the present application, the semiconductor layer 200 is formed by forming the barrier layer 202 which provides an etching barrier in a subsequent process in the same process for forming the active layer 201, then the inorganic layer 300 covering the active layer 201 and the barrier layer 202 is formed, the inorganic layer 300 is etched to form a plurality of grooves with the semiconductor layer 200 as an end point, and after the active layer 201 is hydrotreated, the organic layer 500 is deposited on the side of the inorganic layer 300 away from the substrate 100. Because the grooves are formed on the side of the semiconductor layer 200 away from the substrate 100, part of hydrogen can seep out of the grooves, which is beneficial to improving the subthreshold swing of the active layer 201 on the premise of ensuring the stability of the threshold voltage, so that the gray scale switching of the display panel carrying the array substrate is more convenient; in addition, the inorganic layer 300 may be etched using the semiconductor layer 200 as an end point after the active layer 201 is hydrotreated to form a groove, thereby improving the mobility of the active layer 201 and avoiding the threshold voltage drift phenomenon. Therefore, the manufacturing method of the array substrate provided by the embodiment of the application can avoid the deterioration of the original performance of the array substrate or further optimize the performance of the array substrate on the basis of ensuring the flexibility of the array substrate.

Referring to fig. 15, an array substrate 10 is further provided in the present embodiment, and the array substrate 10 may be manufactured according to the foregoing method. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.

The array substrate 10 may include:

a substrate 100;

in an embodiment of the present application, the base 100 includes a substrate and a buffer layer 102, wherein: in order to ensure the flexibility of the array substrate 10, the substrate provided by the embodiment of the present application is a flexible substrate 101 made of an organic material; the buffer layer 102 is disposed on one side of the substrate for isolating water vapor, oxygen or metal ions from the substrate, so the buffer layer 102 is usually made of an inorganic layer 300, which may be silicon oxide or silicon nitride; in a preferred embodiment, the buffer layer 102 has a stacked structure, such as: and a structure in which silicon nitride layers and silicon oxide layers are alternately stacked.

A semiconductor layer 200 disposed on one side of the substrate 100, and specifically, the semiconductor layer 200 includes an active layer 201 and a barrier layer 202 disposed in the same layer; in the extending direction parallel to the plane of the substrate 100, the active layer 201 and the barrier layer 202 are arranged at intervals and are distributed on one side of the substrate 100 in an array manner; further, the semiconductor layer 200 is disposed on a side of the buffer layer 102 away from the substrate, wherein the active layer 201 and the barrier layer 202 are disposed at an interval and distributed in an array on a side of the substrate 100. In the embodiment, the material of the semiconductor layer 200 is polysilicon.

The inorganic layer 300, the inorganic layer 300 is arranged on one side of the active layer 201 and the barrier layer 202 far away from the substrate 100, and the active layer 201 and the barrier layer 202 are covered; in other words, the inorganic layer 300 covers the active layer 201 and the barrier layer 202 both in a direction perpendicular to the substrate 100 and in an extending direction parallel to the plane of the substrate 100. In the embodiment, the material of the inorganic layer 300 is silicon nitride or silicon oxide; since silicon nitride has a higher dielectric constant and better insulation property than silicon oxide, in the embodiment of the present invention, the material of the inorganic layer 300 is silicon nitride.

The groove is formed in one side, away from the substrate 100, of the inorganic layer 300, and the bottom surface of the groove is overlapped with the surface of one side, away from the substrate 100, of the barrier layer 202; in other words, the grooves penetrate the inorganic layer 300, and extend to the barrier layer 202 in a direction perpendicular to the substrate 100.

The organic layer 500 fills the recess and covers the inorganic layer 300, in other words, the organic layer 500 is disposed on the side of the barrier layer 202 away from the semiconductor layer 200, penetrates through the inorganic layer 300, and covers the inorganic layer 300, and at the same time, the surface of the organic layer 500 facing the substrate 100 coincides with the surface of the barrier layer 202 away from the substrate 100.

In the embodiment of the present application, an opening area of the organic layer 500 on a side facing the substrate 100 is smaller than an opening area of the organic layer 500 on a side away from the substrate 100, in other words, an angle between a sidewall of the organic layer 500 and the substrate 100 is smaller than 90 degrees.

The organic layer 500 in this embodiment is one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyethersulfone, and polyetherimide. Therefore, it can be understood that, in the embodiment of the present application, the young's modulus of the organic layer 500 is smaller than that of the inorganic layer 300.

In a preferred embodiment, the organic layer 500 is a planarization layer. The purpose of this arrangement is that, because processes such as hydrogenation treatment are usually required to be performed on the active layer before the planarization layer is formed, and the organic layer 500 is configured as the planarization layer in the array substrate due to the characteristics of the organic material such as no high temperature resistance and less hydrogen ions, it is helpful to avoid the deterioration of the original performance of the array substrate while the flexibility of the screen is improved by using the organic layer 500.

In the array substrate 10 provided in the embodiment of the present application, the organic layer 500 is disposed on one side of the barrier layer 202 away from the semiconductor layer 200, penetrates through the inorganic layer 300, and covers the inorganic layer 300, and meanwhile, it is ensured that the surface of the organic layer 500 facing the substrate 100 side coincides with the surface of the barrier layer 202 away from the substrate 100 side, so that the contact area between the organic layer 500 and the inorganic layer 300 is larger than the contact area between the organic layer 500 and the inorganic layer 300 in the technical solution disclosed in the prior art, thereby ensuring that the array substrate 10 has better bendability than the prior art.

In the embodiment of the present application, the array substrate 10 further includes a through hole, the through hole is opened on a side of the inorganic layer 300 away from the substrate 100, and a bottom surface of the through hole coincides with a surface of the active layer 201 away from the substrate 100. In other words, the via hole also penetrates the inorganic layer 300, and the via hole extends to the active layer 201 in a direction perpendicular to the substrate 100.

In the embodiment of the present application, the inorganic layer 300 further includes a first inorganic layer 301, wherein the first inorganic layer 301 is located on a side of the semiconductor layer 200 away from the substrate 100, and the first inorganic layer 301 covers the active layer 201 and the barrier layer 202, in other words, in a direction perpendicular to the substrate 100 and in an extending direction parallel to a plane of the substrate 100, the first inorganic layer 301 covers both the active layer 201 and the barrier layer 202, and the first inorganic layer 301 completely covers both sides of the active layer 201 and the barrier layer 202 away from the substrate 100 in the direction perpendicular to the substrate 100 and covers both sides of the active layer 201 and the barrier layer 202 in the direction parallel to the substrate 100, so that the first inorganic layer 301 can serve as an insulating layer between the semiconductor layer 200 and other film layers located on the side away from the semiconductor layer 200 away from the substrate 100. Since silicon nitride has a higher dielectric constant and better insulating properties than silicon oxide, in the present embodiment, silicon nitride is used as a material for manufacturing the first inorganic layer 301 as a preferred embodiment.

The first metal layer 401 is disposed on a side of the first inorganic layer 301 away from the active layer 201, an orthographic projection of the first metal layer 401 on the substrate 100 does not overlap with an orthographic projection of the barrier layer 202 on the substrate 100, and an orthographic projection of at least a portion of the first metal layer 401 on the substrate 100 falls within a range of the orthographic projection of the active layer 201 on the substrate 100: a portion of the first metal layer 401, which has an orthographic projection on the substrate 100 falling within an orthographic projection range of the active layer 201 on the substrate 100, may serve as a gate electrode of the thin film transistor, and a portion of the first metal layer 401, which has an orthographic projection on the substrate 100 not falling within an orthographic projection range of the active layer 201 on the substrate 100, may serve as a first electrode of the storage capacitor.

It is understood that the active layer 201 includes a channel layer and a source layer 211 and a drain layer 212 located at both sides of the channel layer in a horizontal direction, and a projection of the first metal layer 401 on the substrate 100 coincides with a projection of the channel layer on the substrate 100. Further, the first metal layer 401, the channel layer, the source layer 211 and the drain layer 212, which are used as the gate electrodes, form a thin film transistor, and the thin film transistor can control the circuit signal passing through the thin film transistor to be turned on or off through the gate electrode, so that the display panel on which the array substrate 10 provided in the embodiment of the present application is mounted can emit light for display through the cooperation of a plurality of thin film transistors.

In the embodiment of the present application, the inorganic layer 300 further includes a second inorganic layer 302, the second inorganic layer 302 is located on a side of the first inorganic layer 301 away from the semiconductor layer 200, the second inorganic layer 302 covers the first metal layer 401, in other words, in a direction perpendicular to the substrate 100 and in an extending direction parallel to a plane of the substrate 100, the second inorganic layer 302 covers the first metal layer 401, the second inorganic layer 302 completely covers a side of the first metal layer 401 away from the substrate 100 in the direction perpendicular to the substrate 100, and also covers two sides of the first metal layer 401 in the direction parallel to the substrate 100, so that the second inorganic layer 302 can serve as an insulating layer between the first metal layer 401 and other film layers located on a side of the first metal layer 401 away from the substrate 100. Since silicon nitride has a higher dielectric constant and better insulation property than silicon oxide, in the present embodiment, silicon nitride is used as a material for manufacturing the second inorganic layer 302 as a preferred embodiment.

The second metal layer 402 is disposed on a side of the second inorganic layer 302 away from the first metal layer 401, an orthogonal projection of the second metal layer 402 on the substrate 100 does not overlap an orthogonal projection of the semiconductor layer 200 on the substrate 100, and an orthogonal projection of at least a portion of the second metal layer 402 on the substrate 100 covers an orthogonal projection of the first metal layer 401 on the substrate 100, and the second metal layer 402 may serve as a second pole of the storage capacitor.

The inorganic layer 300 further includes a third inorganic layer 303, and the third inorganic layer 303 is located on a side of the second metal layer 402 away from the second inorganic layer 302 and is disposed to cover the second metal layer 402, in other words, the third inorganic layer 303 completely covers a side of the second metal layer 402 away from the substrate 100 in a direction perpendicular to the substrate 100, and also covers two sides of the second metal layer 402 in a direction parallel to the substrate 100. In this embodiment, the third inorganic layer 303 may be a stacked structure, and specifically may include a silicon nitride layer and a silicon oxide layer, where the silicon nitride layer and the silicon oxide layer are alternately stacked on one side of the second metal layer 402 away from the second inorganic layer 302 according to a predetermined sequence and are disposed to cover the second metal layer 402, and the stacked inorganic material stack may have a sufficient blocking effect on water vapor, metal ions, and oxygen, and may also effectively avoid mechanical damage to the film structure from an external force.

It is to be understood that the first inorganic layer 301, the second inorganic layer 302, and the third inorganic layer 303 are all inorganic layers including hydrogen bonds.

The array substrate 10 provided in the embodiment of the present invention further includes a conductive pillar 413, wherein the conductive pillar 413 fills the through hole, and at least a portion of the conductive pillar 413 is disposed on a side of the third inorganic layer 302 away from the substrate 100, in other words, the conductive pillar 413 penetrates through the inorganic layer 300 along a direction toward the substrate 100, and the conductive pillar 413 is disposed on a side of the source layer 211 away from the substrate 100 or a side of the drain layer 212 away from the substrate 100; specifically, the technical solution that the conductive pillar 413 penetrates through the inorganic layer 300 in the direction toward the substrate further includes that the conductive pillar 413 sequentially penetrates through the third inorganic layer 303, the second inorganic layer 302 and the first inorganic layer 301 in the direction toward the substrate, and meanwhile, as a preferred embodiment, an orthogonal projection of the conductive pillar 413 on the substrate 100 is not overlapped with an orthogonal projection of the first metal layer 401 on the substrate 100, in other words, a projection of the conductive pillar 413 on the substrate 100 is not overlapped with a projection of the active layer 201 on the substrate 100. Since the conductive pillar 413 sequentially penetrates the third inorganic layer 303, the second inorganic layer 302, and the first inorganic layer 301 in a direction toward the substrate, the conductive pillar 413 is insulated from the first metal layer 401 and the second metal layer 402 by the inorganic layers.

It is understood that the conductive pillar 413 can be formed by etching the third metal layer 403 covering the inorganic layer 300 on one side.

It should be added that the material of the first metal layer 401 is one or more of molybdenum, copper, chromium, tungsten, tantalum, and titanium; the material of the second metal layer 402 is the same as that of the first metal layer 401, i.e. it may be one or more of molybdenum, copper, chromium, tungsten, tantalum and titanium; the conductive pillar 413 may be made of at least one of titanium, aluminum, molybdenum, and tungsten, as a preferred embodiment, the conductive pillar 413 is made of a titanium aluminum titanium (TiAlTi) composite material, in some embodiments, the conductive pillar 413 may also be made of a molybdenum aluminum molybdenum (MoAlMo) composite material, and the specific material selection of the first metal layer 401, the second metal layer 402, and the conductive pillar 413 is not limited in this embodiment.

Further, in the array substrate provided in the embodiment of the present application, the organic layer 500 is disposed on a side of the third inorganic layer 303 away from the substrate 100 and penetrates through the inorganic layer 300, the organic layer 500 covers the inorganic layer 300 and the conductive pillars 413 at the same time, in other words, the organic layer 500 sequentially penetrates through the third inorganic layer 303, the second inorganic layer 302 and the first inorganic layer 301 along a direction toward the substrate 100, and the organic layer 500 covers the third inorganic layer 303 and the conductive pillars 413.

It can be understood that, in the array substrate provided in the embodiment of the present application, the array substrate includes a thin film transistor and a storage capacitor, wherein a gate of the thin film transistor is located on the first metal layer 401, a source of the thin film transistor is located on the source layer 211, and a drain of the thin film transistor is located on the drain layer 212, in other words, the active layer 201 and the first metal layer 401 whose orthographic projection on the substrate 100 falls within a range of the orthographic projection of the active layer 201 on the substrate 100 together constitute the thin film transistor; (ii) a The storage capacitor comprises a first plate and a second plate, wherein the first plate and the second plate are made of metal materials, and according to a capacitor definition formula, in a direction perpendicular to the substrate 100, a capacitor can be formed in an overlapped area of the first plate and the second plate, and the capacitor can be used as a storage capacitor, in the array substrate manufactured in the embodiment of the application, the first plate of the storage capacitor is located in the first metal layer 401, the second plate of the storage capacitor is located in the second metal layer 402, in other words, the first metal layer 401 and the second metal layer 402 jointly form the storage capacitor; in the extending direction parallel to the plane of the substrate 100, the orthographic projection of the barrier layer 202 on the substrate 100 is located between the orthographic projection of the thin film transistor on the substrate 100 and the orthographic projection of the storage capacitor on the substrate 100.

It should be noted that, the thin film transistor referred to in the embodiments of the present application is a Low Temperature Polysilicon (LTPS) thin film transistor, and since the active layer 201 of the Low Temperature polysilicon thin film transistor is amorphous Silicon, in the process of modifying amorphous Silicon into polysilicon, since amorphous Silicon contains a large number of hydrogen bonds inside it, during the high Temperature melt crystallization process, hydrogen explosion may occur due to the hydrogen bonds breaking at high Temperature, thereby affecting the performance of the thin film transistor, and therefore, it is necessary to perform dehydrogenation treatment on amorphous Silicon before crystallization at high Temperature, and since the dehydrogenation treatment may sacrifice the mobility of a part of the active layer 201 of the thin film transistor, it is necessary to perform hydrogenation in the subsequent processes.

In the prior art, to meet the requirement of flexibility of the array substrate 10, the material of the interlayer dielectric layer is usually made of an inorganic material instead of an organic material, but when the material of the interlayer dielectric layer is replaced by an organic material, although the requirement of flexibility of the array substrate 10 is met, the hydrogenation effect is reduced due to reasons such as lack of high temperature resistance and hydrogen bonding of the organic material, so that when the hydrogenation process is performed on the active layer 201 through the interlayer dielectric layer, the active layer 201 is not hydrogenated sufficiently. Therefore, in the array substrate 10 provided in the embodiment of the present application, the organic layer 500 is disposed through the inorganic layer 300 and disposed on the side of the barrier layer 202 away from the substrate 100, and the material of the interlayer dielectric layer is still an inorganic material, so that the performance of the thin film transistor is not deteriorated while the flexibility of the array substrate 10 is ensured.

In contrast, in the oxide semiconductor thin film transistor, an oxide semiconductor material represented by indium tin oxide does not need to be crystallized, so that the oxide semiconductor material is not placed in a high-temperature environment in the process of forming the active layer 201, and even if a large number of hydrogen bonds are contained in the oxide semiconductor, the hydrogen explosion phenomenon does not occur to cause performance damage of the active layer 201 of the thin film transistor.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for manufacturing an array substrate includes:

forming an inorganic layer covering the active layer and the barrier layer;

and depositing an organic layer on the side of the inorganic layer far away from the substrate, so that the organic layer covers the inorganic layer while filling the groove.

2. The method of manufacturing of claim 1, further comprising:

3. The method of manufacturing according to claim 2, wherein the step of forming the inorganic layer further comprises:

4. The manufacturing method according to claim 3, wherein the step of forming the second inorganic layer further comprises:

and forming a third inorganic layer on one side of the second metal layer, which is far away from the second inorganic layer, wherein the third inorganic layer covers the second metal layer.

5. The method of manufacturing according to claim 4, further comprising, after the step of forming the third inorganic layer:

6. The manufacturing method of claim 5, wherein the array substrate comprises a thin film transistor and a storage capacitor, wherein:

7. The method of manufacturing of claim 1, further comprising:

8. The method of manufacturing of claim 1, further comprising:

9. An array substrate manufactured by the manufacturing method of any one of claims 1 to 8, the array substrate comprising:

a substrate;

an organic layer filling the groove and covering the inorganic layer.

10. The array substrate of claim 9, wherein the array substrate further comprises:

11. The array substrate of claim 10, wherein:

the inorganic layer comprises a first inorganic layer, the first inorganic layer is positioned on one side of the semiconductor layer far away from the substrate, and the first inorganic layer is arranged to cover the active layer and the barrier layer;

12. The array substrate of claim 11, wherein:

the inorganic layer also comprises a second inorganic layer, the second inorganic layer is positioned on one side, away from the semiconductor layer, of the first inorganic layer, and the second inorganic layer is arranged to cover the first metal layer;

13. The array substrate of claim 12, wherein:

the inorganic layer further comprises a third inorganic layer, and the third inorganic layer is positioned on one side of the second metal layer, which is far away from the second inorganic layer, and is arranged to cover the second metal layer;

14. The array substrate of claim 13, wherein:

the organic layer is arranged on one side, away from the substrate, of the third inorganic layer and sequentially penetrates through the third inorganic layer, the second inorganic layer and the first inorganic layer along the direction close to the substrate, and the organic layer covers the third inorganic layer and the conductive posts.

15. The array substrate of claim 14, wherein the array substrate comprises a thin film transistor and a storage capacitor, wherein:

the grid electrode of the thin film transistor is positioned on the first metal layer, the source electrode of the thin film transistor is positioned on the source electrode layer, and the drain electrode of the thin film transistor is positioned on the drain electrode layer; the first polar plate of the storage capacitor is positioned on the first metal layer, and the second polar plate of the storage capacitor is positioned on the second metal layer; in the extending direction parallel to the plane of the substrate, the orthographic projection of the barrier layer on the substrate is positioned between the orthographic projection of the thin film transistor on the substrate and the orthographic projection of the storage capacitor on the substrate.