CN111933671B - Display substrate, manufacturing method thereof and display panel - Google Patents
Display substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN111933671B CN111933671B CN202010826310.4A CN202010826310A CN111933671B CN 111933671 B CN111933671 B CN 111933671B CN 202010826310 A CN202010826310 A CN 202010826310A CN 111933671 B CN111933671 B CN 111933671B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
Abstract
The invention provides a display substrate, a manufacturing method thereof and a display panel, and relates to the technical field of display. A display substrate comprising a binding region, the binding region comprising a substrate and a plurality of binding units located above the substrate, the binding units comprising: a binding portion including a first interlayer dielectric layer and a binding terminal covering the first interlayer dielectric layer; a first flat part wrapping at least a partial edge of the binding terminal. The invention is suitable for manufacturing the display substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display panel.
Background
The OLED (Organic Light-Emitting Diode) display product gradually occupies the market of consumers by virtue of advantages of low power consumption, wide color gamut, lightness, thinness, heteromorphism and the like, and is widely applied to the fields of portable electronics, wearable equipment, instant messaging, virtual reality and the like.
The OLED display panel includes a display area and a binding area (pad). The bonding region includes bonding terminals electrically connected to the chip terminals, and the display region includes a thin film transistor and an OLED light emitting unit. The binding terminal is generally disposed at the same layer as a Source Drain (SD) of the thin film transistor. In order to obtain lower resistance, the source and drain electrodes adopt a Ti/Al/Ti (titanium/aluminum/titanium) laminated structure. In order to improve the light extraction efficiency of the OLED light-emitting unit, the anode of the OLED light-emitting unit adopts a stacked structure of ITO/Ag/ITO (indium tin oxide/silver/indium tin oxide). Ag and ITO are difficult to dry etch and are generally manufactured by wet etch. Then, when the anode is formed by wet etching, the Al in the edge of the binding terminal is etched by the silver etching solution to form undercut; meanwhile, after the Al is etched by the silver etching liquid, Ag is separated out, and the separated Ag can cause the short circuit of two adjacent binding terminals or the phenomenon of GDS (Growing Dark Spot) generated when the two adjacent binding terminals move to the display area, so that the product quality is reduced.
Disclosure of Invention
The embodiment of the invention provides a display substrate, a manufacturing method thereof and a display panel.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in one aspect, a display substrate is provided, which includes a binding region, where the binding region includes a substrate and a plurality of binding units located on the substrate, and the binding units include:
a binding portion including a first interlayer dielectric layer and a binding terminal covering the first interlayer dielectric layer;
a first flat portion covering at least a partial edge of the binding terminal.
Optionally, the binding unit further includes:
a recess located at least on one side of the binding portion; the distance from the opening end of the groove to the substrate along the direction perpendicular to the substrate is smaller than the distance from the first interlayer dielectric layer to the substrate along the direction perpendicular to the substrate, and at least part of the edge of the binding terminal is positioned in the groove; the first flat portion is located within the groove.
Optionally, the binding part further includes a connecting wire, the first interlayer dielectric layer covers the connecting wire, and the binding terminal is electrically connected to the connecting wire;
the binding region further comprises a first insulating layer positioned between the substrate and the plurality of binding units, and the connecting lines of the binding units are respectively contacted with the first insulating layer;
in the binding unit, the bottom end of the groove is located in the first insulating layer.
Optionally, the binding unit further comprises a lead part; the lead wire part comprises a lead wire and a second interlayer dielectric layer, the second interlayer dielectric layer covers the lead wire, and the lead wire is connected with the connecting wire;
in the binding unit, the grooves are formed in the peripheral area of the binding part except for the area where the lead is located.
Optionally, the display substrate further includes a display area connected to the binding area, and the display area includes: a plurality of sub-pixels arranged in an array, wherein each sub-pixel comprises a thin film transistor and a second flat part covering the thin film transistor, each second flat part comprises a flat through hole, and the hole depth of each flat through hole is smaller than the groove depth of the corresponding groove;
the first flat portion and the second flat portion are arranged in the same layer.
Optionally, the display area further includes: a plurality of grid lines, wherein one grid line is arranged between two adjacent rows of the sub-pixels, and the plurality of grid lines are correspondingly connected with the plurality of leads respectively;
the thin film transistor comprises an active layer, a gate insulating layer, a gate electrode and a second insulating layer which are arranged in a stacked mode, wherein the gate insulating layer covers the active layer, and the second insulating layer covers the gate electrode;
the grid electrode, the grid line, the lead and the connecting line are arranged on the same layer;
the first insulating layer comprises a first sublayer and a second sublayer, the first sublayer and the gate insulating layer are arranged on the same layer, and the second sublayer and the second insulating layer are arranged on the same layer.
Optionally, the thin film transistor further includes a third interlayer dielectric layer, a source/drain electrode, and a source/drain electrode via hole located on the second insulating layer; the source and drain through hole penetrates through the third interlayer dielectric layer, the second insulating layer and the gate insulating layer, and the source and drain are electrically connected with the active layer through the source and drain through hole;
the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer are arranged on the same layer; the source and drain electrodes and the binding terminal are arranged on the same layer; the groove and the source and drain via hole are arranged on the same layer.
Optionally, two adjacent grooves in two adjacent binding units are connected.
Optionally, the display substrate further includes a display area connected to the binding area, and the display area includes: a plurality of sub-pixels arranged in an array, the sub-pixels including thin film transistors and second flat portions covering the thin film transistors;
the first flat portion is located on a side of the binding terminal away from the substrate, and a thickness of the first flat portion in a direction perpendicular to the substrate is smaller than a thickness of the second flat portion in the direction perpendicular to the substrate.
In another aspect, a display panel is provided, which includes the display substrate.
In another aspect, a method for manufacturing a display substrate is provided, where the method includes:
forming a binding part, wherein the binding part comprises a first interlayer dielectric layer and a binding terminal, and the binding terminal covers the first interlayer dielectric layer;
forming a first flat part covering at least a partial edge of the binding terminal.
Optionally, the display substrate further includes a groove; prior to the forming the first flat portion, the method further comprises:
forming a groove at least on one side of the binding portion; the distance from the opening end of the groove to the substrate along the direction perpendicular to the substrate is smaller than the distance from the first interlayer dielectric layer to the substrate along the direction perpendicular to the substrate, and partial edge of the binding terminal is located in the groove.
The embodiment of the invention provides a display substrate, a manufacturing method thereof and a display panel, wherein the display substrate comprises a binding region, the binding region comprises a substrate and a plurality of binding units positioned on the substrate, and the binding units comprise: a binding portion including a first interlayer dielectric layer and a binding terminal covering the first interlayer dielectric layer; a first flat portion covering at least a partial edge of the binding terminal. In the display substrate, the first flat part at least covers part of the edge of the binding terminal, so that in the subsequent etching process, the first flat part at least can prevent the part of the edge of the binding terminal from being in direct contact with etching liquid, the edge of the binding terminal covered by the first flat part is effectively prevented from being etched, and the product quality is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along the direction AB of FIG. 1;
FIG. 3 is another cross-sectional view taken along the direction AB of FIG. 1;
FIG. 4 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view taken along the CD of FIG. 4;
FIG. 6 is another cross-sectional view taken along the CD direction of FIG. 4;
fig. 7 is a further sectional view taken along the direction AB of fig. 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the embodiments of the present invention, the terms "first", "second", "third", and the like are used for distinguishing the same or similar items with substantially the same functions and actions, and are used only for clearly describing technical solutions of the embodiments of the present invention, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
In the embodiments of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the embodiments of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Example one
An embodiment of the present invention provides a display substrate, including a binding region, as shown in fig. 1, where the binding region includes a substrate and a plurality of binding units 1 located on the substrate, as shown in fig. 2 and 3, where the binding units include:
and a binding part including a first interlayer dielectric layer 32 and binding terminals 31, the binding terminals 31 covering the first interlayer dielectric layer 32.
And a first flat part 5, wherein the first flat part 5 covers at least part of the edge of the binding terminal 31.
The binding terminals described above can be used for subsequent binding with chip terminals. The binding terminal may include a two-layer laminate structure, for example: the aluminum layer is in contact with the first interlayer dielectric layer; three-layer laminate structures may also be included, for example: the first titanium layer, the aluminum layer and the second titanium layer, which are not limited herein, can be selected according to actual requirements.
The first flat part at least covers part of the edge of the binding terminal, and the first flat part is as follows: the first flat portion may cover only a part of the edge of the bound terminal, or may cover the entire edge of the bound terminal. The more the edge of the binding terminal covered by the first flat part is, the more effectively the edge of the binding terminal can be prevented from being etched in the subsequent etching process. In addition, the first flat part has two functions of planarization and insulation, and the material of the first flat part can be photoresist.
The specific arrangement position of the first flat part is not limited, and for example, the first flat part may be located in the groove 4 as shown in fig. 2; or may be located on the side of the binding terminal 31 remote from the substrate 10, as shown in fig. 3.
The material of the substrate is not limited, and it can be made of rigid material, such as: glass; it can also be made of flexible materials, such as: PI (Polyimide) film or PDMS (Polydimethylsiloxane) film.
In the display substrate, the first flat part at least covers part of the edge of the binding terminal, and in the subsequent etching process, the first flat part at least can prevent the part of the edge of the binding terminal from being in direct contact with etching liquid, so that the edge of the binding terminal covered by the first flat part is effectively prevented from being etched, and the product quality is improved.
Optionally, referring to fig. 2, the binding unit further includes:
a groove 4, which is at least positioned at one side of the binding part; the distance h1 from the opening end of the groove 4 to the substrate 10 along the direction perpendicular to the substrate 10 is smaller than the distance h2 from the first interlayer dielectric layer 31 to the substrate 10 along the direction perpendicular to the substrate 10, and at least part of the edge of the binding terminal is positioned in the groove; the first flat portion is located in the groove.
The groove is at least positioned at one side of the binding part, and the groove is characterized in that: the recess may be located on only one side of the binding portion or may be located on multiple sides of the binding portion. If all set up the recess around the portion of binding, then bind all edges of terminal and all be located the recess. If one side of the binding part is provided with a groove, partial edges of the binding terminals are all positioned in the groove. The groove can be continuous or comprise a plurality of independent sub-grooves; the former may be chosen in order to avoid that more edges of the bound terminals are etched.
The cross-sectional shape of the groove in the direction perpendicular to the substrate is not limited here, and may be rectangular, trapezoidal, or the like. Fig. 2 is a view showing an example in which the sectional shape of the groove in the direction perpendicular to the substrate is an inverted trapezoid.
It should be noted that, before the chip terminals and the terminals are bound, the film structure of the display area in the display substrate is basically formed; if the chip terminals and the bonding terminals are in poor contact, a large yield loss occurs, resulting in a sharp increase in cost. According to the invention, the first flat part is arranged in the groove, at least part of the edge of the binding terminal is positioned in the groove, and the first flat part at least covers the edge of the binding terminal positioned in the groove; meanwhile, the distance from the opening end of the groove to the substrate along the direction perpendicular to the substrate is smaller than the distance from the first interlayer dielectric layer to the substrate along the direction perpendicular to the substrate, so that the first flat part can not cause the generation of a section difference between the center and the edge of the binding terminal under the condition that the edge of the binding terminal coated by the first flat part is effectively prevented from being etched, the problem of poor contact during subsequent binding of the chip terminal and the binding terminal is avoided, the binding quality is guaranteed, the yield is improved, and the cost is reduced.
Further alternatively, as shown in fig. 2, the binding portion further includes a connection line 33, the first interlayer dielectric layer 32 covers the connection line, and the binding terminal 31 is electrically connected to the connection line.
The binding region further includes a first insulating layer 34 between the substrate and the plurality of binding units, and the connection lines 33 of the respective binding units are in contact with the first insulating layer 34, respectively.
In the binding unit, the bottom end of the groove 4 is located within the first insulating layer 34.
The material of the first insulating layer is not limited, and may be, for example, silicon nitride, silicon oxide, silicon oxynitride, or the like. The first insulating layer may include only one layer or may include a plurality of layers, and for example, the first insulating layer may include a first sub-layer and a second sub-layer which are stacked.
The groove penetrates through the first interlayer dielectric layer and part of the first insulating layer and is enough for accommodating the edge of the binding terminal and the first flat part. The structure is simple and easy to manufacture.
The groove may only penetrate through all of the first interlayer dielectric layers, and at this time, the bottom end of the groove is the surface, far away from the substrate, of the first insulating layer, and the first interlayer dielectric layers of two adjacent binding portions are disconnected; or, the bottom end of the groove is positioned in the first interlayer dielectric layer, and the first interlayer dielectric layers of two adjacent binding parts are connected.
Alternatively, as shown in fig. 1, the binding unit further includes a lead part 3; the lead part comprises a lead and a second interlayer dielectric layer, the second interlayer dielectric layer covers the lead, and the lead is connected with the connecting wire.
Referring to fig. 1, in the binding unit, grooves are formed in the peripheral region of the binding portion 2 except for the region where the lead is located.
The lead wires are used for connecting the wiring in the display area and the connecting wires of the binding part, and the lead wires can be grid wire lead wires, data wire lead wires and the like, wherein the grid wire lead wires can be used for connecting grid wires and the connecting wires, and the data wire lead wires can be used for connecting data wires and the connecting wires.
Because the bottom end of the groove is positioned in the first insulating layer and the lead is positioned on the first insulating layer, the groove is not arranged in the area where the lead is positioned in order to avoid the disconnection of the lead. In order to avoid the etching of the edge of the binding terminal to the maximum degree, grooves are formed in the peripheral area of the binding part except for the area where the lead is located.
Optionally, in order to fully utilize the original manufacturing process without additionally adding a mask, referring to fig. 4, the display substrate further includes a display area OE connected to the bonding area OF, and the display area OE includes: a plurality of sub-pixels 6 arranged in an array, as shown in fig. 5 and 6, the sub-pixels including a thin film transistor 7 and a second flat portion 14 covering the thin film transistor 7, the second flat portion including a flat via hole (not labeled in fig. 5 and 6), the flat via hole having a hole depth smaller than the groove depth of the groove; the first flat part and the second flat part are arranged on the same layer.
The display Area (AA) is an Area for realizing display.
The sub-pixel may be any one of a red sub-pixel (R), a green sub-pixel (G), or a blue sub-pixel (B). The display area of the display substrate can simultaneously comprise three sub-pixels, namely a red sub-pixel, a green sub-pixel and a blue sub-pixel; it is also possible to include only one sub-pixel, for example: including only a plurality of red subpixels, or only a plurality of green subpixels, or only a plurality of blue subpixels. The concrete can be determined according to actual requirements.
The groove depth of the groove, i.e., the distance between the open end and the bottom end of the groove in the direction perpendicular to the substrate, may be in the range of 0.8 to 1.2 μm, and specifically, may be in the ranges of 0.8 μm, 1.0 μm, and 1.2 μm.
The first flat part and the second flat part are arranged on the same layer, namely the first flat part and the second flat part are manufactured by adopting a one-time composition process. The one-time patterning process refers to a process of forming a desired layer structure through one exposure. The primary patterning process includes masking, exposing, developing, etching, and stripping processes.
Because the hole depth of the flat through hole is smaller than the groove depth of the groove, when a common mask plate (mask) is used for patterning to form the flat through hole, unexposed flat film material can be naturally left in the groove, and then the first flat part is formed.
The thin film transistor may include an active layer 21, a gate insulating layer 11, a gate electrode 22, a third interlayer dielectric layer 13, a source electrode 23, and a drain electrode 24 as shown in fig. 6; and may further include an active layer 21, a gate insulating layer 11, a gate electrode 22, a second insulating layer 12, a third interlayer dielectric layer 13, a source electrode 23, and a drain electrode 24 as shown in fig. 5. Here, the type of the thin film transistor is not limited, and the thin film transistor may be a top gate type thin film transistor or a bottom gate type thin film transistor. The material of the active layer is also not limited here, and may be an oxide semiconductor material, such as: IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), and the like; but also LTPS (Low Temperature Poly-silicon); of course, the material may be single crystal silicon or the like.
Optionally, in order to further fully utilize the original manufacturing process without additionally adding a mask, referring to fig. 4, the display area OE further includes: a plurality of grid lines 7, wherein one grid line 7 is arranged between two adjacent rows of sub-pixels 6; the grid lines are correspondingly connected with the lead wires respectively.
Referring to fig. 5, the thin film transistor includes an active layer 21, a gate insulating layer 11, a gate electrode 22, and a second insulating layer 12, which are stacked, the gate insulating layer 11 covering the active layer 21, and the second insulating layer 12 covering the gate electrode 22.
The grid electrode, the grid line, the lead and the connecting line are arranged on the same layer.
The first insulating layer comprises a first sublayer and a second sublayer, the first sublayer and the gate insulating layer are arranged on the same layer, and the second sublayer and the second insulating layer are arranged on the same layer. The same-layer arrangement of the grid electrode, the grid line, the lead and the connecting line means that the grid electrode, the grid line, the lead and the connecting line are manufactured by adopting a one-step composition process. The arrangement of the first sub-layer and the gate insulating layer on the same layer means that the first sub-layer and the gate insulating layer are manufactured by adopting a one-time composition process. The arrangement of the second sub-layer and the second insulating layer on the same layer means that the second sub-layer and the second insulating layer are manufactured by adopting a one-time composition process.
A gate line is arranged between the two adjacent rows of sub-pixels, where the two adjacent rows of sub-pixels may be two adjacent rows of sub-pixels, or two adjacent columns of sub-pixels as shown in fig. 4. The driving method of the gate line is not limited here, and one gate line may drive one row of sub-pixels, or one gate line may drive two rows of sub-pixels. The gate line may be electrically connected to a gate electrode of the thin film transistor.
Optionally, referring to fig. 5, the thin film transistor 7 further includes a third interlayer dielectric layer 13, a source drain, and a source drain via (not labeled in fig. 5) on the second insulating layer 12; and the source and drain via hole penetrates through the third interlayer dielectric layer, the second insulating layer and the gate insulating layer, and the source and drain are electrically connected with the active layer through the source and drain via hole. As shown in fig. 6, the source and drain electrodes include a source electrode 23 and a drain electrode 24; the source and drain vias include source and drain vias.
The first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer are arranged on the same layer; the source and drain electrodes and the binding terminal are arranged on the same layer; the groove and the source and drain via hole are arranged on the same layer.
The first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer are arranged in the same layer, namely the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer are manufactured by adopting a one-time composition process; the arrangement of the source drain and the binding terminal on the same layer means that a one-time composition process is adopted to manufacture the source drain and the binding terminal; the same layer arrangement of the groove and the source and drain via hole means that the groove and the source and drain via hole are manufactured by adopting a one-step composition process.
The source and drain electrodes and the binding terminal are arranged on the same layer, so that the structure of the binding terminal is the same as that of the source and drain electrodes. In order to obtain lower resistance, the source electrode, the drain electrode and the binding terminal can both adopt a Ti/Al/Ti laminated structure. When the anode is formed by subsequently adopting the silver etching liquid, the first flat part coats the edge of the binding terminal, so that the contact between Al and the silver etching liquid is avoided, the edge of the binding terminal is prevented from being etched, Ag is prevented from being separated out, and the conductivity of the binding terminal is ensured.
The structure does not add a new film layer, can be manufactured by utilizing the original process to the maximum extent, does not add an additional mask plate and has low manufacturing cost.
As shown in fig. 5, the sub-pixel of the display substrate may further include a first electrode 25 and a second electrode 26, and the first electrode 25 and the gate electrode 12 are disposed in the same layer, and the first electrode 25 and the second electrode 26 may form a capacitor. In addition, the sub-pixel may further include an anode 15, a pixel defining layer 16, an organic light emitting function layer 17, a cathode 18, a Spacer (PS), and the like as shown in fig. 5, the anode being electrically connected to the drain through the flat via hole of the second flat portion; the depth of the source and drain via hole is larger, and the source and drain via hole belongs to a deep hole; certainly, shallow holes are further formed between the third interlayer dielectric layer and the gate and between the third interlayer dielectric layer and the first electrode, so that connection and routing are facilitated.
Optionally, in order to save space as much as possible, two adjacent grooves of two adjacent binding units are connected.
In the above structure, the first flat portion is located in the groove. Another arrangement structure of the first flat portion is provided below.
Optionally, referring to fig. 4, the display substrate further includes a display area OE connected to the bonding area OF, and the display area OE includes: and a plurality of sub-pixels 6 arranged in an array, the sub-pixels including thin film transistors and second flat portions covering the thin film transistors.
Referring to fig. 3, the first flat portion 5 is located on a side of the binding terminal 31 away from the substrate 10, and the thickness of the first flat portion in the direction perpendicular to the substrate is smaller than the thickness of the second flat portion in the direction perpendicular to the substrate.
In order not to increase the number of masks, the first and second flat portions may be formed by one patterning process using a Half-Tone Mask.
It should be noted that the second flat portion is generally thick, and if the thickness of the first flat portion in the direction perpendicular to the substrate is the same as the thickness of the first flat portion in the direction perpendicular to the substrate, as shown in fig. 7, a higher protrusion (caused by the first flat portion 5) is formed on the edge of the binding terminal 31, so that a larger step difference is generated between the center and the edge of the binding terminal; then, when the chip terminals and the binding terminals are subsequently bound, the problem of poor contact between the chip terminals and the binding terminals is easily caused, and the binding yield is reduced. Therefore, the thickness of the first flat portion in the direction perpendicular to the substrate needs to be smaller than the thickness of the second flat portion in the direction perpendicular to the substrate, so as to reduce the step difference between the center and the edge of the binding terminal, and further alleviate the problem of poor contact between the chip terminal and the binding terminal, thereby improving the binding yield.
Example two
The embodiment of the invention provides a display panel, which comprises the display substrate provided by the first embodiment.
The display panel may be a flexible display panel or a rigid display panel, which is not limited herein. The display panel may be an OLED (Organic Light-Emitting Diode) display panel, and any product or component with a display function, such as a television, a digital camera, a mobile phone, and a tablet computer, which includes the OLED display panel. The OLED display panel may be a top-emission OLED display panel or a bottom-emission OLED display panel, which is not limited herein.
EXAMPLE III
The embodiment of the invention provides a manufacturing method of a display substrate in the first embodiment, which comprises the following steps:
and S01, forming a binding part, wherein the binding part comprises a first interlayer dielectric layer and binding terminals, and the binding terminals cover the first interlayer dielectric layer.
And S02, forming a first flat part, wherein the first flat part at least covers part of the edge of the binding terminal.
In the display substrate formed by the method, the first flat part at least covers part of the edge of the binding terminal, and in the subsequent etching process, the first flat part at least can prevent part of the edge of the binding terminal from being in direct contact with etching liquid, so that the edge of the binding terminal covered by the first flat part is effectively prevented from being etched, and the product quality is improved.
Optionally, the display substrate further includes a groove; prior to forming the first flat portion at S02, the method further includes:
s03, forming a groove, wherein the groove is at least positioned on one side of the binding part; the distance from the opening end of the groove to the substrate along the direction vertical to the substrate is smaller than the distance from the first interlayer dielectric layer to the substrate along the direction vertical to the substrate, and the partial edge of the binding terminal is positioned in the groove.
The following describes the manufacturing method specifically by taking the structure of the display substrate shown in fig. 5 and 2 as an example. The method comprises the following steps:
and S10, forming an active layer on the substrate, wherein the active layer is positioned in the display area.
The material of the active layer may be low temperature polysilicon.
S11, forming a gate insulating layer and a first sub-layer through a one-time composition process; the first sublayer is located in the bonding region, and the gate insulating layer is located in the display region and covers the active layer.
S12, forming a grid electrode (Gate), a second electrode, a grid line, a lead and a connecting line through a one-time composition process; the grid electrode, the first electrode and the grid line are positioned on the grid insulating layer, and the lead and the connecting line are positioned on the first sub-layer.
S13, forming a second electrode, a second insulating layer covering the second electrode and a second sub-layer; the second electrode and the second insulating layer are located in the display area, the second sub-layer is located in the binding area, and at the moment, the first sub-layer and the second sub-layer form a first insulating layer, namely the first insulating layer of the binding area comprises a two-layer structure of the first insulating sub-layer and the second insulating sub-layer.
And S14, forming a second electrode on the second insulating layer, wherein the second electrode is positioned in the display area.
And S15, forming a first interlayer dielectric layer (ILD1), a second interlayer dielectric layer (ILD2) and a third interlayer dielectric layer (ILD3) through a one-time composition process, wherein the first interlayer dielectric layer and the second interlayer dielectric layer are both positioned on the second insulating sublayer, and the third interlayer dielectric layer is positioned to cover the second electrode and the second insulating layer.
And S16, forming a source and drain via hole and a groove through an etching process, wherein the source and drain via hole is positioned in the display area, and the groove is positioned in the binding area.
S17, forming a Source Drain (SD) and a binding terminal; the source and drain electrodes are positioned in the display area and comprise a source electrode and a drain electrode; the binding terminal is located in the binding area, and the edge of the binding terminal is located in the groove.
The source electrode, the drain electrode and the binding terminal can adopt a Ti/Al/Ti laminated structure so as to obtain lower resistance; at this time, forming the source-drain and the binding terminal includes: and sequentially forming a titanium layer, an aluminum layer and a titanium layer.
And S18, forming a first flat part (PLN1) and a second flat part (PLN2) by adopting a common mask plate, wherein the first flat part is positioned in the groove, and the second flat part is positioned in the display area and covers the source and drain electrodes.
S19, an Anode (AND) AND a Pixel Defining Layer (PDL) are sequentially formed on the second flat portion.
The anode can adopt a laminated structure of ITO/Ag/ITO (indium tin oxide/silver/indium tin oxide) to improve the light extraction efficiency; at this time, the forming the anode includes: and sequentially forming an indium tin oxide layer, a silver layer and an indium tin oxide layer.
S20, forming a light Emitting Layer (EL) in the opening of the pixel defining layer.
S21, forming a cathode on the light-emitting layer.
The display substrate formed through the steps can effectively avoid the etching of the edge of the binding terminal coated by the first flat part, and meanwhile, the step difference between the center and the edge of the binding terminal cannot be caused, so that the problem of poor contact when the chip terminal is subsequently bound and the terminal is bound is avoided, the binding quality is guaranteed, the yield is improved, and the cost is reduced.
For the description of the structure related to the display substrate in this embodiment, reference may be made to embodiment one, and details are not described here.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. A display substrate comprising a binding region, wherein the binding region comprises a substrate and a plurality of binding units located above the substrate, and wherein the binding units comprise:
a binding portion including a first interlayer dielectric layer and a binding terminal covering the first interlayer dielectric layer;
a first flat portion covering at least a partial edge of the binding terminal;
a recess located at least on one side of the binding portion; the distance from the opening end of the groove to the substrate along the direction perpendicular to the substrate is smaller than the distance from the first interlayer dielectric layer to the substrate along the direction perpendicular to the substrate, and at least part of the edge of the binding terminal is positioned in the groove; the first flat portion is located within the groove;
the binding part further comprises a connecting wire, the first interlayer dielectric layer covers the connecting wire, and the binding terminal is electrically connected with the connecting wire;
the bonding region further comprises a first insulating layer located between the substrate and the plurality of bonding units, and the connecting lines of the bonding units are respectively in contact with the first insulating layer;
in the binding unit, the bottom end of the groove is located in the first insulating layer.
2. The display substrate of claim 1,
the binding unit further includes a lead part; the lead wire part comprises a lead wire and a second interlayer dielectric layer, the second interlayer dielectric layer covers the lead wire, and the lead wire is connected with the connecting wire;
in the binding unit, the grooves are formed in the peripheral area of the binding part except for the area where the lead is located.
3. The display substrate of claim 2, further comprising a display area connected to the bonding area, the display area comprising: a plurality of sub-pixels arranged in an array, wherein each sub-pixel comprises a thin film transistor and a second flat part covering the thin film transistor, each second flat part comprises a flat through hole, and the hole depth of each flat through hole is smaller than the groove depth of the corresponding groove;
the first flat part and the second flat part are arranged on the same layer.
4. The display substrate according to claim 3, wherein the display area further comprises: a plurality of grid lines, wherein one grid line is arranged between two adjacent rows of the sub-pixels, and the plurality of grid lines are correspondingly connected with the plurality of leads respectively;
the thin film transistor comprises an active layer, a gate insulating layer, a gate electrode and a second insulating layer which are arranged in a stacked mode, wherein the gate insulating layer covers the active layer, and the second insulating layer covers the gate electrode;
the grid electrode, the grid line, the lead and the connecting line are arranged on the same layer;
the first insulating layer comprises a first sublayer and a second sublayer, the first sublayer and the gate insulating layer are arranged on the same layer, and the second sublayer and the second insulating layer are arranged on the same layer.
5. The display substrate according to claim 4, wherein the thin film transistor further comprises a third interlayer dielectric layer, source and drain electrodes and source and drain via holes located on the second insulating layer; the source and drain via hole penetrates through the third interlayer dielectric layer, the second insulating layer and the gate insulating layer, and the source and drain are electrically connected with the active layer through the source and drain via hole;
the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer are arranged on the same layer; the source and drain electrodes and the binding terminal are arranged on the same layer; the groove and the source and drain via hole are arranged on the same layer.
6. The display substrate according to any one of claims 1 to 5, wherein two adjacent grooves of two adjacent binding units are connected.
7. The display substrate of claim 1, further comprising a display area connected to the bonding area, the display area comprising: a plurality of sub-pixels arranged in an array, the sub-pixels including thin film transistors and second flat portions covering the thin film transistors;
the first flat portion is located on a side of the binding terminal away from the substrate, and a thickness of the first flat portion in a direction perpendicular to the substrate is smaller than a thickness of the second flat portion in the direction perpendicular to the substrate.
8. A display panel comprising the display substrate according to any one of claims 1 to 7.
9. A method of manufacturing a display substrate according to any one of claims 1 to 7, the method comprising:
forming a first insulating layer;
forming a binding part, wherein the binding part comprises a connecting wire, a first interlayer dielectric layer and a binding terminal, and the binding terminal covers the first interlayer dielectric layer; the first interlayer dielectric layer covers the connecting wire, and the binding terminal is electrically connected with the connecting wire; the first insulating layer is in contact with the connecting wire;
forming a groove at least at one side of the binding portion; the distance from the opening end of the groove to the substrate along the direction perpendicular to the substrate is smaller than the distance from the first interlayer dielectric layer to the substrate along the direction perpendicular to the substrate, and partial edge of the binding terminal is positioned in the groove; the bottom end of the groove is positioned in the first insulating layer;
forming a first flat portion covering at least a partial edge of the binding terminal, the first flat portion being located in the groove.
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| CN113838868B (en) * | 2021-09-23 | 2024-02-20 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
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| CN104733471A (en) * | 2013-12-23 | 2015-06-24 | 昆山国显光电有限公司 | Array substrate of organic light-emitting displaying device and preparing method thereof |
| CN106847774A (en) * | 2017-01-09 | 2017-06-13 | 上海天马微电子有限公司 | A kind of preparation method of display panel and display panel |
| CN110676217A (en) * | 2019-10-09 | 2020-01-10 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
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| CN104733471A (en) * | 2013-12-23 | 2015-06-24 | 昆山国显光电有限公司 | Array substrate of organic light-emitting displaying device and preparing method thereof |
| CN106847774A (en) * | 2017-01-09 | 2017-06-13 | 上海天马微电子有限公司 | A kind of preparation method of display panel and display panel |
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