CN110416274B

CN110416274B - Substrate, preparation method thereof and OLED display panel

Info

Publication number: CN110416274B
Application number: CN201910712990.4A
Authority: CN
Inventors: 朴商爀
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-08-02
Filing date: 2019-08-02
Publication date: 2023-04-07
Anticipated expiration: 2039-08-02
Also published as: CN110416274A

Abstract

The invention relates to the technical field of display, in particular to a substrate, a preparation method thereof and an OLED display panel. The method is used for reducing exposure and etching processes, reducing the cost required by the exposure and etching processes, improving the productivity and reducing the manufacturing cost when the TFT backboard is prepared. The embodiment of the invention provides a substrate, which comprises a substrate and a plurality of thin film transistors, wherein the thin film transistors are arranged on the substrate and positioned in each sub-pixel area; each thin film transistor comprises a metal shading layer, a buffer layer and an active layer which are sequentially stacked along the direction far away from the substrate; for each thin film transistor, the orthographic projection of the metal shading layer along the thickness direction of the metal shading layer covers the orthographic projection of the buffer layer along the thickness direction of the buffer layer, and the orthographic projection of the buffer layer along the thickness direction of the buffer layer covers the orthographic projection of the active layer along the thickness direction of the active layer. The embodiment of the invention is used for preparing the TFT backboard.

Description

Substrate, preparation method thereof and OLED display panel

Technical Field

The invention relates to the technical field of display, in particular to a substrate, a preparation method thereof and an OLED display panel.

Background

Compared with LCD (Liquid Crystal Display) devices, OLED (Organic Light-Emitting Diode) Display devices are receiving more and more attention because they have the excellent characteristics of self-luminescence, no need of backlight source, high contrast, thin thickness, wide viewing angle, fast response speed, applicability to flexible panels, wide temperature range, simple structure and process, etc.

Disclosure of Invention

The invention mainly aims to provide a substrate, a preparation method thereof and an OLED display panel. The method is used for reducing exposure and etching processes, reducing the cost required by the exposure and etching processes, improving the productivity and reducing the manufacturing cost when the TFT backboard is prepared.

In order to achieve the purpose, the invention adopts the following technical scheme:

in one aspect, an embodiment of the present invention provides a substrate, including a substrate, and a plurality of thin film transistors disposed on the substrate and located in each sub-pixel region; each thin film transistor comprises a metal shading layer, a buffer layer and an active layer which are sequentially stacked along the direction far away from the substrate; wherein, for each thin film transistor, the orthographic projection of the metal shading layer along the thickness direction covers the orthographic projection of the buffer layer along the thickness direction, and the orthographic projection of the buffer layer along the thickness direction covers the orthographic projection of the active layer along the thickness direction.

Optionally, the thickness of the metal light shielding layer is

The thickness of the buffer layer is

The active layer has a thickness of +>

Optionally, the slope angle of the side wall of the metal light shielding layer is greater than 0 degree and less than or equal to 90 degrees; the slope angle of the side wall of the buffer layer is larger than 0 degree and smaller than or equal to 90 degrees; the slope angle of the side wall of the active layer is larger than 0 degree and smaller than or equal to 90 degrees.

Optionally, each sub-pixel region is further provided with a capacitor, and the capacitor includes a first pole and a second pole; a plurality of said thin film transistors including a driving TFT and at least one switching TFT; the driving TFT also comprises a grid electrode, a first electrode and a second electrode, wherein the first electrode of the capacitor and the grid electrode of the driving TFT are in the same layer and are insulated from each other, the second electrode of the capacitor and the first electrode and the second electrode of the driving TFT are in the same layer and are insulated from each other, and the second electrode of the capacitor is electrically connected with the grid electrode of the driving TFT.

Optionally, the at least one switching TFT includes a first switching TFT, the first switching TFT further includes a gate electrode, a first electrode and a second electrode, the first electrode of the first switching TFT is electrically connected to the data line, and the second electrode of the first switching TFT is electrically connected to the second electrode of the capacitor.

In another aspect, an embodiment of the present invention provides a method for manufacturing a substrate, including: sequentially forming a metal layer, an insulating layer and a semiconductor layer on a substrate; forming a photoresist pattern on the semiconductor layer through a photolithography process; etching the semiconductor layer, the insulating layer and the metal layer under the mask of the photoresist pattern to obtain an active layer, a buffer layer and a metal shading layer contained in each thin film transistor; for each thin film transistor, the orthographic projection of the metal shading layer in the thickness direction covers the orthographic projection of the buffer layer in the thickness direction, and the orthographic projection of the buffer layer in the thickness direction covers the orthographic projection of the active layer in the thickness direction.

Optionally, etching the semiconductor layer, the insulating layer and the metal layer under the mask of the photoresist pattern; the method comprises the following steps: etching the semiconductor layer to obtain the active layer, so that the active layer has a first etching deviation relative to the photoresist pattern; etching the insulating layer to obtain the buffer layer, wherein the buffer layer has a second etching deviation relative to the photoresist pattern, and the second etching deviation is smaller than the first etching deviation; and etching the metal layer to obtain the metal shading layer, so that the metal shading layer has a third etching deviation relative to the photoresist pattern, and the third etching deviation is smaller than the second etching deviation.

Optionally, etching the insulating layer includes: before the metal layer is etched, etching the insulating layer through a dry etching process to obtain a first insulating pattern, wherein the first insulating pattern has a fourth etching deviation relative to the photoresist pattern, and the fourth etching deviation is smaller than the third etching deviation;

and after the metal layer is etched, ashing treatment is carried out on the photoresist pattern, and the first insulation pattern is etched through a dry etching process to obtain the buffer layer.

Optionally, performing ashing processing on the photoresist pattern and etching the first insulating pattern through a dry etching process are performed simultaneously, or performing ashing processing on the photoresist pattern and etching the first insulating pattern through a dry etching process are performed alternately.

On the other hand, the embodiment of the invention provides an OLED display panel, which comprises a TFT backboard and an OLED device arranged on the TFT backboard; the TFT backplane comprises a substrate as described above.

Optionally, the OLED device is a bottom-emitting OLED device.

Optionally, the OLED device is a white OLED device, the OLED display panel further includes a color filter layer disposed between the white OLED device and the TFT backplane, the color filter layer includes a plurality of color filter units, each color filter unit is disposed in one sub-pixel region in a one-to-one correspondence, and the plurality of color filter units includes a first color filter unit, a second color green unit, and a third color filter unit; the first color, the second color, and the third color are three primary colors.

The embodiment of the invention provides a substrate, a preparation method thereof and an OLED display panel, wherein when a TFT backboard is prepared, the following steps can be carried out: 1. depositing a metal layer; 2. depositing an insulating layer; 3. depositing a semiconductor layer; 4. exposing the semiconductor layer, the insulating layer and the metal layer; 5. respectively etching the semiconductor layer, the insulating layer and the metal layer; 6. and removing the photoresist. In the process, the light-shielding metal layer, the buffer layer and the active layer can be formed only by one-time photoetching process. Compared with the TFT backboard in which the buffer layer arranged between the metal shading layer and the active layer covers the whole substrate, the TFT backboard can reduce the exposure and etching processes, reduce the cost required by the exposure and etching processes, improve the productivity and reduce the manufacturing cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic top view of an OLED display panel according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structural diagram of an OLED display panel according to an embodiment of the present invention;

fig. 3 is a schematic top view illustrating a sub-pixel region of an OLED display panel according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional structural diagram of another OLED display panel according to an embodiment of the present invention;

FIG. 5 is an enlarged view of a portion of the structure shown in FIG. 2 according to an embodiment of the present invention;

fig. 6 is an equivalent circuit diagram of a driving circuit including the switching TFT, the driving TFT and the capacitor according to an embodiment of the present invention.

Fig. 7 is a schematic flow chart illustrating a method for fabricating a substrate according to an embodiment of the invention;

fig. 8 is a schematic structural diagram of sequentially forming a metal layer, an insulating layer and a semiconductor layer on a substrate according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a photoresist pattern formed based on the FIG. 8 embodiment of the present invention;

fig. 10 is a schematic structural diagram of forming an active layer, a buffer layer and a metal light shielding layer based on fig. 9 according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of an active layer formed based on fig. 9 according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a buffer layer formed based on the method shown in FIG. 9 according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of forming a metal light shielding layer based on fig. 9 according to an embodiment of the invention;

fig. 14 is a schematic structural view illustrating a first insulation pattern formed based on fig. 11 according to an embodiment of the present invention;

FIG. 15 is a schematic diagram illustrating a structure of a photoresist pattern after ashing processing based on FIG. 14 according to an embodiment of the invention;

fig. 16 is a schematic structural diagram of a buffer layer formed based on fig. 14 according to an embodiment of the present invention;

fig. 17 is a schematic diagram of another structure for forming a buffer layer based on fig. 14 according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

Embodiments of the present invention provide an OLED display panel that may be used for an OLED display device.

As shown in fig. 1, the OLED display panel includes a display Area (AA) a and a peripheral Area S located at a periphery of the display Area a; the peripheral region S is used for wiring, and a driving circuit (e.g., a gate driving circuit) may be provided. The display area A is provided with a plurality of sub-pixels P, and each sub-pixel P is correspondingly arranged in one sub-pixel area Q.

Here, as shown in fig. 1, a plurality of sub-pixels P are arranged in a matrix form as an example. In this case, the sub-pixels P arranged in a line in the horizontal direction X are referred to as the same row of sub-pixels P, and the sub-pixels P arranged in a line in the vertical direction Y are referred to as the same column of sub-pixels P. The same row of subpixels P may be connected to one gate line, and the same column of subpixels P may be connected to one data line.

On this basis, as shown in fig. 2, the OLED display panel includes a TFT (Thin Film Transistor) backplane 1 and an OLED device 2 disposed on the TFT backplane 1.

As shown in fig. 2 and 3, the TFT backplane 1 includes a substrate 11, and a pixel driving circuit disposed on the substrate 11 and located in each sub-pixel region. Wherein the pixel driving circuit comprises a plurality of thin film transistors 12. The plurality of thin film transistors 12 include a driving TFT121 and at least one switching TFT122. The drain of the drive TFT121 is electrically connected to the first pole 21 of the OLED device 2.

As shown in fig. 2, each of the thin film transistors 12 may include a metal light-shielding layer 1211, a buffer layer 1212, and an active layer 1213, which are sequentially stacked in a direction away from the substrate 11. And for each thin film transistor 12, the orthographic projection of the metal light-shielding layer 1211 in the thickness direction thereof covers the orthographic projection of the buffer layer 1212 in the thickness direction thereof, and the orthographic projection of the buffer layer 1212 in the thickness direction thereof covers the orthographic projection of the active layer 1213 in the thickness direction thereof.

With respect to the TFT back sheet 1, as shown in fig. 4, the buffer layer 1212 disposed between the metal light-shielding layer 1211 and the active layer 1213 covers the entire substrate 11, and the following steps are required in preparation: 1. depositing a metal layer; 2. exposing the metal layer; 3. etching the metal layer; 4. depositing a buffer layer; 5. depositing a semiconductor layer; 6. exposing the semiconductor layer; 7. etching the semiconductor layer; 8. the photoresist and the like are removed, and in the process, two times of photoetching processes are needed.

In the embodiment of the present invention, when the TFT backplane 1 is manufactured, the following steps may be performed: 1. depositing a metal layer; 2. depositing an insulating layer; 3. depositing a semiconductor layer; 4. exposing the semiconductor layer, the insulating layer and the metal layer; 5. respectively etching the semiconductor layer, the insulating layer and the metal layer; 6. and removing the photoresist. In this process, the light blocking metal layer 1211, the buffer layer 1212, and the active layer 1213 may be formed through only one photolithography process. Compared with the TFT backplane 1 in which the buffer layer 1212 provided between the metal light-shielding layer 1211 and the active layer 1213 covers the entire substrate 11, the exposure and etching processes can be reduced, the costs required for the exposure and etching processes can be reduced, the throughput can be improved, and the manufacturing cost can be reduced.

The thicknesses of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 are not particularly limited.

In order to prevent the metal light-shielding layer 1211, the buffer layer 1212 and the active layer 1213 from being too thick, the subsequent film layers are likely to be broken during deposition, thereby easily causing corrosion or short-circuit problems. In one embodiment of the present invention, as shown in FIG. 5, the thickness of the metal light-shielding layer 1211 is

The cushion layer 1212 can have a thickness +>

The active layer 1213 has a thickness->

The thickness of the metal light-shielding layer 1211 can be

And &>

Can be @, the buffer layer 1212 can have a thickness>

And &>

Can be thick/be any value of (4), the active layer 1213 can be thick @>

And &>

Any value of (1).

In the case where the thicknesses of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 are constant, in order to prevent the sidewall slope angles (shown by θ 1, θ 2, and θ 3 in fig. 5) of any one or more of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 from being too large, the subsequent film layers are likely to be broken during deposition, and thus corrosion or short-circuit problems are likely to occur. In another embodiment of the present invention, as shown in fig. 5, the slope angle θ 1 of the sidewall of the metal light-shielding layer 1211 is greater than 0 degree and less than or equal to 90 degrees; the slope angle theta 2 of the side wall of the buffer layer 1212 is greater than 0 degree and less than or equal to 90 degrees; the angle θ 3 of the sidewall of the active layer 1213 is greater than 0 degrees and equal to or less than 90 degrees.

In an example, the slope angle θ 1 of the sidewall of the metal light-shielding layer 1211 may be any one of 20 degrees, 30 degrees, 50 degrees, 80 degrees and 90 degrees, and the slope angle θ 2 of the sidewall of the buffer layer 1212 may be any one of 30 degrees, 45 degrees, 60 degrees, 70 degrees and 90 degrees; the slope angle θ 3 of the sidewall of the active layer 1213 may be any of 30 degrees, 40 degrees, 45 degrees, 50 degrees, 60 degrees, 70 degrees and 90 degrees.

In another embodiment of the present invention, as shown in fig. 2 and 3, each subpixel region is further provided with a capacitor Cst including a first electrode 31 and a second electrode 32. The capacitor Cst and the plurality of thin film transistors 12 constitute a driving circuit for driving the OLED device 2 to emit light.

Therefore, it should be understood by those skilled in the art that, regardless of how the capacitor Cst and the plurality of thin film transistors 12 are disposed, the capacitor Cst necessarily needs to be electrically connected to the plurality of thin film transistors 12 based on the driving circuit for driving the OLED device 2 to emit light.

The structure of the capacitor Cst and the connection manner between the capacitor Cst and the thin film transistors 12 are not limited, as long as the thin film transistors 12 can provide different potentials for the first electrode 31 and the second electrode 32 of the capacitor Cst.

In an example of the present invention, as shown in fig. 2 and 3, the driving TFT121 further includes a gate electrode 1214, a first pole 1215, and a second pole 1216; the first electrode 31 of the capacitor Cst may be in the same layer as the gate 1214 of the driving TFT121 and insulated from each other, and the second electrode 32 of the capacitor Cst may be in the same layer as the first electrode 1215 and the second electrode 1216 of the driving TFT121 and insulated from each other. The gate 1214 of the driving TFT121 may be electrically connected to the second electrode 32 of the capacitor Cst.

In the embodiment of the invention, the first electrode 1215 of the driving TFT121 may be a source, and the second electrode 1216 may be a drain; alternatively, the first electrode 1215 of the driving TFT is a drain electrode, and the second electrode 1216 is a source electrode, which is not particularly limited.

As shown in fig. 3, the power line VDD is electrically connected to the first electrode 1215 of the driving TFT121 for transmitting a voltage signal, and the plurality of thin film transistors 12 and the capacitor Cst drive the OLED device 2 to emit light. Wherein, as shown in fig. 3, the power supply line VDD may be disposed in the same layer as the first and

second poles

1215 and 1216 of the driving TFT 121.

Note that, the embodiment of the present invention does not limit the plurality of thin film transistors 12, and the plurality of thin film transistors may be formed by connecting two TFTs as described above, or may be formed by connecting two or more TFTs.

In yet another example of the present invention, referring to fig. 3, the at least one switching TFT includes a first switching TFT122. The first switching TFT122 further includes a gate 1224, a first pole 1225, and a second pole 1226. The gate electrode 1224 of the first switching TFT122 is electrically connected to the gate line, the first electrode 1225 of the first switching TFT122 is electrically connected to the data line DL, and the second electrode 1226 of the first switching TFT122 is electrically connected to the second electrode 32 of the capacitor Cst.

Since the second pole 32 of the capacitor Cst is also electrically connected to the gate 1214 of the driving TFT121, when the second pole 1226 of the first switching TFT122 is electrically connected to the second pole 32 of the capacitor Cst, the second pole 1226 of the first switching TFT122 and the gate 1214 of the driving TFT121 are electrically connected through the second pole 32 of the Cst.

In the embodiment of the present invention, the first electrode 1225 of the first switching TFT122 may be a source electrode, and the second electrode 1226 is a drain electrode; alternatively, the first electrode 1225 of the first switching TFT122 is a drain electrode, and the second electrode 1226 is a source electrode, which is not limited herein.

The first switching TFT122 and the driving TFT121 may be top gate TFTs or bottom gate TFTs. The bottom gate type can be further classified into a Back Channel Etch (BCE) structure and an Etch Stop Layer (ESL).

In an example of the present invention, as shown in fig. 3, the driving TFT121 and the first switching TFT121 are both top gate TFTs, the gate electrode 1214 of the driving TFT121 and the gate electrode 1224 of the first switching TFT122 are disposed in the same layer, and the first pole 1215 and the second pole 1216 of the driving TFT121 and the first pole 1225 and the second pole 1226 of the first switching TFT122 are disposed in the same layer.

Thus, the gate electrode 1214 of the driving TFT121 and the gate electrode 1224 of the first switching TFT122 may be formed through the same patterning process, and the first pole 1215 and the second pole 1216 of the driving TFT121 may be formed through the same patterning process as the first pole 1225 and the second pole 1226 of the driving TFT122.

Fig. 3 illustrates the gate line GL and the gate electrode 1224 of the first switching TFT122 being shared, but the embodiment of the invention is not limited thereto, and the gate line GL and the gate electrode 1224 of the first switching TFT122 may be separately disposed.

Based on this, an equivalent circuit diagram of the driving circuit composed of the one switching TFT122, the one driving TFT121, and the capacitor Cst can be referred to as shown in fig. 6. When the gate line GL is turned on, the switching TFT122 is turned on, and transmits an input signal on the data line DL to the gate electrode 1214 of the driving TFT121 to charge the capacitor Cst, and when the gate line GL is turned off, the voltage of the gate electrode 1214 of the driving TFT121 is held by the capacitor Cst.

As shown in fig. 2, the peripheral region S of the OLED display panel is further provided with a gate driving IC (Integrated Circuit) electrically connected to the gate lines GL and a data driving IC electrically connected to the data lines DL, and the gate driving IC and the data driving IC may be respectively disposed at left and lower sides of the display region a.

At this time, as shown in fig. 2, the TFT backplane 1 may further include a gate pad and a source pad disposed on the substrate 11 and located in the peripheral region S, the gate line GL being electrically connected to the gate driving IC through the gate pad, and the data line DL being electrically connected to the data driving IC through the source pad. Taking COF (Chip On Film, commonly called as Chip On Film) as an example, the gate driver IC and the data driver IC may be respectively bonded to the gate pad and the source pad by anisotropic conductive adhesive.

As shown in fig. 2, the OLED device 2 may comprise a light emitting functional layer 22 and a second electrode 23 in addition to the first electrode 21 described above.

Wherein the first pole 21 of the OLED device 2 may be an anode and the second pole 23 of the OLED device 2 is a cathode, or the first pole of the OLED device 2 is a cathode and the second pole 23 of the OLED device 2 is an anode. And is not particularly limited herein.

The OLED device 2 may be a top-emitting light-emitting device, a bottom-emitting light-emitting device, or a double-sided light-emitting device, which is not limited herein.

In an embodiment of the present invention, the first pole 21 of the OLED device 2 is taken as an anode, and the second pole 23 of the OLED device 2 is taken as a cathode.

When the OLED device 2 is a top-emission type light emitting device, the first electrode 21 is opaque and may be a stacked structure of ITO (Indium Tin Oxides)/Ag/ITO, and the second electrode 23 is transparent or translucent and may be a thin metal silver. When the OLED device 2 is a bottom emission type light emitting device, the first electrode 21 is transparent, and may be Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In 2O 3), or the like, and the second electrode 23 is opaque, and may be metallic silver or metallic aluminum. In the case that the OLED device 2 is a double-sided light emitting device, the first electrode 21 and the second electrode 23 are transparent, in this case, the first electrode 21 may be Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In 2O 3), or the like, and the second electrode 23 may be a thin metal silver.

In one example of the present invention, the OLED device 2 is a bottom-emitting OLED device, as shown in FIG. 2. I.e. the first pole 21 is transparent and the second pole 23 is opaque.

Based on this, in some embodiments of the present invention, the light emitting functional layer 22 includes a light emitting layer. In other embodiments, the light-emitting function layer 22 further includes one or more layers of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL), in addition to the light-emitting layer.

Here, as for the light emission function layer 22, one light emission function layer 22 may be independently provided for each OLED device 2. The light emitting function 22 may be provided in a whole layer covering the display area a. When the light-emitting functional layer 22 is provided in a whole layer, the light-emitting functional layer 22 emits white light, and the light-emitting functional layer 22 can be formed by evaporation using an Open Mask (Open Mask).

In an embodiment of the present invention, as shown in fig. 2, the OLED device 2 is a white OLED device, the OLED display panel further includes a color filter layer 4 disposed between the white OLED device 2 and the TFT backplane 1, the color filter layer 4 includes a plurality of color filter units 41, each color filter unit 41 is disposed in a sub-pixel area in a one-to-one correspondence manner, and the plurality of color filter units 41 includes a first color filter unit, a second color green light unit, and a third color filter unit; the first color, the second color and the third color are three primary colors.

In an embodiment of the present invention, the light-emitting functional layer 22 in the OLED device 2 is provided in a single layer.

In addition, as shown in fig. 2, the TFT backplane 1 may further include a passivation layer 13 and a planarization layer 14 disposed between the driving transistor 12 and the first electrode 21 of the OLED device 2, for example.

Based on this, in some embodiments of the present invention, the color filter layer 41 may be disposed between the passivation layer 13 and the planarization layer 14.

An embodiment of the present invention provides a method for manufacturing a substrate, referring to fig. 7, including:

s1, as shown in fig. 8, a metal layer 100, an insulating layer 200, and a semiconductor layer 300 are sequentially formed on a substrate 11.

Illustratively, the metal layer 100, the insulating layer 200, and the semiconductor layer 300 may be sequentially formed by a sputtering or deposition process. The insulating layer 200 may also be formed by a coating and curing process.

The thicknesses of the metal layer 100, the insulating layer 200, and the semiconductor layer 300 are not particularly limited.

In order to prevent the finally obtained metal light-shielding layer 1211, buffer layer 1212 and active layer 1213 from being too thick, the subsequent film layers are broken due to too large sidewall gradient angle during deposition. In one embodiment of the present invention, the thickness of the metal layer 100 is

The insulating layer 200 has a thickness of->

The thickness of the semiconductor layer 300 is

S2, as shown in fig. 9, a photoresist pattern 400 is formed on the semiconductor layer 300 through a photolithography process.

For example, a photoresist may be formed on the semiconductor layer 300, and then, a photoresist completely remaining portion and a photoresist completely removed portion may be formed through exposure, development, and the like, and the photoresist completely removed portion may be removed, thereby obtaining the photoresist pattern 400.

S3, etching the semiconductor layer 300, the insulating layer 200 and the metal layer 100 under the mask of the photoresist pattern 400 to obtain an active layer 1213, a buffer layer 1212 and a metal light shielding layer 1211 which are contained in each thin film transistor; as shown in fig. 10, for each thin film transistor, an orthographic projection of the metal light-shielding layer 1211 in the thickness direction thereof covers an orthographic projection of the buffer layer 1212 in the thickness direction thereof, and an orthographic projection of the buffer layer 1212 in the thickness direction thereof covers an orthographic projection of the active layer 1213 in the thickness direction thereof.

Wherein, under the mask of the photoresist pattern 400, the semiconductor layer 300, the insulating layer 200, and the metal layer 100 are etched; the method can comprise the following steps:

s31, the semiconductor layer 300 is etched to obtain an active layer 1213, and the active layer 1213 has a first etching deviation k1 with respect to the photoresist pattern 400, so as to obtain the structure shown in fig. 11.

The semiconductor layer 300 may be etched by a wet etching process, and the first etching deviation k1 may be formed by a drill etching.

S32, etching the insulating layer 200 to obtain a buffer layer 1212, so that the buffer layer 1212 has a second etching deviation k2 with respect to the photoresist pattern 400, where the second etching deviation k2 is smaller than the first etching deviation k1, and the structure shown in fig. 12 is obtained.

Wherein the insulating layer 200 may be etched by a dry etching process.

S33, etching the metal layer 100 to obtain a metal light-shielding layer 1211, so that the metal light-shielding layer 1211 has a third etching deviation k3 with respect to the photoresist pattern 400, and the third etching deviation k3 is smaller than the second etching deviation k2, thereby obtaining the structure shown in fig. 13.

The metal layer 100 may be etched by a dry etching process or a wet etching process.

If the buffer layer 1212 is etched in place at a time, the formation of the third etching deviation k3 is easily affected by the etching due to the drilling when the metal layer 100 is etched by the wet etching process.

Based on this, in an embodiment of the present invention, the etching the insulating layer 200 may include:

before the metal layer 100 is etched, the insulating layer 200 is etched by a dry etching process to obtain a first insulating pattern 500, such that the first insulating pattern 500 has a fourth etching deviation k4 with respect to the photoresist pattern 400, and the fourth etching deviation k4 is smaller than the third etching deviation k3, such that the structure shown in fig. 14 is obtained.

And after the metal layer 100 is etched, ashing treatment is performed on the photoresist pattern 400 to obtain the structure shown in fig. 15, and the first insulating pattern 500 is etched through a dry etching process to obtain the buffer layer 1212, i.e., the structure shown in fig. 16.

In the embodiment of the present invention, before the metal layer 100 is etched, the first etching is performed on the insulating layer 200 by using a dry etching process to obtain the first insulating pattern 500, so that the fourth etching deviation k3 of the first insulating pattern 500 is smaller than the third etching deviation k3, that is, when the metal layer 100 is etched by using a wet etching process, the third etching deviation k3 is formed by using a drill etching, and then, the second etching is performed on the insulating layer 200 by using a dry etching process to remove the portion of the first insulating pattern 500 protruding from the metal light shielding layer 1211.

It should be noted that, in the whole process, in order to make the finally obtained third etching deviation k3 smaller than the second etching deviation k2 and the second etching deviation k2 smaller than the first etching deviation k1, when etching the semiconductor layer 300 by the wet etching process, the etching deviation of the buffer layer 1212 (i.e., the second etching deviation k 2) and the etching deviation of the metal light-shielding layer 1211 (i.e., the third etching deviation k 3) need to be considered, and in this case, the semiconductor layer 300 may be etched by a sufficiently large etching deviation (for example, the etching deviation may be increased by lengthening the etching time).

It should be noted that, in the whole etching process, according to the etching deviations of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 and the slope angle distribution of the sidewalls caused by the etching process, the sidewalls of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 may be continuous slopes as shown in fig. 5, or discontinuous as shown in fig. 16, that is, the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 are stepped.

Here, the size of the slope angles of the sidewalls of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 is not particularly limited.

In an embodiment of the invention, as shown in fig. 5, a slope angle θ 1 of a sidewall of the metal light-shielding layer 1211 is greater than 0 degree and equal to or less than 90 degrees, a slope angle θ 2 of a sidewall of the buffer layer 1212 is greater than 0 degree and equal to or less than 90 degrees, and a slope angle θ 3 of a sidewall of the active layer 1213 is greater than 0 degree and equal to or less than 90 degrees.

For example, the slope angle θ 1 of the sidewall of the metal light-shielding layer 1211 may be any one of 20 degrees, 30 degrees, 50 degrees, 80 degrees and 90 degrees, and the slope angle θ 2 of the sidewall of the buffer layer 1212 may be any one of 30 degrees, 45 degrees, 60 degrees, 70 degrees and 90 degrees; the slope angle θ 3 of the sidewall of the active layer 1213 may be any of 30 degrees, 40 degrees, 45 degrees, 50 degrees, 60 degrees, 70 degrees and 90 degrees.

Therefore, in the embodiment of the invention, at least one of the metal light shielding layer 1211, the buffer layer 1212 and the active layer 1213 can be prevented from having an excessively large gradient angle, so that the subsequent film layer is easy to break during deposition, thereby easily causing corrosion or short circuit.

It should be noted that, based on the above slope angle range, in another embodiment of the present invention, the ashing process is performed on the photoresist pattern 400 and the etching is performed on the first insulating pattern 500 through the dry etching process at the same time; alternatively, ashing treatment of the photoresist pattern 400 and etching of the first insulation pattern 500 through a dry etching process are alternately performed.

In the embodiment of the present invention, in a case where the ashing process is performed on the photoresist pattern 400 and the etching is performed on the first insulating pattern 500 through the dry etching process, the ashing gas and the etching gas may be mixed, the film layer etching rate and the ashing rate of the photoresist pattern 400 are affected by different proportions of the gases, and the proportion of the etching gas and the ashing gas is adjusted to control the slope angle θ 2 of the buffer layer 1212, and in a case where the slope angles of the sidewalls of the metal light-shielding layer 1211 and the active layer 1213 are constant, the sidewalls of the metal light-shielding layer 1211, the buffer layer 1212, and the active layer 1213 may form a continuous slope, as shown in fig. 5, which facilitates the deposition of the subsequent film layer and prevents the fracture of the subsequent film layer.

In the case where the ashing process is performed on the photoresist pattern 400 and the etching of the first insulating pattern 500 is performed alternately by the dry etching process, the film layer etching may be performed after the ashing process is performed on the photoresist pattern 400, and the film layer gradually forms a slope by the continuous film layer etching and the ashing process of the photoresist pattern 400. The number and time of ashing of the photoresist pattern 400 determine the size of the slope angle, and as the number of ashing of the photoresist pattern 400 increases and the time increases, a smaller slope angle (e.g., θ 2 shown in fig. 17) can be obtained while smoothing the slope. Similarly, the slope angle of the buffer layer 1212 can be controlled, and the sidewall of the metal light-shielding layer 1211, the sidewall of the buffer layer 1212, and the sidewall of the active layer 1213 can be formed into a continuous slope when the slope angles of the sidewalls of the metal light-shielding layer 1211 and the active layer 1213 are constant.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of preparing a substrate, comprising:

sequentially forming a metal layer, an insulating layer and a semiconductor layer on a substrate;

forming a photoresist pattern on the semiconductor layer through a photolithography process;

etching the semiconductor layer, the insulating layer and the metal layer under the mask of the photoresist pattern to obtain an active layer, a buffer layer and a metal shading layer contained in each thin film transistor;

for each thin film transistor, the orthographic projection of the metal light shielding layer along the thickness direction of the metal light shielding layer covers the orthographic projection of the buffer layer along the thickness direction of the metal light shielding layer, and the orthographic projection of the buffer layer along the thickness direction of the metal light shielding layer covers the orthographic projection of the active layer along the thickness direction of the active layer;

the metal shading layer, the buffer layer and the side wall of the active layer are continuous inclined planes; and/or the metal shading layer, the buffer layer and the side wall of the active layer are in a step shape;

etching the semiconductor layer, the insulating layer and the metal layer under the mask of the photoresist pattern; the method comprises the following steps:

etching the semiconductor layer to obtain the active layer, so that the active layer has a first etching deviation relative to the photoresist pattern;

etching the insulating layer to obtain the buffer layer, wherein the buffer layer has a second etching deviation relative to the photoresist pattern, and the second etching deviation is smaller than the first etching deviation;

etching the metal layer to obtain the metal shading layer, so that the metal shading layer has a third etching deviation relative to the photoresist pattern, and the third etching deviation is smaller than the second etching deviation;

etching the insulating layer under the mask of the photoresist pattern; the method comprises the following steps: before the metal layer is etched, etching the insulating layer through a dry etching process to obtain a first insulating pattern, wherein the first insulating pattern has a fourth etching deviation relative to the photoresist pattern, and the fourth etching deviation is smaller than the third etching deviation;

and after the metal layer is etched, ashing the photoresist pattern, and etching the first insulating pattern by a dry etching process to obtain the buffer layer.

2. The method for producing a substrate according to claim 1,

ashing the photoresist pattern and etching the first insulating pattern by a dry etching process are performed simultaneously, or

And performing ashing treatment on the photoresist pattern and alternately performing etching on the first insulating pattern through a dry etching process.

3. The substrate is characterized by comprising a substrate and a plurality of thin film transistors which are arranged on the substrate and positioned in each sub-pixel area;

each thin film transistor comprises a metal shading layer, a buffer layer and an active layer which are sequentially stacked along the direction far away from the substrate;

wherein, for each thin film transistor, the orthographic projection of the metal light shielding layer along the thickness direction covers the orthographic projection of the buffer layer along the thickness direction, and the orthographic projection of the buffer layer along the thickness direction covers the orthographic projection of the active layer along the thickness direction;

the side walls of the metal shading layer, the buffer layer and the active layer are continuous inclined planes; and/or the side walls of the metal shading layer, the buffer layer and the active layer are in a step shape;

the substrate is prepared by the following method:

for each thin film transistor, the orthographic projection of the metal shading layer in the thickness direction covers the orthographic projection of the buffer layer in the thickness direction, and the orthographic projection of the buffer layer in the thickness direction covers the orthographic projection of the active layer in the thickness direction;

the side walls of the metal shading layer, the buffer layer and the active layer are continuous inclined planes; and/or the metal shading layer, the buffer layer and the side wall of the active layer are in a step shape;

etching the insulating layer under the mask of the photoresist pattern; the method comprises the following steps: before the metal layer is etched, etching the insulating layer by a dry etching process to obtain a first insulating pattern, wherein the first insulating pattern has a fourth etching deviation relative to the photoresist pattern, and the fourth etching deviation is smaller than the third etching deviation;

4. The substrate of claim 3,

the thickness of the metal shading layer is

The thickness of the buffer layer is

The active layer has a thickness of

5. The substrate according to claim 3 or 4,

the slope angle of the side wall of the metal shading layer is larger than 0 degree and smaller than or equal to 90 degrees;

the slope angle of the side wall of the buffer layer is greater than 0 degree and less than or equal to 90 degrees;

the slope angle of the side wall of the active layer is larger than 0 degree and smaller than or equal to 90 degrees.

6. The substrate of claim 3,

each sub-pixel region is also provided with a capacitor, and the capacitor comprises a first pole and a second pole;

a plurality of said thin film transistors including a driving TFT and at least one switching TFT;

the driving TFT also comprises a grid electrode, a first electrode and a second electrode, wherein the first electrode of the capacitor and the grid electrode of the driving TFT are in the same layer and are insulated from each other, the second electrode of the capacitor and the first electrode and the second electrode of the driving TFT are in the same layer and are insulated from each other, and the second electrode of the capacitor is electrically connected with the grid electrode of the driving TFT.

7. The substrate of claim 6,

the at least one switching TFT includes a first switching TFT, the first switching TFT further includes a gate electrode, a first pole and a second pole, the first pole of the first switching TFT is electrically connected with the data line, and the second pole of the first switching TFT is electrically connected with the second pole of the capacitor.

8. The OLED display panel is characterized by comprising a TFT backboard and an OLED device arranged on the TFT backboard;

the TFT backplane is the substrate of any one of claims 3-7.

9. The OLED display panel of claim 8,

the OLED device is a bottom-emitting OLED device.

10. The OLED display panel of claim 9,

the OLED device is a white OLED device, the OLED display panel further comprises a color filter layer arranged between the white OLED device and the TFT backboard, the color filter layer comprises a plurality of color filter units, each color filter unit is correspondingly arranged in one sub-pixel area, and the plurality of color filter units comprise a first color filter unit, a second color green light unit and a third color filter unit;

the first color, the second color, and the third color are three primary colors.