CN111863926B - Display substrate, preparation method thereof and mask - Google Patents
Display substrate, preparation method thereof and mask Download PDFInfo
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- CN111863926B CN111863926B CN202010760861.5A CN202010760861A CN111863926B CN 111863926 B CN111863926 B CN 111863926B CN 202010760861 A CN202010760861 A CN 202010760861A CN 111863926 B CN111863926 B CN 111863926B
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- 239000000758 substrate Substances 0.000 title claims abstract description 109
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims description 164
- 238000002834 transmittance Methods 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
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- 238000010586 diagram Methods 0.000 description 10
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- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
- H10K59/179—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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Abstract
The embodiment of the invention provides a display substrate, a preparation method thereof and a mask plate, which can avoid the phenomenon of poor display of the display substrate, and comprises the following steps: a substrate; a first conductive pattern layer disposed on the substrate, including a plurality of first conductive patterns; the first insulating layer is positioned on one side, far away from the substrate, of the first conductive pattern layer, and a plurality of opening parts are formed in the first insulating layer; the second conductive pattern layer can reflect light and is positioned on one side of the first insulating layer, which is far away from the substrate, and the second conductive pattern layer comprises a plurality of approximately parallel conductive wires; each conductive line is electrically connected with at least one first conductive pattern through at least one opening, and the part of the conductive line on the at least one opening is conformal with the at least one opening; each opening portion includes a first sidewall and a second sidewall opposite to each other in a width direction of the conductive line, and inclination directions of the first sidewall and the second sidewall of different opening portions are the same; the difference of the slope angles of the first side wall and the second side wall corresponding to the at least two conductive lines is larger than 5 degrees.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a mask plate.
Background
In the prior art, a plurality of metal layers are usually included in the display panel, and in order to reduce the resistance of the metal layers, the metal layers are usually configured as double-layer metal layers, and the electrical connection between the adjacent metal layers is realized through an opening on an insulating layer between the double-layer metal layers.
Disclosure of Invention
The embodiment of the invention provides a display substrate, a preparation method thereof and a mask plate, which can avoid the phenomenon of poor display of the display substrate.
In one aspect, an embodiment of the present invention provides a display substrate, including:
a substrate; a first conductive pattern layer disposed on the substrate, the first conductive pattern layer comprising: a plurality of first conductive patterns.
The first insulating layer is positioned on one side, far away from the substrate, of the first conductive pattern layer, and the first insulating layer is provided with a plurality of opening parts.
And the second conductive pattern layer can reflect light and is positioned on one side of the first insulating layer far away from the substrate, and the second conductive pattern layer comprises a plurality of approximately parallel conductive wires.
Each conductive line is electrically connected with at least one first conductive pattern through at least one opening part, and the part of the conductive line on the at least one opening part is conformal to the at least one opening part; each opening portion comprises a first side wall and a second side wall which are opposite along the width direction of the conductive wire, the inclination directions of the first side walls of different opening portions are the same, and the inclination directions of the second side walls of different opening portions are the same; the difference of the slope angles of the first side walls corresponding to at least two of the conductive lines is larger than 5 degrees, and/or the difference of the slope angles of the second side walls corresponding to at least two of the conductive lines is larger than 5 degrees.
Optionally, the range of the slope angle is 20 degrees to 80 degrees.
Optionally, the plurality of substantially parallel conductive lines include at least one of a gate line and a light emitting control line, or at least one of a data line, a power line and a clock signal line.
Optionally, the second conductive pattern layer further includes: a plurality of first electrodes.
The display substrate further includes: and the first electrode, the light-emitting functional layer and the second electrode form a light-emitting device.
The first insulating layer is a flat layer.
Optionally, the method further includes: the second insulating layer and the third conductive pattern layer are sequentially arranged along one side, close to the substrate, of the first conductive pattern layer, and the third conductive pattern layer comprises a plurality of third conductive patterns; a third conductive pattern and the first conductive pattern are formed on the second insulating layer.
In another aspect, an embodiment of the present disclosure provides a mask for manufacturing the first insulating layer of the display substrate, including: a mask body; a plurality of light-transmitting portions provided on the mask body, each of the light-transmitting portions being configured to form an opening portion on one of the first insulating layers.
Each light-transmitting part comprises a full-transmission pattern which has the maximum transmission rate; at least one of the light-transmitting portions further includes: and semi-transparent patterns which are positioned on at least one side of the full-transparent patterns and are connected with the full-transparent patterns along the width direction of the conductive wires in the display substrate, wherein the transmittance of each semi-transparent pattern is smaller than the maximum transmittance, and the transmittances of the semi-transparent patterns are configured to form a slope angle of one side wall of the opening part corresponding to the semi-transparent patterns.
Optionally, the semi-transparent pattern is a halftone mask pattern; or the semi-transparent pattern is a gray tone mask pattern.
In another aspect, an embodiment of the present invention provides a mask for manufacturing a first insulating layer in the display substrate, including: a mask body; a plurality of light shielding portions provided on the mask body, each light shielding portion being configured to form an opening portion on one of the first insulating layers.
Each of the light shielding portions includes a light shielding pattern having a minimum transmittance; at least one of the light shielding portions further includes: and semi-transparent patterns which are located on at least one side of the light-shielding patterns and are connected with the light-shielding patterns along the width direction of the conductive wires in the display substrate, wherein the transmittance of each semi-transparent pattern is greater than the minimum transmittance, and the transmittance of the semi-transparent patterns is configured to form a slope angle of one side wall of the opening part corresponding to the semi-transparent patterns.
Optionally, the semi-transparent pattern is a halftone mask pattern; or the semi-transparent pattern is a gray tone mask pattern.
In another aspect, an embodiment of the present invention provides a method for manufacturing a display substrate, including: a first conductive pattern layer is formed on a substrate, the first conductive pattern layer including a plurality of first conductive patterns.
Forming a first insulating film on the substrate on which the first conductive pattern layer is formed, and exposing and developing the first insulating film by using the mask plate to form a first insulating layer; the first insulating layer includes a plurality of opening portions.
Forming a second conductive pattern layer on the substrate on which the first insulating layer is formed, the second conductive pattern layer being reflective, the second conductive pattern layer including a plurality of substantially parallel conductive lines.
Each conductive line is electrically connected with at least one first conductive pattern through at least one opening, and the part of the conductive line on the at least one opening is conformal with the at least one opening; each opening portion comprises a first side wall and a second side wall which are opposite along the width direction of the conductive wire, the inclined directions of the first side walls of different opening portions are the same, and the inclined directions of the second side walls of different opening portions are the same; the difference of the slope angles of the first side walls corresponding to the at least two conductive wires is larger than 5 degrees, and/or the difference of the slope angles of the second side walls corresponding to the at least two conductive wires is larger than 5 degrees.
Optionally, before forming the first conductive pattern layer on the substrate, a third conductive pattern layer and a second insulating layer are sequentially formed on the substrate.
The third conductive layer includes a plurality of third conductive patterns; a third conductive pattern is electrically connected to the first conductive pattern through a via on the second insulating layer.
The conductive line is electrically connected to at least one third conductive pattern through at least one of the first conductive patterns.
Optionally, after the first insulating film is exposed and developed, baking is performed to form a first insulating layer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a display panel according to the related art;
FIG. 2 is a schematic diagram of a display panel according to the related art;
FIG. 3A is a schematic view of a display substrate according to the related art;
FIG. 3B is a cross-sectional view taken along direction AA' in FIG. 3A;
fig. 4A is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;
FIG. 4B is a cross-sectional view taken along line BB' of FIG. 4A according to an embodiment of the present invention;
FIG. 5 is a schematic view of another display substrate according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another display substrate according to an embodiment of the present invention;
FIG. 7 is a schematic view of another display substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a mask according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of another mask according to an embodiment of the present invention;
fig. 10A is a schematic structural diagram of a semi-transmissive pattern according to an embodiment of the disclosure;
fig. 10B is a schematic structural diagram of another semi-transmissive pattern according to an embodiment of the disclosure;
fig. 11 is a schematic structural diagram of another semi-transmissive pattern according to an embodiment of the disclosure;
FIG. 12 is a schematic structural diagram of another mask according to an embodiment of the present invention;
fig. 13 is a schematic flow chart illustrating a method for manufacturing a display substrate according to an embodiment of the present invention;
fig. 14 is a schematic view of a manufacturing process of a method for manufacturing a display substrate according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a Display device, which includes a Display panel, where the Display panel may be a Liquid Crystal Display (LCD) panel or a self-luminous Display panel. The self-luminous display panel includes one of an electroluminescent display panel and a photoluminescent display panel. The electroluminescent display panel may be an Organic Light-Emitting Diode (OLED) display panel or a Quantum Dot electroluminescent (QLED) display panel, and the photoluminescent display panel may be a Quantum Dot electroluminescent display panel.
When the display panel is a liquid crystal display panel, as shown in fig. 1, the liquid crystal display panel 1 mainly includes a display substrate 11, a counter substrate 12, and a liquid crystal layer 13 provided between the display substrate 11 and the counter substrate 12.
In some embodiments, as shown in fig. 1, the display substrate 11 includes a thin film transistor 111, a pixel electrode 112, and a common electrode 113 disposed on a first substrate 110. In which the pixel electrode 112 and the common electrode 113 may be disposed at the same layer, in which case the pixel electrode 112 and the common electrode 113 are each a comb-tooth structure including a plurality of strip-shaped sub-electrodes. The pixel electrode 112 and the common electrode 113 may also be disposed at different layers, in which case the first insulating layer 114 is disposed between the pixel electrode 112 and the common electrode 113, as shown in fig. 1. In the case where the common electrode 113 is provided between the thin film transistor 111 and the pixel electrode 112, as shown in fig. 1, a second insulating layer 115 is further provided between the common electrode 113 and the thin film transistor 111.
In other embodiments, the common electrode 113 is disposed on the opposite substrate 12.
As shown in fig. 1, the opposite substrate 12 includes a second substrate 120 and a Color filter layer 121 disposed on the second substrate 120, in which case, the opposite substrate 12 may also be referred to as a Color Filter (CF). The color filter layer 121 at least includes a first color filter unit, a second color filter unit, and a third color filter unit, and the first color filter unit, the second color filter unit, and the third color filter unit are located in one sub-pixel in a one-to-one correspondence. Wherein the first, second and third colors are three primary colors, for example red, green and blue. The opposite substrate 12 further includes a black matrix pattern 122 disposed on the second substrate 120, the black matrix pattern 122 for spacing the first color filter unit, the second color filter unit, and the third color filter unit.
As shown in fig. 1, the liquid crystal display panel 1 further includes an upper polarizer 14 provided on the side of the counter substrate 12 away from the liquid crystal layer 13, and a lower polarizer 15 provided on the side of the display substrate 11 away from the liquid crystal layer 13.
As for the self-luminous display panel, the self-luminous display panel is taken as an example of the electroluminescence display panel 3. As shown in fig. 2, the electroluminescent display panel includes a display substrate 11, and the display substrate 11 includes a third substrate 310 and a pixel driving circuit provided on the third substrate 310 and located in each sub-pixel. The pixel driving circuit includes a plurality of thin film transistors 111, and one of the thin film transistors is a driving transistor.
In addition, the display panel further includes a light emitting device in each sub-pixel, and an encapsulation layer 32 covering the light emitting device. The light emitting device includes a first electrode 311, a light emitting function layer 312, and a second electrode 313. For example, the first electrode 311 is an anode, the second electrode 313 is a cathode, and the anode is electrically connected to the pixel driving circuit through a via hole on the planarization layer 315. One opening region of the pixel defining layer 314 is provided one for each light emitting device.
The light emitting device may be one of a bottom emission type light emitting device, a top emission type light emitting device, and a dual emission type light emitting device.
In some embodiments, the light emitting functional layer 312 includes a light emitting layer. In other embodiments, the light emitting function layer 312 includes one or more of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL) in addition to the light emitting layer.
The structure of the photoluminescent display panel is similar to that of the electroluminescent display panel 3, and is not described in detail here.
Based on the above, the display panel includes the display substrate 11 regardless of the liquid crystal display panel, the electroluminescence display panel, or the photoluminescence display panel, and the performance of the display substrate 11 has a great influence on the display effect of these display panels.
As shown in fig. 3, an embodiment of the present invention provides a display substrate, which includes a substrate 10, a first conductive pattern layer 40, a first insulating layer 50, and a second conductive pattern layer 60.
The first conductive pattern layer 40 includes a plurality of first conductive patterns 401. The first insulating layer 50 has a plurality of openings 501. The second conductive pattern layer 60 is reflective and located on a side of the first insulating layer 50 away from the substrate 10, and the second conductive pattern layer 60 includes a plurality of substantially parallel conductive lines 601.
Each of the conductive lines 601 is electrically connected to at least one of the first conductive patterns 401 through at least one of the openings 501, and a portion of the conductive line 601 on the at least one of the openings 501 is conformal with the at least one of the openings 501. Each opening 501 includes a first sidewall 501a and a second sidewall 501b opposite to each other in the width direction of the conductive line 601, and the first sidewalls 501a of different openings 501 are inclined in the same direction and the second sidewalls 501b of different openings are inclined in the same direction. The difference of the slope angles of the first side walls 501a corresponding to at least two conductive lines 601 is greater than 5 °, or the difference of the slope angles of the second side walls 501b corresponding to at least two conductive lines 601 is greater than 5 °, or the difference of the slope angles of the first side walls 501a corresponding to at least two conductive lines 601 is greater than 5 ° and the difference of the slope angles of the second side walls 501b corresponding to at least two conductive lines 601 is greater than 5 °.
It should be noted that "substantially parallel" refers to an average value of the angular values of the plurality of electrically conductive lines when they are not parallel within an acceptable deviation range for a particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).
Conformal means that, with respect to the surface of the first insulating layer 50 on the side away from the substrate 10, the portion of the conductive line 601 on the opening 501 is recessed toward the side close to the substrate 10, and is electrically connected to at least one first conductive pattern 401 through a via on the first insulating layer 50. As shown in fig. 4A, one conductive line 601 is electrically connected to one first conductive pattern 401 through a portion on one opening 501, or as shown in fig. 5, one conductive line 601 is electrically connected to one first conductive pattern 401 through a portion on a plurality of openings 501, or as shown in fig. 6, one conductive line is electrically connected to a plurality of first conductive patterns 401 through a plurality of openings 501.
In the related art, for a Display panel product, for example, an Organic light emitting semiconductor (OLED) Display panel 2 which is currently rapidly developed includes, as shown in fig. 3, a Display Area 20 (Active Area) and a peripheral Area 21, a control circuit such as a Gate On Array (GOA) circuit is disposed in the peripheral Area 21 of the Display panel 2, and a plurality of signal lines 22 connected to the control circuit are disposed in the peripheral Area 21 and the Display Area 20. The GOA circuit comprises a Gate (Gate) GOA circuit and an EM (enable) GOA circuit. In order to reduce the resistance of the signal line 22, the signal line is generally provided as a double-layered trace. The double-layer wirings comprise a double-layer Source Drain (SD) layer, or the SD layer and other layers form the double-layer wirings. An insulating layer is arranged between the double-layer wires, and the double-layer wires are electrically connected through an opening part on the insulating layer. When the double-layer traces comprise a reflective material, if the display panel is in a black state and the light in the external environment is strong, the traces near the upper layer of the display panel 2 at the side wall of the opening part reflect the strong light in the external environment, the reflected light enters the human eyes 23 at a specific angle, and the human eyes 23 observe a plurality of signal lines 22 at a specific angle, so that the display panel has a poor appearance.
In order to solve the above problem, in the display substrate provided in the embodiment of the present invention, each of the openings 501 includes a first sidewall 501a and a second sidewall 501b, the first sidewall 501a and the second sidewall 501b of different openings 501 have the same inclination direction, but the inclination angles of the first sidewalls 501a corresponding to at least two conductive lines 601 are different, for example, α and β, respectively, in this case, if light rays incident from the outside to the display substrate are regarded as parallel light, then for the first sidewalls 501a of the openings 501 corresponding to different conductive lines 601, because the inclination angles α and β are different, for the first sidewalls 501a of the openings 501 corresponding to different conductive lines 601, the incident angles of the corresponding light rays are different, and the reflection angles of the corresponding light rays are also different, so the directions of the light rays reflected by the first sidewalls 501a of the openings 501 corresponding to different conductive lines 601 are different, in this case, because the reflected light enters the human eyes 23 at least two different angles, and the human eyes 23 do not observe a plurality of conductive lines 601 at a specific same angle, thereby avoiding the display phenomenon of the display substrate 11.
Optionally, the range of the slope angle is 20 to 80 °. Exemplary values for the ramp angle may be 25 °,67 °,70 ° or 75 °.
Optionally, the plurality of substantially parallel conductive lines include at least one of a gate line and a light emitting control line, or at least one of a data line, a power line and a clock signal line.
The display substrate is divided into a plurality of independent sub-pixel areas by the grid lines and the data lines.
Optionally, as shown in fig. 7, the second conductive pattern layer 60 further includes a plurality of first electrodes 610. The display substrate further includes: and a light-emitting functional layer 620 and a second electrode 630 sequentially disposed on a side of each first electrode 610 away from the substrate 10, wherein the first electrode 610, the light-emitting functional layer 620 and the second electrode 630 constitute a light-emitting device. The first insulating layer 50 is a flat layer.
Illustratively, the first electrode 610 is an anode of the light emitting device, the second electrode 80 is a cathode, and the conductive line 601 and the anode of the light emitting device are the same material. The anode of the light emitting device is electrically connected to the first conductive pattern 401 through the via hole on the planarization layer.
Optionally, as shown in fig. 7, the display substrate further includes: the second insulating layer 70 and the third conductive pattern layer 80 are sequentially arranged along the first conductive pattern layer 401 on the side close to the substrate 10, the third conductive pattern layer 80 comprises a plurality of third conductive patterns 801, and one third conductive pattern 801 is electrically connected with one first conductive pattern 401 through the second insulating layer 70. The conductive line 601 is electrically connected with the at least one third conductive pattern 801 through the at least one first conductive pattern 401.
The first insulating layer 50 and the second insulating layer 70 are two flat layers, respectively. For example, as shown in fig. 8, the third conductive pattern layer 80 is an SD layer, that is, the third conductive pattern 801 may be a source or a drain of a driving transistor in the pixel driving circuit, where the conductive line 601 is electrically connected to the source or the drain, and the conductive line 601 is a power line.
On the other hand, as shown in fig. 8, an embodiment of the present invention provides a mask 9 for manufacturing the first insulating layer in the display substrate, including: a mask body 91, a plurality of light-transmissive portions 911 provided on the mask body 91, each light-transmissive portion 911 being configured to form an opening portion on one first insulating layer.
Each of the light-transmitting portions 911 includes a transflective pattern 9111, the transflective pattern 9111 having a maximum transmittance. The at least one light-transmissive portion 911 further includes semi-transmissive patterns 9112 located at least one side of the semi-transmissive pattern 911 and connected to the semi-transmissive pattern 911 along a width direction of the conductive line in the display substrate, a transmittance of each semi-transmissive pattern 9112 is less than a maximum transmittance, and a transmittance of the semi-transmissive pattern 912 is configured to form a slope angle of a sidewall of an opening portion corresponding to the semi-transmissive pattern 9112.
The material of the first insulating layer is a positive photoresist, the transflective pattern 911 corresponds to a portion of the opening portion in the first insulating layer penetrating through the first insulating layer, the transflective pattern 912 corresponds to a slope angle of one sidewall of the opening portion in the first insulating layer, and the magnitude of the slope angle of one sidewall of the opening portion corresponding to the transflective pattern 912 can be adjusted by adjusting the transmittance of the transflective pattern 912 to light.
Alternatively, as shown in fig. 8 to 10, the semi-transmissive pattern 9112 is a halftone mask pattern, or, as shown in fig. 11, the semi-transmissive pattern 9112 is a gray tone mask pattern.
When the semi-transmissive pattern 9112 is a halftone mask pattern, the semi-transmissive pattern 9112 includes a thin semi-transparent metal layer, and the transmittance of the semi-transmissive pattern 9112 can be adjusted by adjusting the thickness of the semi-transparent metal layer.
For example, as shown in fig. 10A and 10B, the semi-transmissive pattern 9112 includes at least one first partial semi-transmissive pattern 9112a and at least one first partial semi-transmissive pattern 9112B, and a line width d1 of the first partial semi-transmissive pattern 9112a is greater than 0um and less than or equal to 6um. The transmittance of the first partially translucent pattern 9112b is the same as that of the translucent pattern, the first partially translucent pattern 9112a is a semitransparent metal, and the transmittance of the translucent pattern 9112 can be adjusted by adjusting the thickness of the semitransparent metal, the line width of the first partially translucent pattern 9112a, and the line width and the number of the first partially translucent pattern 9112 b.
When the semi-transparent pattern 9112 is a gray tone mask pattern, the semi-transparent pattern 9112 is made of shading metal, the transmittance of the semi-transparent pattern 9112 can be adjusted by adjusting the line width of the shading metal, and the principle is that when exposure is carried out and light passes through the slit structure, optical phenomena such as scattering and diffraction occur, so that the exposure of the photoresist corresponding to the semi-transparent pattern 9112 is different from the exposure of other regions.
For example, as shown in fig. 11, the semi-transmissive pattern 9112 includes at least one first partial light-shielding pattern 9112c and a second partial full-transmissive pattern 9112d, a line width d2 of the first partial light-shielding pattern 9112c is greater than 0um and less than or equal to 2um, and a line width d3 of the second partial full-transmissive pattern 9112d is greater than or equal to 0.75um and less than or equal to 2um. The transmittance of the semi-transmissive pattern 9112 can be adjusted by adjusting the line widths of the first partial light-shielding pattern 9112c and the second partial full-transmissive pattern 9112 d.
In another aspect, as shown in fig. 12, an embodiment of the invention provides a mask 9 for manufacturing a first insulating layer in the display substrate, including: the mask body 91, a plurality of light shielding portions 913 disposed on the mask version body, each light shielding portion 913 being configured to form an opening on one first insulating layer.
Each of the light shielding portions 913 includes a light shielding pattern 9131, the light shielding pattern 9131 having a minimum transmittance, and the at least one light shielding portion 913 further includes: and semi-transmissive patterns 9112 located at least one side of the light-shielding patterns 9131 and connected to the light-shielding patterns 9131 along the width direction of the conductive lines in the display substrate, the transmittance of each semi-transmissive pattern 9112 being greater than the minimum transmittance, the transmittance of the semi-transmissive pattern 9112 being configured to form a slope angle of a sidewall of the opening portion corresponding to the semi-transmissive pattern 912.
The material of the first insulating layer is a negative photoresist, the light-shielding pattern 931 corresponds to a portion of the opening portion in the first insulating layer, which penetrates through the first insulating layer, the semi-transmissive pattern 9112 corresponds to a slope angle of one side wall of the opening portion in the first insulating layer, and the size of the slope angle of one side of the opening portion corresponding to the semi-transmissive pattern 9112 can be adjusted by adjusting the transmittance of the semi-transmissive pattern 9112 to light.
Optionally, the semi-transparent pattern 9112 is a halftone mask pattern; alternatively, the semi-transmissive pattern 9112 is a gray-tone mask pattern.
The principle of the halftone mask pattern and the gray-tone mask pattern is similar to that described above, and is not described herein again.
In another aspect, as shown in fig. 13, an embodiment of the invention provides a method for manufacturing a display substrate, including:
s1, forming a first conductive pattern layer 40 on the substrate, the first conductive pattern layer 40 including a plurality of first conductive patterns 401.
S2, forming a first insulating film on the substrate with the first conductive pattern layer 40, and exposing and developing the first insulating film by using a mask plate 91 to form a first insulating layer 50; the first insulating layer 50 includes a plurality of openings 501.
And S3, forming a second conductive pattern layer 60 on the substrate with the first insulating layer 50, wherein the second conductive pattern layer 60 can reflect light, and the second conductive pattern layer 60 comprises a plurality of approximately parallel conductive lines 601.
As shown in fig. 14, each of the conductive lines 601 is electrically connected to at least one of the first conductive patterns 401 through at least one of the openings 501, and a portion of the conductive line 601 on the at least one of the openings 501 is conformal with the at least one of the openings 501; each opening portion 501 includes a first sidewall 501a and a second sidewall 501b opposing each other in the width direction of the conductive line 601, the inclination direction of the first sidewall 501a of different opening portions 501 is the same, and the inclination direction of the second sidewall 501b of different opening portions 501 is the same; the difference between the slope angles of the first sidewalls 501a corresponding to at least two conductive lines 601 is greater than 5 °, and/or the difference between the slope angles of the second sidewalls 501b corresponding to at least two conductive lines 601 is greater than 5 °.
The embodiment of the present invention provides a display substrate prepared by a preparation method of the display substrate, each opening 501 includes a first sidewall 501a and a second sidewall 501b, the inclined directions of the first sidewall 501a and the second sidewall 501b of different openings 501 are the same, but the slope angles of the first sidewalls 501a corresponding to at least two conductive wires 601 are different, for example, α and β, respectively, at this time, if the light incident from the outside to the display substrate is regarded as parallel light, then for the first sidewalls 501a of the openings 501 corresponding to different conductive wires 601, because the slope angles α and β are different, for the first sidewalls 501a of the openings 501 corresponding to different conductive wires 601, the incident angles of the light corresponding to the first sidewalls 501a of the openings 501 corresponding to different conductive wires 601 are different, and the reflection angles of the light corresponding to the first sidewalls 501a are also different, at this time, since this reflected light enters human eyes 23 at least two different angles, the human eyes 23 will not observe a plurality of conductive wires 601 at the same specific angle, and the display phenomenon of the display substrate 11 is avoided.
Optionally, the method for manufacturing a display substrate, before forming the first conductive pattern layer 40 on the substrate 10, further includes:
a third conductive pattern layer 80 and a second insulating layer 70 are sequentially formed on the substrate.
As shown in fig. 7, the third conductive layer 80 includes a plurality of third conductive patterns 801; one third conductive pattern 801 is electrically connected to one first conductive pattern 401 through the via hole on the second insulating layer 70. The conductive line 601 is electrically connected with the at least one third conductive pattern 801 through the at least one first conductive pattern 401.
After the first insulating film is exposed and developed, baking (Oven) is performed to form a first insulating layer. The baking device may be, for example, an oven.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (13)
1. A display substrate, comprising:
a substrate;
a first conductive pattern layer disposed on the substrate, the first conductive pattern layer comprising: a plurality of first conductive patterns;
the first insulating layer is positioned on one side, far away from the substrate, of the first conductive pattern layer, and a plurality of opening parts are formed in the first insulating layer; and
a second conductive pattern layer which is reflective and is located on a side of the first insulating layer away from the substrate, the second conductive pattern layer comprising a plurality of substantially parallel conductive lines;
each conductive line is electrically connected with at least one first conductive pattern through at least one opening, and the part of the conductive line on the at least one opening is conformal with the at least one opening; each opening portion comprises a first side wall and a second side wall which are opposite along the width direction of the conductive wire, the inclination directions of the first side walls of different opening portions are the same, and the inclination directions of the second side walls of different opening portions are the same; the difference of the slope angles of the first side walls corresponding to at least two of the conductive lines is larger than 5 degrees, and/or the difference of the slope angles of the second side walls corresponding to at least two of the conductive lines is larger than 5 degrees.
2. The display substrate of claim 1, wherein the bevel angle is in a range of 20 ° to 80 °.
3. The display substrate according to claim 1, wherein the plurality of substantially parallel conductive lines comprise at least one of a gate line, a light emission control line, or at least one of a data line, a power supply line, and a clock signal line.
4. The display substrate according to claim 1, wherein the second conductive pattern layer further comprises: a plurality of first electrodes;
the display substrate further includes: the light-emitting functional layer and the second electrode are sequentially arranged on one side, away from the substrate, of each first electrode, and the first electrodes, the light-emitting functional layer and the second electrodes form a light-emitting device;
the first insulating layer is a flat layer.
5. The display substrate according to any one of claims 1 to 4, further comprising:
the second insulating layer and the third conductive pattern layer are sequentially arranged along one side, close to the substrate, of the first conductive pattern layer, and the third conductive pattern layer comprises a plurality of third conductive patterns; a third conductive pattern is electrically connected with the first conductive pattern through a via hole on the second insulating layer;
the conductive line is electrically connected with at least one third conductive pattern through at least one of the first conductive patterns.
6. A mask for fabricating the first insulating layer in the display substrate according to any one of claims 1 to 4, comprising:
a mask body;
a plurality of light-transmitting portions provided on the mask body, each light-transmitting portion being configured to form an opening portion on one of the first insulating layers;
each of the light-transmitting portions includes a full-transmission pattern having a maximum transmittance; at least one of the light-transmitting portions further includes: and semi-transparent patterns which are located on at least one side of the semi-transparent patterns and are connected with the semi-transparent patterns along the width direction of the conductive wires in the display substrate, wherein the transmittance of each semi-transparent pattern is smaller than the maximum transmittance, and the transmittance of the semi-transparent patterns is configured to form a slope angle of one side wall of the opening part corresponding to the semi-transparent patterns.
7. The reticle of claim 6,
the semi-transparent pattern is a half-tone mask pattern; or the semi-transparent pattern is a gray tone mask pattern.
8. A reticle for fabricating a first insulating layer in a display substrate according to any one of claims 1 to 4, comprising:
a mask body;
a plurality of light shielding portions provided on the mask body, each light shielding portion being configured to form an opening portion on one of the first insulating layers;
each of the light shielding portions includes a light shielding pattern having a minimum transmittance; at least one of the light shielding portions further includes: and semi-transparent patterns which are located on at least one side of the light-shielding patterns and are connected with the light-shielding patterns along the width direction of the conductive wires in the display substrate, wherein the transmittance of each semi-transparent pattern is greater than the minimum transmittance, and the transmittance of the semi-transparent patterns is configured to form a slope angle of one side wall of the opening part corresponding to the semi-transparent patterns.
9. The reticle of claim 8,
the semi-transparent pattern is a halftone mask pattern; or the semi-transparent pattern is a gray tone mask pattern.
10. A display device comprising the display substrate according to any one of claims 1 to 5.
11. A method for preparing a display substrate is characterized by comprising the following steps:
forming a first conductive pattern layer on a substrate, the first conductive pattern layer including a plurality of first conductive patterns;
forming a first insulating film on the substrate on which the first conductive pattern layer is formed, exposing the first insulating film by using the mask plate according to any one of claims 6 to 9, and developing to form a first insulating layer; the first insulating layer includes a plurality of opening portions;
forming a second conductive pattern layer on the substrate on which the first insulating layer is formed, the second conductive pattern layer being reflective, the second conductive pattern layer including a plurality of substantially parallel conductive lines;
each conductive line is electrically connected with at least one first conductive pattern through at least one opening part, and the part of the conductive line on the at least one opening part is conformal to the at least one opening part; each opening portion comprises a first side wall and a second side wall which are opposite along the width direction of the conductive wire, the inclined directions of the first side walls of different opening portions are the same, and the inclined directions of the second side walls of different opening portions are the same; the difference of the slope angles of the first side walls corresponding to at least two of the conductive lines is larger than 5 degrees, and/or the difference of the slope angles of the second side walls corresponding to at least two of the conductive lines is larger than 5 degrees.
12. The method for manufacturing a display substrate according to claim 11, further comprising:
sequentially forming a third conductive pattern layer and a second insulating layer on the substrate before forming the first conductive pattern layer on the substrate;
the third conductive pattern layer includes a plurality of third conductive patterns; a third conductive pattern is electrically connected with the first conductive pattern through a via hole on the second insulating layer;
the conductive line is electrically connected with at least one third conductive pattern through at least one of the first conductive patterns.
13. The method for manufacturing a display substrate according to claim 11, further comprising:
after the first insulating film is exposed and developed, the first insulating film is baked to form a first insulating layer.
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| CN109638062A (en) * | 2019-01-14 | 2019-04-16 | 京东方科技集团股份有限公司 | Array substrate row driving structure and production method, array substrate, display panel |
| CN110416274A (en) * | 2019-08-02 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of substrate and preparation method thereof and OLED display panel |
| KR20190138764A (en) * | 2019-11-29 | 2019-12-16 | 삼성디스플레이 주식회사 | Method of manufacturing display substrate |
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| KR101261450B1 (en) * | 2006-02-06 | 2013-05-10 | 삼성디스플레이 주식회사 | Liquid crystal display and manufacturing method thereof |
| TWI423391B (en) * | 2010-07-08 | 2014-01-11 | Au Optronics Corp | Common line structure and display panel and method of making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109638062A (en) * | 2019-01-14 | 2019-04-16 | 京东方科技集团股份有限公司 | Array substrate row driving structure and production method, array substrate, display panel |
| CN110416274A (en) * | 2019-08-02 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of substrate and preparation method thereof and OLED display panel |
| KR20190138764A (en) * | 2019-11-29 | 2019-12-16 | 삼성디스플레이 주식회사 | Method of manufacturing display substrate |
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