TWI754323B - Device array substrate and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a device array substrate is provided and at least includes the following steps: forming a first patterned conductor layer, an insulating layer having a first through hole, and a second patterned conductor layer having a portion to be removed and a reserved portion connecting the first patterned conductor layer via the first through hole on a substrate; forming a patterned photoresist later covering the reserved portion and removing the portion to be removed of the second patterned conductor layer; removing the patterned photoresist later; forming a third patterned conductor layer having a source electrode, a drain electrode and a stacked portion, and the stacked portion being disposed on the reserved portion; forming a patterned cover layer; and forming a pixel electrode. A total thickness of the reserved portion and the stacked portion is greater than a thickness of the source electrode or the drain electrode. A device array substrate is also provided.

Description

Element array substrate and manufacturing method thereof

The present invention relates to an element array substrate and a manufacturing method thereof.

In the manufacturing process of the display device using the Polymer Sustained Alignment (PSA) technology, in order to reduce the resistance value of the wiring, a through-hole (VIA) light is usually performed after the process step of the semiconductor layer pattern. A capping process is used to form vias in the gate insulating layer. In this way, the second conductive layer (Metal 2) fabricated subsequently can be electrically connected to the first conductive layer (Metal 1) fabricated previously through the through hole, thereby reducing the resistance value of the wiring.

In addition, in order to avoid an excessively low yield, if the second conductive layer has too many disconnections or short circuits after being patterned, a rework step is usually performed on the second conductive layer.

However, when the rework step is performed, after removing the second conductive layer, the used etchant will continue to erode the first conductive layer downward along the through hole of the gate insulating layer, so that the through hole will be formed. The underlying first conductive layer is hollowed out, resulting in poor yield.

The present invention provides an element array substrate and a manufacturing method thereof, with good yield.

An embodiment of the present invention provides a method for fabricating an element array substrate, including: providing a substrate; forming a first patterned conductive layer on the substrate, where the first patterned conductive layer includes a gate; and forming an insulating layer on the substrate to cover A first patterned conductive layer; a semiconductor pattern is formed on the insulating layer, and the semiconductor pattern is located above the gate electrode; a first through hole is formed in the insulating layer to expose the first patterned conductive layer; a first patterned conductive layer is formed on the insulating layer Two patterned conductive layers, the second patterned conductive layer has a part to be removed and a reserved part, the reserved part is filled in the first through hole, and is electrically connected to the first patterned conductive layer; a patterned photoresist layer is formed Covering the reserved part, and removing the part to be removed of the second patterned conductive layer; removing the patterned photoresist layer; forming a third patterned conductive layer on the substrate, the third patterned conductive layer including a source electrode and a drain electrode , and a lamination part, wherein the lamination part is located on the reserved part; a patterned cover layer is formed on the substrate, and the patterned cover layer has a second through hole to expose the drain electrode; and a pixel electrode is formed on the substrate, The pixel electrode is electrically connected to the drain electrode through the second through hole; wherein, the total thickness of the reserved portion and the stacked portion is greater than the thickness of the source electrode or the drain electrode of the third patterned conductive layer.

In an embodiment of the present invention, the first patterned conductive layer further includes an auxiliary portion of the patch cord, the laminated portion includes a main portion of the patch cord, and the main portion is electrically connected to the auxiliary portion through the reserved portion.

In an embodiment of the present invention, the line width of the main portion of the patch cord is smaller than the line width of the auxiliary portion of the patch cord.

In an embodiment of the present invention, the first patterned conductive layer further includes a common electrode, the laminated portion includes a bridge element, and the bridge element is electrically connected to the common electrode through the reserved portion.

In an embodiment of the present invention, the line width of the bridge element is larger than the line width of the common electrode.

In an embodiment of the present invention, the first patterned conductive layer further includes: a gate line connected to the gate electrode, the laminated part includes a main part of the patch cord, and the main part is electrically connected to the gate line through the reserved part .

In an embodiment of the present invention, the gate lines extend in a first direction, and the transition lines extend in a second direction intersecting with the first direction.

In an embodiment of the present invention, the material of the third patterned conductive layer is the same as the material of the second patterned conductive layer.

In an embodiment of the present invention, the step of forming the patterned cover layer includes: forming a first protective layer, a color filter layer, and a second protective layer on a substrate; and for the first protective layer, the color filter layer, A patterning process is performed with the second protective layer.

An embodiment of the present invention provides an element array substrate, comprising: a substrate, a first patterned conductive layer on the substrate, an insulating layer, a semiconductor pattern, a second patterned conductive layer, a third patterned conductive layer, and a patterned cover layers, and pixel electrodes. The first patterned conductive layer includes a gate. The insulating layer covers the first patterned conductive layer, and the insulating layer has first through holes. The semiconductor pattern is located on the insulating layer and above the gate electrode. The second patterned conductive layer has a reserved portion, and the reserved portion is filled in the first through hole and electrically connected to the first patterned conductive layer. The third patterned conductive layer includes a source electrode, a drain electrode, and a stack portion, and the stack portion is located on the reserved portion. The patterned capping layer has a second through hole. The pixel electrode is electrically connected to the drain electrode through the second through hole. The total thickness of the reserved portion and the stacked portion is greater than the thickness of the source electrode or the drain electrode of the third patterned conductive layer.

In an embodiment of the present invention, the difference between the total thickness of the reserved portion and the stack portion and the thickness of the source or drain is between 200 Å and 10,000 Å.

In an embodiment of the present invention, the first patterned conductive layer further includes: an auxiliary part of the patch cord; the laminated part includes a main part of the patch cord; the main part is electrically connected to the auxiliary part through the reserved part.

In an embodiment of the present invention, the line width of the main portion of the patch cord is smaller than the line width of the auxiliary portion of the patch cord.

In an embodiment of the present invention, the third patterned conductive layer further includes: a data line connected to the source electrode.

In an embodiment of the present invention, the first patterned conductive layer further includes a common electrode; the laminated portion includes a bridge element; the bridge element is electrically connected to the common electrode through the reserved portion.

In an embodiment of the present invention, the line width of the bridge element is larger than the line width of the common electrode.

In an embodiment of the present invention, the first patterned conductive layer further includes: a gate line connected to the gate; the laminated portion includes a main portion of the patch cord; the main portion is electrically connected to the gate line through the reserved portion .

In an embodiment of the present invention, the gate lines extend in a first direction, and the transition lines extend in a second direction intersecting with the first direction.

In an embodiment of the present invention, the material of the third patterned conductive layer is the same as the material of the second patterned conductive layer.

Based on the above, the device array substrate and the manufacturing method thereof according to the embodiments of the present invention have at least the following technical effects: before the rework step is performed on the second conductive layer, at the through hole connecting the first conductive layer and the second conductive layer , pre-covered with a patterned photoresist layer to cover the via. In this way, the etching solution can be prevented from corroding the second conductive layer at the via hole, and the etching solution can be prevented from corroding the first conductive layer downward through the via hole. Therefore, the manufacturing method of the device array substrate according to the embodiment of the present invention has a high yield. In addition, in the element array substrate of the embodiment of the present invention, the patterned conductive layers of different film layers can be electrically connected by using through holes, so as to achieve the design of double-layer metal wiring, which helps to reduce the overall resistance of the wiring. Therefore, the device array substrate is easy to drive, and the layout area of the peripheral circuit region of the device array substrate is reduced, thereby achieving a narrow frame design.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

In the manufacturing method of the device array substrate according to the embodiment of the present invention, before the rework step is performed on the second conductive layer, the through hole connecting the first conductive layer and the second conductive layer is pre-covered with a patterned photoresist layer, so as to Cover the through hole. In this way, the etching solution can be prevented from corroding the second conductive layer at the via hole, and the etching solution can be prevented from corroding the first conductive layer downward through the via hole.

Hereinafter, with reference to FIGS. 1 to 6 , embodiments of the fabrication method of the device array substrate and the device array substrate of the present invention will be described.

FIG. 1 is a schematic top view of a device array substrate according to an embodiment of the present invention. Referring to FIG. 1 , the device array substrate 100 can be used in the display device 10 . Generally speaking, the display device 10 may include: an element array substrate 100 , an opposite substrate (not shown) opposite to the element array substrate 100 , and a display medium (not shown) disposed between the element array substrate 100 and the opposite substrate , for example: a liquid crystal layer, or an organic light-emitting element layer, etc.), and the driving element 200 for driving the element array substrate 100 .

FIG. 1 only shows the element array substrate 100 and the driving element 200 , and other components of the display device 10 are omitted to facilitate the description of the structure of the element array substrate 100 and the driving element 200 .

Referring to FIG. 1 , the device array substrate 100 may have a substrate 110 . On the element array substrate 100 , the transition line gl, the bridge element BL, and the gate line GL are arranged. Here, the arrangement of each wiring is only schematically shown. The detailed layout of the wiring can be determined according to the Depends on design needs.

On the device array substrate 100 , a plurality of pixels 112 may be disposed, that is, a plurality of first pixels 112A ( 112 ) and a plurality of second pixels 112B ( 112 ).

The driving device 200 may include a wafer, and the wafer may be bonded to the device array substrate 100 by a chip-on-film (COF) process. In other embodiments, the wafer can also be bonded to the device array substrate 100 by a die-to-glass bonding process (Chip On Glass, COG), a tape automated bonding (TAB) or other methods.

FIG. 2 is an enlarged schematic view of the first pixel 112A ( 112 ) of the device array substrate of FIG. 1 . On the periphery of the first pixel 112A ( 112 ), a data line DL, a gate line GL, a transition line gl, a common electrode cl and a common electrode pattern CL are also drawn.

3A to 3N are cross-sectional schematic diagrams of the steps of the method for fabricating the device array substrate shown along the section line A-A' of FIG. 2 . 2 and 3A to 3N are used to describe the fabrication method of the device array substrate 100 .

First, referring to FIG. 2 and FIG. 3A , a substrate 110 is provided. For example, the material of the substrate 110 may be glass. However, the material of the substrate 110 can also be quartz, organic polymers, or opaque/reflective materials (eg, wafers, ceramics, etc.), or other applicable materials.

Next, referring to FIG. 2 and FIG. 3A , a first patterned conductive layer 120 is formed on the substrate 110 . The first patterned conductive layer 120 may include: a gate electrode 121c. In addition, the first patterned conductive layer 120 may also include: a gate line GL connected to the gate electrode 121c, a common electrode c1 (ie, a common electrode pattern CL) arranged in parallel with the gate line GL, and a transition line g1 Auxiliary part glb.

Based on the consideration of conductivity, the material of the first patterned conductive layer 120 may include metals, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), Or neodymium (Nd), or an alloy of any combination of the above metals. The first patterned conductive layer 120 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

In addition, the method for forming the first patterned conductive layer 120 may include the following steps: first, a conductive layer (not shown) is formed on the substrate 110 by chemical vapor deposition or physical vapor deposition; then, A patterned photoresist (not shown) is formed on the conductive layer by a lithography process; then, a wet or dry etching process is performed on the conductive layer by using the patterned photoresist as a mask; after that, the patterned photoresist is removed photoresist to form the first patterned conductive layer 120 .

Next, referring to FIG. 2 and FIG. 3B , an insulating layer 130 is formed on the substrate 110 to cover the first patterned conductive layer 120 . The material of the insulating layer 130 may include inorganic materials, organic materials, or a combination thereof. Inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. The organic material is, for example (but not limited to): a polymer material such as polyimide-based resin, epoxy-based resin, or acrylic-based resin. In an embodiment of the present invention, the insulating layer 130 may be a single film layer. In other embodiments, the insulating layer 130 may also be formed by stacking a plurality of film layers. The formation method of the insulating layer 130 may include physical vapor deposition or chemical vapor deposition.

2 and 3C, a semiconductor pattern 121d is formed on the insulating layer 130, and the semiconductor pattern 121d is located above the gate electrode 121c. The method for forming the semiconductor pattern 121d may include the following steps: first, forming a semiconductor material layer (not shown) on the insulating layer 130; then, using a lithography process to form a patterned photoresist (not shown) on the semiconductor material layer shown); then, a wet or dry etching process is performed on the semiconductor material layer by using the patterned photoresist as a mask; after that, the patterned photoresist is removed to form a semiconductor pattern 121d.

Next, referring to FIGS. 2 and 3D , a first through hole 131 is formed in the insulating layer 130 to expose the first patterned conductive layer 120 . The first through hole 131 can be formed by using a lithography process and a dry etching process. For example, in the embodiment of FIG. 2 , the formation position of the first through hole 131 may be located at a position where the auxiliary portion glb of the patch wire gl is exposed.

Then, referring to FIG. 3E , a second patterned conductive layer 140 is formed on the insulating layer 130 . The second patterned conductive layer 140 has a portion to be removed (ie, the data line DL, the source electrode 121a, and the drain electrode 121b as shown in FIG. 3E ) and a reserved portion (ie, the transition line g1 as shown in FIG. 3E ) the main part of gla1). The reserved portion gla1 is filled in the first through hole 131 and is electrically connected to the first patterned conductive layer 140 (ie, the auxiliary portion glb of the patch wire gl as shown in FIG. 3E ).

3E, the second patterned conductive layer 140 may include: the main portion gla1 of the transition line gl, the data line DL, the source electrode 121a, and the drain electrode 121b, wherein the reserved portion of the second patterned conductive layer 140, That is, the main portion gla1 of the transition line gl filled in the first through hole 131, and the portion to be removed of the second patterned conductive layer 140 is the data line DL, the source electrode 121a, and the drain electrode 121b.

Based on the consideration of electrical conductivity, the material of the second patterned conductive layer 140 may use metals, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), Or neodymium (Nd), or an alloy of any combination of the above metals. In other embodiments, the second patterned conductive layer 140 may also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, a stacked layer of metal and other conductive materials, or other Materials with conductive properties. In addition, regarding the formation method of the second patterned conductive layer 140 , the same formation method as the above-mentioned first patterned conductive layer 120 can be used, which will not be repeated here.

Then, referring to FIG. 3F, a patterned photoresist layer 150 is formed to cover the reserved portion gla1. The method for forming the patterned photoresist layer 150 may include the following steps: first, forming a photoresist layer (not shown) on the substrate 110; then, removing most of the photoresist layer, leaving the remaining portion ( That is, the photoresist layer above the main portion gla1) of the wiring gl to form the patterned photoresist layer 150 .

Referring to FIG. 3G, then, the to-be-removed portion of the second patterned conductive layer 140 (ie, the data line DL, the source electrode 121a, and the drain electrode 121b) is removed. For example, the to-be-removed portion may be removed using an etchant. The data line DL, the source electrode 121a, and the drain electrode 121b are not covered by the patterned photoresist layer 150, but are eroded and removed by the etching solution. Also, it can be noted that the remaining portion gla1 covered by the patterned photoresist layer 150 is not removed in the step of FIG. 3G but remains.

Then, referring to FIG. 3H , the patterned photoresist layer 150 is removed, that is, the remaining portion gla1 at the through hole 131 is exposed.

2 and FIG. 3I, a third patterned conductive layer 160 is formed on the substrate 110. The third patterned conductive layer 160 may include: a source electrode 121a, a drain electrode 121b, and a stack portion (ie, a patch cord) The main portion gla2 of gl), wherein the lamination portion gla2 is located on the reserved portion gla1.

The third patterned conductive layer 160 may include: the main portion gla2 of the transfer line gl, the data line DL, the source electrode 121a, and the drain electrode 121b, wherein the stacked portion of the third patterned conductive layer 160 is the transfer line Wiring the main part of gl gl2. 3I, the main portion gla2 of the transition line gl of the third pattern layer 160 is disposed on the reserved portion gla1 of the second patterned conductive layer 140, and is electrically connected to the transition line gl via the reserved portion gla1 Auxiliary part glb.

Based on the above, the steps shown in FIGS. 3F to 3I are generally referred to as rework steps. As shown in FIG. 3F , since the patterned photoresist layer 150 is formed over the reserved portion gla1, the first patterned metal layer 120 located at the first through hole 131 (ie, the first patterned metal layer 120 located at the first through hole 131 (ie, the transition line gl) can be protected. The auxiliary portion glb) and the second patterned metal layer 140 (ie, the main portion gla1 of the transition line gl). As a result, as shown in FIG. 3G , for example, when an etching solution is used to remove the to-be-removed portion of the second patterned conductive layer 140 (ie, the data line DL, the source electrode 121 a , and the drain electrode 121 b ), the etching solution The underlying first patterned metal layer 120 (ie, the auxiliary portion glb of the transition line gl) will not be eroded through the first through hole 131 . As a result, the fabrication yield of the device array substrate 100 can be greatly improved.

The material of the third patterned conductive layer 160 and the material of the second patterned conductive layer 140 may be the same or different. That is to say, when the third patterned conductive layer 160 in FIG. 3I is fabricated, the same materials, mask and lithography etching process as those in the fabrication of the second patterned conductive layer 140 in FIG. 3E can be used. Of course, different materials, masks, and lithography etching processes can also be used for the second patterned conductive layer 140 in FIG. 3E .

In addition, the thickness of the third patterned conductive layer 160 and the thickness of the second patterned conductive layer 140 may be the same or different. The thickness of the third patterned conductive layer 160 may be greater than, less than, or equal to the thickness of the second patterned conductive layer 140 .

2 and 3I, the line width W1 of the main portion gla1 or the main portion gla2 of the patch cord gl is smaller than the line width W2 of the auxiliary portion glb of the patch cord gl, but the present invention is not limited thereto. In addition, as shown in FIG. 2 , it can be seen that the area of the auxiliary portion glb of the patch wire gl belonging to the first patterned conductive layer 120 is larger than that of the main portion gla of the patch wire gl belonging to the third patterned conductive layer 160 In addition, the area of the main part gla of the patch wire gl is larger than the area of the through hole 131 .

It can also be noted that the source electrode 121a, the drain electrode 121b, the gate electrode 121c, and the semiconductor pattern 121d constitute the active element 121 (ie, thin film transistor) of the first pixel 112A, and the insulating layer 130 is sandwiched between the gate electrode 121c and the semiconductor pattern 121d. between the semiconductor patterns 121d.

Next, referring to FIGS. 3J to 3M , a patterned capping layer 170 (as shown in FIG. 3M ) is formed on the substrate 110 , and the patterned capping layer 170 has a second through hole 174 to expose the drain electrode 121 b.

Referring to FIGS. 3J to 3L first, a protective layer 171 , a color filter layer 172 , and a planarization layer 173 are sequentially formed on the substrate 110 . The protective layer 171 is fabricated by, for example, plasma chemical vapor deposition or other suitable thin film deposition techniques, and uses a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The color filter layer 172 may include red filter patterns, green filter patterns, and blue filter patterns. The planarization layer 173 may use a light-transmitting organic material or an inorganic material.

3M again, a second through hole 174 is formed in the protective layer 171, the color filter layer 172, and the planarization layer 173 to expose the drain electrode 121b. That is, the patterned capping layer 170 may include a protective layer 171 , a color filter layer 172 , and a planarization layer 173 , and the second through holes 174 are formed in the patterned capping layer 170 .

Next, referring to FIG. 3N , a pixel electrode 122 is formed on the substrate 110 , and the pixel electrode 122 is electrically connected to the drain electrode 121 b of the third patterned conductive layer 160 through the second through hole 174 .

The pixel electrode 122 may be a transparent conductive layer. The material of the pixel electrode 122 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or at least the above Stacked layers of the two. After the above-mentioned steps in FIGS. 3A to 3N , the fabrication of the element array substrate 100 is completed.

Referring to FIG. 3N again, it can be noted that the main portion gla of the patch cord gl includes: the reserved portion (ie, the main portion gla1 of the patch cord gl) and the laminated portion (ie, the main portion of the patch cord gl) gla2). The total thickness of the reserved portion and the stacked portion (ie, the total thickness of the main portion gla1 and the main portion gla2 ) is greater than the thickness of the data line DL, or the source electrode 121 a, or the drain electrode 121 b of the third patterned conductive layer 160 .

For example, referring to FIG. 3N, the total thickness T1 of the main portion gla1 and the main portion gla2 (ie, the total thickness of the main portion gla), and the thickness T2 of the data line DL, or the thickness T3 of the drain electrode 121b, or the source electrode The difference in thickness T4 of 121a is between 200 Å and 10,000 Å, that is, 200Å≦T1-T2≦10,000Å 200Å≦T1-T3≦10,000Å 200Å≦T1-T4≦10,000Å.

Based on the above, in the embodiments of FIGS. 2 and 3A to 3N, since the patterned photoresist layer 150 is first formed above the reserved portion gla1 during the rework step, the first through hole can be protected. The first patterned metal layer 120 at 131 (ie, the auxiliary portion glb of the patch line gl) and the second patterned metal layer 140 (ie, the main portion gla1 of the patch line gl). In this way, when the etching solution is used to remove the to-be-removed portion of the second patterned conductive layer 140 (ie, the data line DL, the source electrode 121 a, and the drain electrode 121 b ), the etching solution will not pass along the first pass The hole 131 continues to erode the first patterned metal layer 120 (ie, the auxiliary portion glb of the patch line gl) downward. Therefore, the manufacturing yield of the device array substrate 100 can be improved.

Hereinafter, the structure of the device array substrate 100 according to an embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1 , FIG. 2 and FIG. 3N , the device array substrate 100 includes a plurality of data lines DL and a plurality of gate lines GL. A plurality of data lines DL and a plurality of gate lines GL are disposed on the substrate 110 . The plurality of data lines DL are arranged in the first direction x, and the plurality of gate lines GL are arranged in the second direction y, wherein the first direction x and the second direction y are staggered. For example, the first direction x and the second direction y may be perpendicular. In addition, the data line DL and the gate line GL belong to different layers. For example, the gate line GL can selectively belong to the first patterned conductive layer 120 , and the data line DL can selectively belong to the third patterned conductive layer 160 .

Referring to FIGS. 1 and 2 , the first pixel 112A ( 112 ) includes an active element 121 and a pixel electrode 122 . The active element 121 is electrically connected to a corresponding data line DL and a corresponding gate line GL, and the pixel electrode 122 is electrically connected to the active element 121 .

For example, the active element 121 may be a thin film transistor, the thin film transistor has a source electrode 121a, a drain electrode 121b, a gate electrode 121c and a semiconductor pattern 121d, and the source electrode 121a and the drain electrode 121b are respectively different from two regions of the semiconductor pattern 121d For electrical connection, the source electrode 121 a is electrically connected to a corresponding data line DL, the gate electrode 121 c is electrically connected to a corresponding one of the gate electrode lines GL, and the drain electrode 121 b is electrically connected to the pixel electrode 122 . 2 and 3N, the gate electrode 121c and the common electrode cl can selectively belong to the first patterned conductive layer 120, and the source electrode 121a and the drain electrode 121b can selectively belong to the third patterned conductive layer 160.

Referring to FIG. 1 , the device array substrate 100 further includes a plurality of transition wires gl. A plurality of patch cords gl are disposed on the substrate 110 and are arranged in the first direction x. Referring to FIG. 1 , FIG. 2 and FIG. 3N , the first patterned conductive layer 120 further includes an auxiliary portion glb of the patch wire gl. The laminated portion (ie, the main portion gla2 of the patch cord gl) includes the main portion gla of the patch cord gl. The main part gla (gla2) is electrically connected to the auxiliary part glb through the reserved part gla1.

That is to say, referring to FIG. 2 , each patch cord gl may include a main portion gla and an auxiliary portion glb, which are electrically connected to each other through the through hole 131; that is, the patch cord gl may include: belong to different layers respectively The main part gl and the auxiliary part glb are electrically connected to each other through the first through hole 131 by the patterned conductive layer. In this way, the patch cord gl can be designed with double-layer metal wiring, which helps to reduce the overall resistance value of the patch cord gl, and makes the device array substrate 100 easy to drive.

Referring to FIG. 2 , FIG. 3E and FIG. 3N , the main parts gla of the plurality of patch wires gl can selectively belong to the second patterned conductive layer 140 and the third patterned conductive layer 160 . The auxiliary portions glb of the plurality of patch wires gl may selectively belong to the first patterned conductive layer 120 .

2 and 3N, the device array substrate 100 may include: a substrate 110, a first patterned conductive layer 120, an insulating layer 130, a semiconductor pattern 121d, a second patterned conductive layer 140, a third patterned conductive layer 160, The patterned cover layer 170 and the pixel electrodes 122 are formed.

The first patterned conductive layer 120 is located on the substrate 110 and includes a gate electrode 121c. The first patterned conductive layer 120 may further include an auxiliary part glb of the patch wire.

The insulating layer 130 is located on the substrate 110 and covers the first patterned conductive layer 120 . The insulating layer 130 has a first through hole 131 . It can be seen from FIG. 2 and FIG. 3N that the first through hole 131 is located at the position of the auxiliary portion glb of the patch cord gl.

The semiconductor pattern 121d is located on the insulating layer 130 and above the gate electrode 121c.

The second patterned conductive layer 140 has a reserved portion gla1 , and the reserved portion gla1 is filled in the first through hole 131 to be electrically connected to the first patterned conductive layer 120 . As can be seen from FIG. 2 and FIG. 3N , the reserved portion gl1 of the second patterned conductive layer 140 is electrically connected to the auxiliary portion glb of the patch line gl of the first patterned conductive layer 120 .

The third patterned conductive layer 160 is located on the substrate 110. The third patterned conductive layer 160 includes a source electrode 121a, a drain electrode 121b, and a stacked portion gla2 located on the reserved portion gla1. As can be seen from FIG. 2 and FIG. 3N, the third patterned conductive layer 160 may further include: a data line DL connected to the source electrode 121a.

The patterned capping layer 170 has second through holes 174 . The patterned capping layer 170 may include a protective layer 171 , a color filter layer 172 , and a planarization layer 173 . As can be seen from FIGS. 3M and 3N , the second through holes 170 are formed in the protective layer 171 , the color filter layer 172 , and the planarization layer 173 . The pixel electrode 122 is electrically connected to the drain electrode 121b through the second through hole 174 .

Referring to FIG. 3N , it can be noted that the main portion gla of the patch cord gl includes a reserved portion (ie, the main portion gla1 ) and a laminated portion (ie, the main portion gla2 ). The total thickness T1 of the reserved portion and the stacked portion (ie, the total thickness of the main portion gla) is greater than the thickness T2 of the data line DL of the third patterned conductive layer 160 , or the thickness T3 of the drain electrode 121 b , or the source electrode Thickness T4 of 121a.

Referring to FIG. 3N , the difference between the total thickness T1 of the main portion gla and the thickness T2 of the data line DL may be between 200 Å and 10,000 Å. In another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T2 of the data line DL may be between 500 Å and 8,000 Å. In yet another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T2 of the data line DL may be between 1,000 Å and 6,000 Å.

Referring to FIG. 3N, the difference between the total thickness T1 of the main portion gla and the thickness T3 of the drain electrode 121b may be between 200 Å and 10,000 Å. In another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T3 of the drain electrode 121b may be between 500 Å and 8,000 Å. In yet another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T3 of the drain electrode 121b may be between 1,000 Å and 6,000 Å.

Referring to FIG. 3N, the difference between the total thickness T1 of the main portion gla and the thickness T4 of the source electrode 121a may be between 200 Å and 10,000 Å. In another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T4 of the source electrode 121a may be between 500 Å and 8,000 Å. In yet another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T4 of the source electrode 121a may be between 1,000 Å and 6,000 Å.

Based on the above, as shown in FIG. 3N , at the position of the through hole 131 , the reserved portion gla1 of the second patterned conductive layer 140 and the stacked portion gla2 of the third patterned conductive layer 160 are provided. The total thickness T1 of the reserved portion gla1 and the stacked portion gla2 is greater than the thickness T2 of the data line DL of the third patterned conductive layer 160 , the thickness T3 of the drain electrode 121 b , or the thickness T4 of the source electrode. In this way, the patterned conductive layers of different film layers can be electrically connected by using the through holes 131 to achieve the design of double-layer metal traces, which helps to reduce the overall resistance value of the traces, and makes the device array substrate 100 easy to use. drive.

FIG. 4 is an enlarged schematic view of the second pixel 112B ( 112 ) of the device array substrate of FIG. 1 . On the periphery of the second pixel 112B ( 112 ), a data line DL, a bridge element BL, a transition line gl, a gate line GL, a common electrode cl and a common electrode pattern CL are also drawn.

5A to 5K are cross-sectional schematic diagrams of the steps of the method for fabricating the device array substrate shown along the section line B-B' in FIG. 4 . Hereinafter, with reference to FIGS. 4 , 5A to 5K , a method for fabricating the device array substrate 100 will be described.

First, referring to FIG. 4 and FIG. 5A , a substrate 110 is provided. For example, the material of the substrate 110 may be glass. However, the material of the substrate 110 can also be quartz, organic polymers, or opaque/reflective materials (eg, wafers, ceramics, etc.), or other applicable materials.

Next, referring to FIG. 4 and FIG. 5A , a first patterned conductive layer 120 is formed on the substrate 110 . The first patterned conductive layer 120 may include: a common electrode cl. In addition, referring to FIG. 4 , the first patterned conductive layer 120 may also include: a gate line GL arranged in parallel with the common electrode cl (ie, the common electrode pattern CL), and a gate electrode 121c connected to the gate line GL . For the material and formation method of the first patterned conductive layer 120, reference may be made to the foregoing embodiments, which will not be repeated here.

Next, referring to FIG. 4 and FIG. 5B , an insulating layer 130 is formed on the substrate 110 to cover the first patterned conductive layer 120 . For the material and formation method of the insulating layer 130, reference may be made to the foregoing embodiments, which will not be repeated here.

Next, referring to FIG. 4 and FIG. 5C , a first through hole 131 is formed in the insulating layer 130 to expose the first patterned conductive layer 120 . In this embodiment, the formation position of the first through hole 131 may be located at a position where the common electrode cl is exposed.

Then, referring to FIG. 4 and FIG. 5D , a second patterned conductive layer 140 is formed on the insulating layer 130 . The second patterned conductive layer 140 has a portion to be removed (ie, the data line DL as shown in FIG. 5D ) and a reserved portion (ie, the bridge element BL1 as shown in FIG. 5D ). The reserved portion BL1 is filled in the first through hole 131 and is electrically connected to the first patterned conductive layer 120 (ie, the common electrode cl shown in FIG. 5D ).

4 and FIG. 5D , the second patterned conductive layer 140 may include: bridging elements BL1 and data lines DL, wherein the reserved portion of the second patterned conductive layer 140 is filled in the first through holes 131 The bridge element BL1 is bridged, and the portion to be removed of the second patterned conductive layer 140 is the data line DL. The material and forming method of the second patterned conductive layer 140 can be referred to the above-mentioned embodiments, which will not be repeated here.

Then, referring to FIGS. 5E to 5G , a patterned photoresist layer 150 is formed to cover the remaining portion BL1 , and the to-be-removed portion (ie, the data line DL) of the second patterned conductive layer 140 is removed.

5E, the method for forming the patterned photoresist layer 150 may include the following steps: first, forming a photoresist layer (not shown) on the substrate 110; then, removing most of the photoresist layer, leaving A photoresist layer over the reserved portion (ie, the bridging element BL1 ) to form a patterned photoresist layer 150 .

Referring to FIG. 5F , then, the second patterned conductive layer 140 (ie, the data line DL) not covered by the patterned photoresist layer 150 is removed.

Then, referring to FIG. 5G , the patterned photoresist layer 150 is removed.

Next, referring to FIGS. 4 and 5H , a third patterned conductive layer 160 is formed on the substrate 110 . The third patterned conductive layer 160 may include: a data line DL and a laminated portion (ie, a bridge element BL2 ), wherein, The lamination portion BL2 is located on the reserved portion BL1.

The third patterned conductive layer 160 may include a bridge element BL2 and a data line DL, wherein the stacked portion of the third patterned conductive layer 160 is the bridge element BL2. 5H, the bridge element BL2 is disposed on the reserved portion BL1 of the second patterned conductive layer 140, and is electrically connected to the common electrode cl through the reserved portion BL1.

The steps shown in FIGS. 5E to 5H are generally referred to as rework steps. As shown in FIG. 5E , since the patterned photoresist layer 150 is formed over the reserved portion BL1 , the first patterned metal layer (ie, the common electrode cl) located at the first through hole 131 and the first patterned metal layer (ie, the common electrode c1) and the Two patterned metal layers 140 (ie, bridge elements BL1). In this way, as shown in FIG. 5F , when an etching solution is used to remove the to-be-removed portion (ie, the data line DL) of the second patterned conductive layer 140 , the etching solution will not corrode through the first through holes 131 . The underlying first patterned metal layer (ie, the common electrode cl). As a result, the fabrication yield of the device array substrate 100 can be greatly improved.

Referring to FIG. 5H , the material of the third patterned conductive layer 160 and the material of the second patterned conductive layer 140 may be the same or different. During the fabrication of the third patterned conductive layer 160 in FIG. 5H , the same materials, mask and lithography etching process as those in the fabrication of the second patterned conductive layer 140 in FIG. 5D can be used. Of course, different materials, masks, and lithography etching processes can also be used for the second patterned conductive layer 140 in FIG. 5D .

In addition, the thickness of the third patterned conductive layer 160 and the thickness of the second patterned conductive layer 140 may be the same or different. The thickness of the third patterned conductive layer 160 may be greater than, less than, or equal to the thickness of the second patterned conductive layer 140 . In one embodiment, please refer to FIG. 4 and FIG. 5H , the line width W3 of the bridge element BL1 or the bridge element BL2 is greater than the line width W4 of the common electrode cl, but the invention is not limited thereto. 4 and 5H , it can be seen that the area of the common electrode cl belonging to the first patterned conductive layer 120 is smaller than the area of the bridge element BL2 belonging to the third patterned conductive layer 160 . In addition, the area of the bridge element BL is larger than the area of the through hole 131 .

Next, referring to FIGS. 5I to 5K , a protective layer 171 , a color filter layer 172 , and a planarization layer 173 are sequentially formed on the substrate 110 . For the materials and forming methods of the protective layer 171 , the color filter layer 172 , and the planarization layer 173 , reference may be made to the aforementioned embodiments, which will not be repeated here. In addition, a lithography process is performed on the protective layer 171 , the color filter layer 172 , and the planarization layer 173 , thereby forming a patterned protective layer 170 .

Referring to FIG. 5K , the bridge element BL includes: the reserved portion (ie, the bridge element BL1 ) and the stacked portion (ie, the bridge element BL2 ), and the total thickness of the reserved portion and the stacked portion (ie, the bridge element BL1 and the stacked portion) The total thickness of the bridge element BL2 ) is greater than the thickness of the data lines DL of the third patterned conductive layer 160 .

For example, referring to FIG. 5K , the difference between the total thickness T5 of the bridging element BL1 and the bridging element BL2 and the thickness T6 of the data line DL is between 200 Å and 10,000 Å, that is, 200Å≦T5-T6≦10,000Å.

Based on the above, in the embodiments of FIGS. 4 and 5A to 5K, since the patterned photoresist layer 150 is first formed above the reserved portion BL1 during the rework step, the first through hole can be protected. The first patterned metal layer at 131 (ie, the common electrode cl) and the second patterned metal layer 140 (ie, the bridge element BL1 ). In this way, when the etchant is used to remove the portion to be removed (ie, the data line DL) of the second patterned conductive layer 140 , the etchant will not continue to erode the first pattern down the first through hole 131 . The metallization layer 120 (ie, the common electrode cl). Therefore, the manufacturing yield of the device array substrate 100 can be improved.

Referring to FIG. 1 , FIG. 4 and FIG. 5K , the first patterned conductive layer 120 may include a common electrode cl. The laminated portion includes a bridge element BL2. The bridge element BL2 is electrically connected to the common electrode cl through the reserved portion BL1.

Referring to FIG. 4 , the common electrode cl and the pixel electrode 122 are partially overlapped to form a storage capacitor. For example, the plurality of second pixels 112B ( 112 ) can be arranged into a plurality of pixel rows, and the plurality of second pixels 112B ( 112 ) of each pixel row are arranged in the first direction x; the same pixel The common electrodes cl of the second pixels 112B ( 112 ) of the columns can be directly connected to form the common electrode pattern CL. The plurality of common electrode patterns CL of the plurality of pixel columns are arranged in the second direction y.

In the device array substrate 100 , the plurality of common electrode patterns CL of the plurality of pixel columns can be electrically connected to each other by the plurality of bridge elements BL arranged in the first direction x. 4 , in the top view of the device array substrate 100 , a plurality of common electrode patterns CL and a plurality of bridging elements BL having the same reference potential can be intertwined into a nearly mesh-like conductive pattern. However, the present invention is not limited to this. According to other embodiments, the common electrodes cl of the second pixels 112B ( 112 ) can also be electrically connected to each other by bridging elements in other arrangements.

For example, referring to FIG. 4 and FIG. 5K , the common electrode c1 may selectively belong to the first patterned conductive layer 120 . The plurality of bridging elements BL may selectively belong to the second patterned conductive layer 160 and the third patterned conductive layer 170 . The plurality of bridging elements BL can be electrically connected to the plurality of common electrodes cl through the plurality of first through holes 131 of the insulating layer 130, but the invention is not limited thereto. In addition, the bridging element BL can shield the gap between two adjacent pixel electrodes 122 . Therefore, the bridging element BL can also be called shielding metal, but the invention is not limited to this.

Referring to FIG. 5K , in this embodiment, the device array substrate 100 may include: a substrate 110 , a first patterned conductive layer 120 , an insulating layer 130 , a second patterned conductive layer 140 , a third patterned conductive layer 160 , and The capping layer 170 is patterned.

The first patterned conductive layer 120 includes the common electrode cl. The insulating layer 130 is located on the substrate 110 and covers the first patterned conductive layer 120 . The insulating layer 130 has a first through hole 131 . It can be seen from FIG. 4 and FIG. 5K that the first through hole 131 is located at the position of the common electrode cl.

The second patterned conductive layer 140 has a reserved portion (ie, the bridging element BL1 ). The reserved portion BL1 is filled in the first through hole 131 and is electrically connected to the common electrode cl of the first patterned conductive layer 120 .

The third patterned conductive layer 160 is located on the substrate 110 , and the third patterned conductive layer 160 includes the data line DL and the stacked portion (ie, the bridge element BL2 ). The lamination portion BL2 is located on the reserved portion BL1. The patterned capping layer 170 may include a protective layer 171 , a color filter layer 172 , and a planarization layer 173 .

5K , it can be noticed that the total thickness T5 of the reserved portion BL1 and the stacked portion BL2 (ie, the total thickness of the bridge element BL) is greater than the thickness T6 of the data line DL of the third patterned conductive layer 160 .

Referring to FIG. 5K , the difference between the total thickness T5 of the bridge element BL and the thickness T6 of the data line DL is between 200 Å and 10,000 Å. In another embodiment, the difference between the total thickness T5 of the bridge element BL and the thickness T6 of the data line DL may be between 500 Å and 8,000 Å. In yet another embodiment, the difference between the total thickness T5 of the bridge element BL and the thickness T6 of the data line DL may be between 1,000 Å and 6,000 Å.

4 and 5K, the common electrode cl (common electrode pattern CL) extends in the first direction x, and the bridge element BL1 (including the reserved portion BL1 and the stacked portion BL2) is in the second direction intersecting with the first direction x. Extending in the direction y, the bridge element BL can be connected to the common electrode cl through the first through hole 131 .

Based on the above, at the position of the through hole 131 , the reserved portion gla1 of the second patterned conductive layer 140 and the stacked portion gla2 of the third patterned conductive layer 160 are provided. The total thickness T1 of the reserved portion gla1 and the stacked portion gla2 is greater than the thickness T2 of the data line DL of the third patterned conductive layer 160 , the thickness T3 of the drain electrode 121 b , or the thickness T4 of the source electrode. In this way, the patterned conductive layers of different film layers can be electrically connected by using the through holes 131 to achieve the design of double-layer metal traces, which helps to reduce the overall resistance value of the traces, and makes the device array substrate 100 easy to use. drive.

FIG. 6 is a schematic cross-sectional view of the device array substrate taken along the section line C-C' of FIG. 4 . 4 and 6, it can be seen that: the substrate 110, the first patterned conductive layer 120, the insulating layer 130, the second patterned conductive layer 140, the third patterned conductive layer 160, and the patterned cover layer 170, etc. structure.

The first patterned conductive layer 120 includes a gate line GL connected to the gate electrode 121c. The insulating layer 130 covers the first patterned conductive layer 120 . The insulating layer 130 has a first through hole 131 . It can be noted that, in this embodiment, the first through hole 131 is formed at a position where the gate line GL is exposed.

The second patterned conductive layer 140 has a reserved portion (ie, the main portion gla1 of the transition line gl), the reserved portion gla1 is filled in the first through hole 131 and electrically connected to the gate line GL of the first patterned conductive layer 120 sexual connection. The third patterned conductive layer 160 includes a data line DL and a stacked portion (ie, the main portion gla2 of the transition line gl), and the stacked portion gla2 is located on the reserved portion gla1. The main portion gla2 is electrically connected to the gate line GL through the reserved portion gla1. The patterned capping layer 170 may include a protective layer 171 , a color filter layer 172 , and a planarization layer 173 .

In this embodiment, the main portion gla of the patch cord gl includes the reserved portion (ie, the main portion gla1 of the patch cord gl) and the laminated portion (that is, the main portion gla2 of the patch cord gl). The total thickness of the reserved portion and the stacked portion (ie, the total thickness of the main portion gla1 and the main portion gla2 ) is greater than the thickness of the data line DL of the third patterned conductive layer 160 .

Referring to FIG. 6 , the total thickness T7 of the main portion gla1 and the main portion gla2 is greater than the thickness T8 of the data line DL of the third patterned conductive layer 160 . For example, the difference between the total thickness T7 of the main portion gla1 and the main portion gla2 (ie, the total thickness of the main portion gla) and the thickness T8 of the data line DL is between 200 Å and 10,000 Å, that is, 200Å≦T7-T8≦10,000Å.

In another embodiment, the difference between the total thickness T7 of the main portion gla1 and the main portion gla2 and the thickness T8 of the data line DL may be between 500 Å and 8,000 Å. In yet another embodiment, the difference between the total thickness T7 of the main portion gla1 and the main portion gla2 and the thickness T8 of the data line DL may be between 1,000 Å and 6,000 Å.

Please refer to FIG. 4 and FIG. 6 at the same time, the gate line GL extends in the first direction x, and the main portion gla (including the reserved portion gla1 and the laminated portion gla2) of the transition line gl is in the first direction x intersecting the first direction x. Extend in two directions y. The main portion gla of the transition line gl can be connected to the gate line GL through the first through hole 131 . In other words, the gate line GL can be connected to the main portion gla of the transition line gl through the first through hole 131 and extend from the first direction x to the second direction y. In this way, the driving element 200 (as shown in FIG. 1 ) can be arranged only on one side of the element array substrate 100 , and the gate line GL can be used to scan in the first direction x and the second direction y, which is helpful for The layout area of the peripheral circuit region of the device array substrate 100 is reduced, thereby achieving a narrow frame design.

In the above-mentioned device array substrate 100, several embodiments of connecting two conductive layers through the first through holes 131 are described, that is, as shown in FIG. The main part gla of the wiring gl and the auxiliary part glb of the patch wiring gl; as shown in FIG. 5K , the bridge element BL and the common electrode cl connected through the first through hole 131 are described; and, as shown in FIG. 6 , The main portion gla of the transition line gl and the gate line GL connected through the first through hole 131 are described, but the present invention is not limited thereto. The above-mentioned embodiments of connecting two conductive layers through the first through holes 131 can be applied to the same element array substrate or different element array substrates, depending on design requirements.

To sum up, the method for fabricating the device array substrate and the device array substrate of the present invention have at least the following technical effects: The hole is pre-covered with a patterned photoresist layer, so that the etching solution can prevent the etching solution from eroding the second conductive layer at the through hole, thereby preventing the etching solution from eroding the first conductive layer downward. Thereby, the manufacturing yield of the element array substrate can be improved. In addition, in the element array substrate of the embodiment of the present invention, the conductive layers of different film layers can be electrically connected by using through holes, so as to achieve the design of double-layer metal wiring, which is helpful to: reduce the overall resistance value of the wiring, The element array substrate is easy to drive, and the layout area of the peripheral circuit region of the element array substrate can be reduced, thereby achieving the design of a narrow frame.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Display device 100: Element array substrate 110: Substrate 112: Pixel 112A: First pixel 112B: Second pixel 121: Active Components 121a: source 121b: Drain 121c: Gate 121d: Semiconductor pattern 122: pixel electrode 130: Insulation layer 131: first through hole 140: the second patterned conductive layer 150: Patterned photoresist layer 160: the third patterned conductive layer 170: Patterned Overlay 171: Protective Layer 172: Color filter layer 173: planarization layer 174: second through hole 200: Drive element A-A', B-B', C-C': hatching BL, BL1, BL2: Bridge elements CL: Common electrode pattern cl: common electrode DL: data line GL: gate line gl: transfer cable gla, gla1, gla2: main department glb: auxiliary department T1～T8: Thickness W1, W2, W3, W4: Line width x: first direction y: the second direction

FIG. 1 is a schematic top view of a device array substrate according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of a first pixel of the device array substrate of FIG. 1 . 3A to 3N are cross-sectional schematic diagrams of the steps of the method for fabricating the device array substrate shown along the section line A-A' of FIG. 2 . FIG. 4 is an enlarged schematic view of a second pixel of the device array substrate of FIG. 1 . 5A to 5K are cross-sectional schematic diagrams of the steps of the method for fabricating the device array substrate shown along the section line B-B' in FIG. 4 . FIG. 6 is a schematic cross-sectional view of the device array substrate taken along the section line C-C' of FIG. 4 .

100: Element array substrate

110: Substrate

120: the first patterned conductive layer

121a: source

121b: Drain

121c: Gate

121d: Semiconductor pattern

122: pixel electrode

130: Insulation layer

131: first through hole

140: the second patterned conductive layer

160: the third patterned conductive layer

170: Patterned Overlay

171: Protective Layer

172: Color filter layer

173: planarization layer

A-A’: hatch line

DL: data line

gla, gla1, gla2: main department

glb: auxiliary department

T1~T4: Thickness

Claims (13)

A manufacturing method of an element array substrate, comprising: providing a substrate; forming a first patterned conductive layer on the substrate, the first patterned conductive layer including a gate; forming an insulating layer on the substrate to cover the first patterned conductive layer; a semiconductor pattern is formed on the insulating layer, and the semiconductor pattern is located above the gate; a first through hole is formed in the insulating layer to expose the first patterned conductive layer layer; a second patterned conductive layer is formed on the insulating layer, the second patterned conductive layer has a part to be removed and a reserved part, the reserved part is filled in the first through hole, and is connected with the first through hole. A patterned conductive layer is electrically connected; a patterned photoresist layer is formed to cover the reserved portion, and the to-be-removed portion of the second patterned conductive layer is removed; the patterned photoresist layer is removed; A third patterned conductive layer is formed thereon, the third patterned conductive layer includes a source electrode, a drain electrode and a stacked layer portion, wherein the stacked layer portion is located on the reserved portion; a pattern is formed on the substrate a patterned cover layer, the patterned cover layer has a second through hole to expose the drain electrode; and a pixel electrode is formed on the substrate, the pixel electrode is electrically connected to the drain electrode through the second through hole sexual connection; Wherein, the total thickness of the reserved portion and the stacked portion is greater than the thickness of the source electrode or the drain electrode of the third patterned conductive layer, and the first patterned conductive layer further includes an auxiliary portion of a patch cord , the stacked portion includes a main portion of the patch cord, the main portion is electrically connected to the auxiliary portion through the reserved portion, the first patterned conductive layer also includes a common electrode, and the stacked portion includes a bridge The bridging element is electrically connected to the common electrode through the reserved portion, the first patterned conductive layer also includes a gate line connected to the gate, and the main portion is electrically connected to the gate line through the reserved portion sexual connection. The method for manufacturing an element array substrate according to claim 1, wherein the line width of the main portion of the patch cord is smaller than the line width of the auxiliary portion of the patch cord. The method for fabricating an element array substrate according to claim 1, wherein the line width of the bridge element is larger than the line width of the common electrode. The method for fabricating an element array substrate according to claim 1, wherein the gate line extends in a first direction, and the transition line extends in a second direction intersecting with the first direction. The method for manufacturing an element array substrate according to claim 1, wherein the material of the third patterned conductive layer is the same as the material of the second patterned conductive layer. The method for manufacturing an element array substrate according to claim 1, wherein the step of forming the patterned cover layer comprises: A first protective layer, a color filter layer and a second protective layer are formed on the substrate; and a patterning process is performed on the first protective layer, the color filter layer and the second protective layer. An element array substrate, comprising: a substrate; a first patterned conductive layer on the substrate, the first patterned conductive layer comprising a gate; an insulating layer on the substrate, the insulating layer covering the first a patterned conductive layer, the insulating layer has a first through hole; a semiconductor pattern is located on the insulating layer, the semiconductor pattern is located above the gate; a second patterned conductive layer has a reserved portion, the The reserved part is filled in the first through hole and is electrically connected to the first patterned conductive layer; a third patterned conductive layer is located on the substrate, and the third patterned conductive layer includes a source electrode, a a drain electrode, and a stacking part, the stacking part is located on the reserved part; a patterned cover layer has a second through hole; and a pixel electrode, which is electrically connected to the drain electrode through the second through hole connection; wherein, the total thickness of the reserved portion and the stack portion is greater than the thickness of the source electrode or the drain electrode of the third patterned conductive layer, and the first patterned conductive layer also includes a transition wire. an auxiliary part, the laminated part includes a main part of the patch cord, the main part communicates with the auxiliary part through the reserved part The first patterned conductive layer further includes a common electrode, the laminated portion includes a bridge element, the bridge element is electrically connected to the common electrode through the reserved portion, and the first patterned conductive layer also Including a gate line connected with the gate, the main part is electrically connected with the gate line through the reserved part. The element array substrate of claim 7, wherein the difference between the total thickness of the reserved portion and the stacked portion and the thickness of the source electrode or the drain electrode is between 200 Å and 10,000 Å. The device array substrate of claim 7, wherein the line width of the main portion of the patch cord is smaller than the line width of the auxiliary portion of the patch cord. The device array substrate of claim 7, wherein the third patterned conductive layer further comprises: a data line connected to the source electrode. The element array substrate according to claim 7, wherein the line width of the bridge element is larger than the line width of the common electrode. The device array substrate of claim 7, wherein the gate line extends in a first direction, and the transition line extends in a second direction intersecting with the first direction. The device array substrate according to claim 7, wherein the material of the third patterned conductive layer is the same as the material of the second patterned conductive layer.

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