CN112909018B - Element array substrate and manufacturing method thereof - Google Patents
Element array substrate and manufacturing method thereof Download PDFInfo
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- CN112909018B CN112909018B CN202011330565.8A CN202011330565A CN112909018B CN 112909018 B CN112909018 B CN 112909018B CN 202011330565 A CN202011330565 A CN 202011330565A CN 112909018 B CN112909018 B CN 112909018B
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- 238000000034 method Methods 0.000 claims description 44
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
A manufacturing method of an element array substrate at least comprises the following steps. Forming a first patterned conductive layer, an insulating layer with a first through hole and a second patterned conductive layer with a portion to be removed and a reserved portion on the substrate, wherein the reserved portion is filled in the first through hole and is electrically connected with the first patterned conductive layer; forming a patterned photoresist layer covering the reserved part, and removing the part to be removed of the second patterned conductive layer; removing the patterned photoresist layer; forming a third patterned conductive layer having a source electrode, a drain electrode, and a stacked portion, the stacked portion being located on the remaining portion; forming a patterned cover layer; and forming a pixel electrode. The total thickness of the remaining portion and the stacked portion is greater than the thickness of the source or drain. In addition, an element array substrate is also provided.
Description
Technical Field
The invention relates to an element array substrate and a manufacturing method thereof.
Background
In the process of manufacturing a display device using the polymer stabilized alignment (Polymer Sustained Alignment, PSA) technology, a VIA (VIA) mask process is usually performed after the semiconductor layer patterning process to form a VIA on the gate insulating layer in order to reduce the resistance of the trace. Therefore, the second conductive layer (Metal 2) manufactured later is electrically connected with the first conductive layer (Metal 1) manufactured earlier through the through hole, and the resistance value of the wiring is reduced.
In order to avoid the low yield, if the second conductive layer is too much broken or shorted after patterning, a reworking step (rework step) is usually performed on the second conductive layer.
However, when the reworking step is performed, the etching solution used further erodes the first conductive layer downward along the through hole of the gate insulating layer after removing the second conductive layer, so that the first conductive layer below the through hole is hollowed out, resulting in poor yield.
Disclosure of Invention
The invention provides a device array substrate and a manufacturing method thereof, and the yield is good.
An embodiment of the present invention provides a method for manufacturing an element array substrate, including: providing a substrate; forming a first patterned conductive layer on a substrate, the first patterned conductive layer including a gate electrode; forming an insulating layer on the substrate to cover the first patterned conductive layer; forming a semiconductor pattern on the insulating layer, wherein the semiconductor pattern is positioned above the grid electrode; forming a first through hole in the insulating layer to expose the first patterned conductive layer; forming a second patterned conductive layer on the insulating layer, wherein the second patterned conductive layer is provided with a part to be removed and a reserved part, and the reserved part is filled in the first through hole and is electrically connected with the first patterned conductive layer; forming a patterned photoresist layer to cover the reserved part, and removing the part to be removed of the second patterned conductive layer; removing the patterned photoresist layer; forming a third patterned conductive layer on the substrate, the third patterned conductive layer including a source electrode, a drain electrode, and a stacked portion, wherein the stacked portion is located on the remaining portion; forming a patterned covering layer on the substrate, wherein the patterned covering layer is provided with a second through hole so as to expose the drain electrode; forming a pixel electrode on the substrate, wherein the pixel electrode is electrically connected with the drain electrode through the second through hole; wherein the total thickness of the remaining portion and the stacked portion is greater than the thickness of the source or drain of the third patterned conductive layer.
In an embodiment of the invention, the first patterned conductive layer further includes an auxiliary portion of the patch cord, and the stacked portion includes a main portion of the patch cord, and the main portion is electrically connected to the auxiliary portion through the remaining portion.
In an embodiment of the present invention, a line width of the main portion of the patch cord is smaller than a line width of the auxiliary portion of the patch cord.
In an embodiment of the invention, the first patterned conductive layer further includes a common electrode, and the stacked portion includes a bridge element electrically connected to the common electrode through the remaining portion.
In an embodiment of the invention, a line width of the bridge element is greater than a line width of the common electrode.
In an embodiment of the present invention, the first patterned conductive layer further includes: and the laminated part comprises a main part of the patch cord, and the main part is electrically connected with the gate line through the reserved part.
In one embodiment of the present invention, the gate line extends in a first direction, and the patch cord extends in a second direction intersecting the first direction.
In an embodiment of the invention, a material of the third patterned conductive layer is the same as a material of the second patterned conductive layer.
In one embodiment of the present invention, the step of forming the patterned capping layer includes: forming a first protective layer, a color filter layer and a second protective layer on the substrate; and patterning the first protective layer, the color filter layer and the second protective layer.
An embodiment of the present invention provides an element array substrate, including: the liquid crystal display device comprises a substrate, a first patterned conductive layer, an insulating layer, a semiconductor pattern, a second patterned conductive layer, a third patterned conductive layer, a patterned covering layer and a pixel electrode, wherein the first patterned conductive layer, the insulating layer, the semiconductor pattern, the second patterned conductive layer, the third patterned conductive layer, the patterned covering layer and the pixel electrode are arranged on the substrate. The first patterned conductive layer includes a gate. The insulating layer covers the first patterned conductive layer, and the insulating layer is provided with a first through hole. The semiconductor pattern is located on the insulating layer and above the gate electrode. The second patterned conductive layer is provided with a reserved part, and the reserved part is filled in the first through hole and is electrically connected with the first patterned conductive layer. The third patterned conductive layer includes a source electrode, a drain electrode, and a stacked portion, the stacked portion being located on the remaining portion. The patterned covering layer is provided with a second through hole. The pixel electrode is electrically connected with the drain electrode through the second through hole. The total thickness of the remaining portion and the stacked portion is greater than the thickness of the source or drain of the third patterned conductive layer.
In one embodiment of the present invention, the difference between the total thickness of the remaining portion and the stacked portion and the thickness of the source or drain is betweenTo->Between them.
In an embodiment of the present invention, the first patterned conductive layer further includes: an auxiliary part of the patch cord; the laminated part comprises a main part of the patch cord; the main part is electrically connected with the auxiliary part through the retaining part.
In an embodiment of the present invention, a line width of the main portion of the patch cord is smaller than a line width of the auxiliary portion of the patch cord.
In an embodiment of the present invention, the third patterned conductive layer further includes: and a data line connected to the source electrode.
In an embodiment of the invention, the first patterned conductive layer further includes a common electrode; the laminate section includes a bridging element; the bridging element is electrically connected with the common electrode through the reserved part.
In an embodiment of the invention, a line width of the bridge element is greater than a line width of the common electrode.
In an embodiment of the present invention, the first patterned conductive layer further includes: a gate line connected to the gate electrode; the laminated part comprises a main part of the patch cord; the main portion is electrically connected with the gate line through the reserved portion.
In one embodiment of the present invention, the gate line extends in a first direction, and the patch cord extends in a second direction intersecting the first direction.
In an embodiment of the invention, a material of the third patterned conductive layer is the same as a material of the second patterned conductive layer.
Based on the above, the element array substrate and the manufacturing method thereof according to the embodiments of the present invention have at least the following technical effects: before the reworking step is carried out on the second conductive layer, a patterned photoresist layer is covered in advance at the through hole connecting the first conductive layer and the second conductive layer so as to cover the through hole. In this way, the etching liquid can be prevented from corroding the second conductive layer at the through hole, and the etching liquid can be prevented from corroding the first conductive layer downward via the through hole. Therefore, the manufacturing method of the element array substrate has higher yield. In addition, the element array substrate of the embodiment of the invention can electrically connect the patterned conductive layers of different film layers by using the through holes, thereby realizing the design of double-layer metal wiring and being beneficial to: the overall resistance of the wiring is reduced, so that the element array substrate is easy to drive, and the layout area of the peripheral circuit area of the element array substrate is reduced, thereby achieving the design of a narrow frame.
The invention will now be described in more detail with reference to the drawings and specific examples, which are not intended to limit the invention thereto.
Drawings
Fig. 1 is a schematic top view of an element array substrate according to an embodiment of the invention.
Fig. 2 is an enlarged schematic view of a first pixel of the element array substrate of fig. 1.
Fig. 3A to 3N are schematic cross-sectional views illustrating a flow of steps of a method for manufacturing a device array substrate along a cross-sectional line A-A' in fig. 2.
Fig. 4 is an enlarged schematic view of a second pixel of the element array substrate of fig. 1.
Fig. 5A to 5K are schematic cross-sectional views illustrating a step flow of a method for manufacturing the device array substrate along the cross-sectional line B-B' of fig. 4.
Fig. 6 is a schematic cross-sectional view of the device array substrate along the cross-sectional line C-C' of fig. 4.
Wherein, the reference numerals:
10: display device
100: element array substrate
110: substrate board
112: pixel arrangement
112A: first pixel
112B: second pixel
121: active element
121a: source electrode
121b: drain electrode
121c: grid electrode
121d: semiconductor pattern
122: pixel electrode
130: insulating layer
131: first through hole
140: second patterned conductive layer
150: patterning photoresist layer
160: third patterned conductive layer
170: patterning a cover layer
171: protective layer
172: color filter layer
173: planarization layer
174: second through hole
200: driving element
A-A ', B-B ', C-C ': section line
BL, BL1, BL2: bridging element
CL: common electrode pattern
cl: common electrode
DL: data line
GL: gate line
gl: patch cord
gla, gla1, gla2: main part
glb: auxiliary part
T1 to T8: thickness of (L)
W1, W2, W3, W4: line width
x: first direction
y: second direction
Detailed Description
The structural and operational principles of the present invention are described in detail below with reference to the accompanying drawings:
in the method for manufacturing the element array substrate of the embodiment of the invention, before the second conductive layer is reworked, the through hole connecting the first conductive layer and the second conductive layer is covered with the patterned photoresist layer in advance so as to cover the through hole. In this way, the etching liquid can be prevented from corroding the second conductive layer at the through hole, and the etching liquid can be prevented from corroding the first conductive layer downward via the through hole.
Hereinafter, a method for manufacturing an element array substrate and an embodiment of the element array substrate according to the present invention will be described with reference to fig. 1 to 6.
Fig. 1 is a schematic top view of an element array substrate according to an embodiment of the invention. Referring to fig. 1, the device array substrate 100 may be suitable for use in the display device 10. In general, the display device 10 may include: the display device includes an element array substrate 100, an opposite substrate (not shown) opposite to the element array substrate 100, a display medium (not shown, for example, a liquid crystal layer, an organic light emitting element layer, or the like) disposed between the element array substrate 100 and the opposite substrate, and a driving element 200 for driving the element array substrate 100.
Fig. 1 only shows the element array substrate 100 and the driving element 200, and other components of the display device 10 are omitted to facilitate explanation of the structures of the element array substrate 100 and the driving element 200.
Referring to fig. 1, a device array substrate 100 may have a substrate 110. The patch cord GL, the bridge element BL and the gate line GL are provided on the element array substrate 100, and the arrangement of each trace is only schematically shown, and the detailed layout of the traces may be determined according to design requirements.
On the device array substrate 100, a plurality of pixels 112, that is, a plurality of first pixels 112A (112) and a plurality of second pixels 112B (112), may be disposed.
The driving element 200 may include: a Chip, which can be bonded to the device array substrate 100 through a Chip On Film (COF) process. In other embodiments, the Chip may also be bonded to the device array substrate 100 by a die-to-Glass bonding process (COG), die-On-Chip bonding (Tape Automated Bonding, TAB), or other means.
Fig. 2 is an enlarged schematic diagram of a first pixel 112A (112) of the element array substrate of fig. 1. The data line DL, the gate line GL, the transfer line GL, the common electrode CL, and the common electrode pattern CL are also drawn around the first pixel 112A (112).
Fig. 3A to 3N are schematic cross-sectional views illustrating a flow of steps of a method for manufacturing a device array substrate along a cross-sectional line A-A' in fig. 2. Hereinafter, a method of manufacturing the element array substrate 100 will be described with reference to fig. 2 and 3A to 3N.
First, referring to fig. 2 and 3A, a substrate 110 is provided. For example, the material of the substrate 110 may be glass. However, the material of the substrate 110 may be quartz, an organic polymer, or an opaque/reflective material (e.g., wafer, ceramic, etc.), or other suitable materials.
Next, referring to fig. 2 and fig. 3A, a first patterned conductive layer 120 is formed on the substrate 110. The first patterned conductive layer 120 may include: and a gate electrode 121c. In addition, the first patterned conductive layer 120 may also include: a gate line GL connected to the gate electrode 121c, a common electrode CL (i.e., a common electrode pattern CL) provided in parallel with the gate line GL, and an auxiliary portion glb of the patch cord GL.
Based on conductivity considerations, the material of the first patterned conductive layer 120 may include a metal, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), or neodymium (Nd), or an alloy of any combination of the foregoing metals. Other conductive materials may also be used for the first patterned conductive layer 120, such as: metal nitrides, metal oxides, metal oxynitrides, stacked layers of metal and other conductive materials, or other materials having conductive properties.
In addition, regarding the forming method of the first patterned conductive layer 120, the method may include the following steps: first, a conductive layer (not shown) is formed on a substrate 110 using a chemical vapor deposition method or a physical vapor deposition method; then, a patterning photoresist (not shown) is formed on the conductive layer by using a photolithography process; then, using the patterned photoresist as a mask to perform wet or dry etching process on the conductive layer; then, the patterned photoresist is removed to form the first patterned conductive layer 120.
Next, referring to fig. 2 and fig. 3B, an insulating layer 130 is formed on the substrate 110 to cover the first patterned conductive layer 120. The material of the insulating layer 130 may include an inorganic material, an organic material, or a combination thereof. Inorganic materials are for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the foregoing materials. The organic material is for example (but not limited to): polyimide resin, epoxy resin, acryl resin, and other polymer materials. In an embodiment of the present invention, the insulating layer 130 may be a single film layer. In other embodiments, the insulating layer 130 may be formed by stacking a plurality of film layers. The forming method of the insulating layer 130 may include a physical vapor deposition method or a chemical vapor deposition method.
Next, referring to fig. 2 and 3C, a semiconductor pattern 121d is formed on the insulating layer 130, and the semiconductor pattern 121d is located above the gate electrode 121C. Regarding the forming method of the semiconductor pattern 121d, the method may include the steps of: first, a semiconductor material layer (not shown) is formed on the insulating layer 130; then, a patterning photoresist (not shown) is formed on the semiconductor material layer by using a photolithography process; then, using the patterned photoresist as a mask to perform wet or dry etching process on the semiconductor material layer; thereafter, the patterned photoresist is removed to form the semiconductor pattern 121d.
Next, referring to fig. 2 and fig. 3D, a first via 131 is formed in the insulating layer 130 to expose the first patterned conductive layer 120. The first via 131 may be formed by a photolithography process in combination with a dry etching process. For example, in the embodiment of fig. 2, the first through hole 131 may be formed at a position exposing the auxiliary portion glb of the patch cord gl.
Then, referring to fig. 3E, a second patterned conductive layer 140 is formed on the insulating layer 130. The second patterned conductive layer 140 has: the portion to be removed (i.e., the data line DL, the source electrode 121a, the drain electrode 121b as shown in fig. 3E) and the remaining portion (i.e., the main portion gla1 of the patch cord gl as shown in fig. 3E). The remaining portion gla1 fills in the first via 131 and is electrically connected to the first patterned conductive layer 140 (i.e., the auxiliary portion glb of the patch cord gl shown in fig. 3E).
Referring to fig. 3E, the second patterned conductive layer 140 may include: the main portion gla1 of the patch cord gl, the data line DL, the source electrode 121a, and the drain electrode 121b, wherein the remaining portion of the second patterned conductive layer 140 is the main portion gla1 of the patch cord gl filled in the first through hole 131, and the portion of the second patterned conductive layer 140 to be removed is the data line DL, the source electrode 121a, and the drain electrode 121b.
The material of the second patterned conductive layer 140 may use a metal, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), or neodymium (Nd), or an alloy of any combination of the above metals, based on the consideration of conductivity. In other embodiments, the second patterned conductive layer 140 may use other conductive materials, such as: metal nitrides, metal oxides, metal oxynitrides, stacked layers of metal and other conductive materials, or other materials having conductive properties. The second patterned conductive layer 140 may be formed by the same method as that for the first patterned conductive layer 120, which will not be described again here.
Then, referring to fig. 3F, a patterned photoresist layer 150 is formed to cover the remaining portion gla1. The method for forming the patterned photoresist layer 150 may include the following steps: first, a photoresist layer (not shown) is formed on a substrate 110; then, most of the photoresist layer is removed, and the photoresist layer above the remaining portion (i.e., the main portion gla1 of the patch cord gl) is remained to form the patterned photoresist layer 150.
Referring to fig. 3G, the portions to be removed (i.e., the data line DL, the source electrode 121a, and the drain electrode 121 b) of the second patterned conductive layer 140 are removed. For example, an etching solution may be used to remove the portion to be removed. The data line DL, the source electrode 121a, and the drain electrode 121b are not covered by the patterned photoresist layer 150 and are etched and removed by the etching solution. Also, it is noted that the remaining portion gla1 covered by the patterned photoresist layer 150 is not removed but remains in the step of fig. 3G.
Then, referring to fig. 3H, the patterned photoresist layer 150 is removed, i.e., the remaining portion gla1 at the via 131 is exposed.
Next, referring to fig. 2 and 3I, a third patterned conductive layer 160 is formed on the substrate 110, and the third patterned conductive layer 160 may include: the source electrode 121a, the drain electrode 121b, and a stacked portion (i.e., a main portion gla2 of the patch cord gl), wherein the stacked portion gla2 is located on the remaining portion gla1.
The third patterned conductive layer 160 may include: the main portion gla2 of the patch cord gl, the data line DL, the source electrode 121a, and the drain electrode 121b, wherein the stacked portion of the third patterned conductive layer 160 is the main portion gla2 of the patch cord gl. Referring to fig. 3I, a main portion gla2 of the interposer gl of the third pattern layer 160 is disposed on the reserved portion gla1 of the second patterned conductive layer 140, and is electrically connected to an auxiliary portion glb of the interposer gl through the reserved portion gla1.
The steps shown in fig. 3F to 3I are generally called rework steps (reworking steps). As shown in fig. 3F, since the patterned photoresist layer 150 is formed over the remaining portion gla1, the first patterned metal layer 120 (i.e., the auxiliary portion glb of the interposer gl) and the second patterned metal layer 140 (i.e., the main portion gla1 of the interposer gl) at the first via hole 131 may be protected. As a result, as shown in fig. 3G, when the portion to be removed (i.e., the data line DL, the source electrode 121a, and the drain electrode 121 b) of the second patterned conductive layer 140 is removed by using an etching solution, the etching solution does not attack the underlying first patterned metal layer 120 (i.e., the auxiliary portion glb of the interposer gl) through the first via 131. As a result, the yield of the device array substrate 100 can be greatly improved.
The material of the third patterned conductive layer 160 may be the same as or different from the material of the second patterned conductive layer 140. That is, in the fabrication of the third patterned conductive layer 160 of fig. 3I, the same material, mask and photolithography process as the fabrication of the second patterned conductive layer 140 of fig. 3E may be used. Of course, materials, masks and photolithography processes that are different from those used to fabricate the second patterned conductive layer 140 of fig. 3E may also be used.
In addition, the thickness of the third patterned conductive layer 160 and the thickness of the second patterned conductive layer 140 may be the same or different. The thickness of the third patterned conductive layer 160 may be greater than, less than, or equal to the thickness of the second patterned conductive layer 140.
Further, referring to fig. 2 and 3I, the line width W1 of the main portion gla1 or the main portion gla2 of the patch cord gl is smaller than the line width W2 of the auxiliary portion glb of the patch cord gl, but the invention is not limited thereto. In addition, as shown in fig. 2, it can be seen that the area of the auxiliary portion glb of the patch cord gl belonging to the first patterned conductive layer 120 is larger than the area of the main portion gla of the patch cord gl belonging to the third patterned conductive layer 160; the area of the main portion gla of the patch cord gl is larger than the area of the through hole 131.
It is also noted that the source electrode 121a, the drain electrode 121b, the gate electrode 121c, and the semiconductor pattern 121d constitute the active element 121 (i.e., the thin film transistor) of the first pixel 112A, and the insulating layer 130 is interposed between the gate electrode 121c and the semiconductor pattern 121 d.
Next, referring to fig. 3J to 3M, a patterned covering layer 170 (as shown in fig. 3M) is formed on the substrate 110, and the patterned covering layer 170 has a second through hole 174 to expose the drain electrode 121b.
Referring to fig. 3J to 3L, a passivation layer 171, a color filter layer 172, and a planarization layer 173 are sequentially formed on the substrate 110. The protective layer 171 is formed, for example, by plasma chemical vapor deposition or other suitable thin film deposition techniques, and uses a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The color filter layer 172 may include a red filter pattern, a green filter pattern, and a blue filter pattern. The planarization layer 173 may use a light-transmitting organic material or an inorganic material.
Referring to fig. 3M, a second via 174 is formed in the protective layer 171, the color filter layer 172, and the planarization layer 173 to expose the drain electrode 121b. That is, patterning the cover layer 170 may include: a protective layer 171, a color filter layer 172, and a planarization layer 173, and a second via 174 is formed in the patterned cap layer 170.
Next, referring to fig. 3N, a pixel electrode 122 is formed on the substrate 110, and the pixel electrode 122 is electrically connected to the drain electrode 121b of the third patterned conductive layer 160 through the second via 174.
The pixel electrode 122 may be a transparent conductive layer. The material of the pixel electrode 122 may include a metal oxide, for example: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stack of at least two of the foregoing. After the steps of fig. 3A to 3N described above, the fabrication of the element array substrate 100 is completed.
Referring to fig. 3N again, it can be noted that the main portion gla of the patch cord gl includes: the reserved portion (i.e., the main portion gla1 of the patch cord gl) and the laminated portion (i.e., the main portion gla2 of the patch cord gl). The total thickness of the remaining portion and the stacked portion (i.e., the total thickness of the main portions gla1 and gla 2) is greater than the thickness of the data line DL, or the source electrode 121a, or the drain electrode 121b of the third patterned conductive layer 160.
For example, referring to fig. 3N, the total thickness T1 of the main portions gla1 and gla2 (i.e., the total thickness of the main portions gla) is equal to the thickness T2 of the data line DL, the thickness T3 of the drain electrode 121b, or the thickness T4 of the source electrode 121aTo->Between, that is,
in the embodiments of fig. 2 and 3A to 3N, since the patterned photoresist layer 150 is formed above the remaining portion gla1 during the rework process, the first patterned metal layer 120 (i.e., the auxiliary portion glb of the interposer gl) and the second patterned metal layer 140 (i.e., the main portion gla1 of the interposer gl) at the first via 131 can be protected. Thus, when the etching solution is used to remove the portion of the second patterned conductive layer 140 to be removed (i.e., the data line DL, the source electrode 121a, and the drain electrode 121 b), the etching solution does not continuously attack the first patterned metal layer 120 (i.e., the auxiliary portion glb of the interposer gl) downward along the first via 131. Therefore, the manufacturing yield of the device array substrate 100 can be improved.
Hereinafter, a structure of the element array substrate 100 according to an embodiment of the present invention will be described with reference to the accompanying drawings. Referring to fig. 1, 2 and 3N, the device array substrate 100 includes: a plurality of data lines DL and a plurality of gate lines GL. A plurality of data lines DL and a plurality of gate lines GL are disposed on the substrate 110. The plurality of data lines DL are arranged in a first direction x, and the plurality of gate lines GL are arranged in a second direction y, wherein the first direction x is staggered with the second direction y. For example, the first direction x and the second direction y may be perpendicular. In addition, the data line DL and the gate line GL belong to different layers. For example, the gate line GL may selectively belong to the first patterned conductive layer 120, and the data line DL may selectively belong to the third patterned conductive layer 160.
Referring to fig. 1 and 2, the first pixel 112A (112) includes: an active element 121 and a pixel electrode 122. The active device 121 is electrically connected to a corresponding one of the data lines DL and a corresponding one of the gate lines GL, and the pixel electrode 122 is electrically connected to the active device 121.
For example, the active device 121 may be a thin film transistor, which has a source electrode 121a, a drain electrode 121b, a gate electrode 121c and a semiconductor pattern 121d, wherein the source electrode 121a and the drain electrode 121b are respectively electrically connected to different two regions of the semiconductor pattern 121d, the source electrode 121a is electrically connected to a corresponding one of the data lines DL, the gate electrode 121c is electrically connected to a corresponding one of the gate lines GL, and the drain electrode 121b is electrically connected to the pixel electrode 122. Referring to fig. 2 and 3N, the gate electrode 121c and the common electrode cl may optionally belong to the first patterned conductive layer 120, and the source electrode 121a and the drain electrode 121b may optionally belong to the third patterned conductive layer 160.
Referring to fig. 1, the device array substrate 100 further includes a plurality of patch cords gl. The plurality of patch cords gl are disposed on the substrate 110 and arranged in the first direction x. Referring to fig. 1, fig. 2, and fig. 3N, the first patterned conductive layer 120 further includes an auxiliary portion glb of the patch cord gl. The laminated portion (i.e., the main portion gla2 of the patch cord gl) includes the main portion gla of the patch cord gl. The main portion gla (gla 2) is electrically connected to the auxiliary portion gla through the remaining portion gla 1.
That is, referring to fig. 2, each of the transfer lines gl may include a main portion gla and an auxiliary portion glb electrically connected to each other through the through hole 131; that is, the patch cord gl may include: a main portion gla and an auxiliary portion glb respectively belonging to different patterned conductive layers and electrically connected to each other through the first via 131. In this way, the patch cord gl has a double-layer metal wiring design, which is conducive to reducing the overall resistance of the patch cord gl, so that the device array substrate 100 is easy to drive.
Referring to fig. 2, 3E and 3N, the main portion gla of the plurality of patch cords gl may optionally belong to the second patterned conductive layer 140 and the third patterned conductive layer 160. The auxiliary portions glb of the plurality of patch cords gl may selectively belong to the first patterned conductive layer 120.
Referring to fig. 2 and 3N, the device array substrate 100 may include: the substrate 110, the first patterned conductive layer 120, the insulating layer 130, the semiconductor pattern 121d, the second patterned conductive layer 140, the third patterned conductive layer 160, the patterned capping layer 170, and the pixel electrode 122.
The first patterned conductive layer 120 is disposed on the substrate 110 and includes a gate 121c. The first patterned conductive layer 120 may further include an auxiliary portion glb of the patch cord.
The insulating layer 130 is disposed on the substrate 110 and covers the first patterned conductive layer 120. The insulating layer 130 has a first via 131. As can be seen from fig. 2 and 3N, the first through hole 131 is located at the position of the auxiliary portion glb of the patch cord gl.
The semiconductor pattern 121d is on the insulating layer 130 and over the gate electrode 121c.
The second patterned conductive layer 140 has a remaining portion gla1, and the remaining portion gla1 is filled into the first via 131 and electrically connected to the first patterned conductive layer 120. As can be seen from fig. 2 and 3N, the remaining portion gla1 of the second patterned conductive layer 140 is electrically connected to the auxiliary portion glb of the patch cord gl of the first patterned conductive layer 120.
The third patterned conductive layer 160 is disposed on the substrate 110, and the third patterned conductive layer 160 includes a source electrode 121a, a drain electrode 121b, and a stacked portion gla2, wherein the stacked portion gla2 is disposed on the remaining portion gla 1. As can be seen from fig. 2 and 3N, the third patterned conductive layer 160 may further include: and a data line DL connected to the source electrode 121 a.
The patterned cap layer 170 has a second via 174. The patterned coating 170 may include a protective layer 171, a color filter layer 172, and a planarization layer 173. As can be seen from fig. 3M and 3N, the second via 170 is formed in the protective layer 171, the color filter layer 172, and the planarization layer 173. The pixel electrode 122 is electrically connected to the drain electrode 121b through the second via 174.
Referring to fig. 3N, it can be noted that the main portion gla of the patch cord gl includes: a remaining portion (i.e., a main portion gla 1) and a laminated portion (i.e., a main portion gla 2). The total thickness T1 of the remaining portion and the stacked portion (i.e., the total thickness of the main portion gla) is greater than the thickness T2 of the data line DL of the third patterned conductive layer 160, the thickness T3 of the drain electrode 121b, or the thickness T4 of the source electrode 121 a.
Referring to FIG. 3N, the difference between the total thickness T1 of the main portion gla and the thickness T2 of the data line DL can be betweenTo the point ofBetween them. In other embodiments, the difference between the total thickness T1 of the main portion gla and the thickness T2 of the data line DL can be between +.>To->Between them. In a further embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T2 of the data line DL can be between +.>To->Between them.
Referring to FIG. 3N, the difference between the total thickness T1 of the main portion gla and the thickness T3 of the drain 121b may be To the point ofBetween them. In another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T3 of the drain 121b may be betweenTo->Between them. In a further embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T3 of the drain electrode 121b may be between +.>To->Between them.
Referring to FIG. 3N, the difference between the total thickness T1 of the main portion gla and the thickness T4 of the source 121a may beTo the point ofBetween them. In another embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T4 of the source 121a can be betweenTo->Between them. In a further embodiment, the difference between the total thickness T1 of the main portion gla and the thickness T4 of the source 121a may be between +.>To->Between them.
As described above, as shown in fig. 3N, at the position of the through hole 131, there are provided: the remaining portion gla1 of the second patterned conductive layer 140, and the stacked portion gla2 of the third patterned conductive layer 160. The total thickness T1 of the remaining portion gla1 and the stacked portion gla2 is greater than the thickness T2 of the data line DL, the thickness T3 of the drain electrode 121b, or the thickness T4 of the source electrode of the third patterned conductive layer 160. In this way, the patterned conductive layers of different layers can be electrically connected by the through holes 131, so as to achieve the design of a dual-layer metal trace, which is helpful for reducing the overall resistance of the trace, and the device array substrate 100 is easy to drive.
Fig. 4 is an enlarged schematic view of a second pixel 112B (112) of the element array substrate of fig. 1. At the periphery of the second pixel 112B (112), a data line DL, a bridge element BL, a transfer line GL, a gate line GL, a common electrode CL, and a common electrode pattern CL are also drawn.
Fig. 5A to 5K are schematic cross-sectional views illustrating a step flow of a method for manufacturing the device array substrate along the cross-sectional line B-B' of fig. 4. Hereinafter, a method of manufacturing the element array substrate 100 will be described with reference to fig. 4 and 5A to 5K.
First, referring to fig. 4 and 5A, a substrate 110 is provided. For example, the material of the substrate 110 may be glass. However, the material of the substrate 110 may be quartz, an organic polymer, or an opaque/reflective material (e.g., wafer, ceramic, etc.), or other suitable materials.
Next, referring to fig. 4 and fig. 5A, a first patterned conductive layer 120 is formed on the substrate 110. The first patterned conductive layer 120 may include: and sharing an electrode cl. In addition, referring to fig. 4, the first patterned conductive layer 120 may further include: a gate line GL provided in parallel with the common electrode CL (i.e., the common electrode pattern CL), and a gate electrode 121c connected to the gate line GL. The material and the forming method of the first patterned conductive layer 120 can refer to the foregoing embodiments, and are not repeated here.
Next, referring to fig. 4 and fig. 5B, an insulating layer 130 is formed on the substrate 110 to cover the first patterned conductive layer 120. The material and forming method of the insulating layer 130 may refer to the foregoing embodiments, and will not be repeated here.
Next, referring to fig. 4 and fig. 5C, a first via 131 is formed in the insulating layer 130 to expose the first patterned conductive layer 120. In this embodiment, the formation position of the first via hole 131 may be located at a position where the common electrode cl is exposed.
Then, referring to fig. 4 and fig. 5D, a second patterned conductive layer 140 is formed on the insulating layer 130. The second patterned conductive layer 140 has: a portion to be removed (i.e., the data line DL shown in fig. 5D) and a remaining portion (i.e., the bridging element BL1 shown in fig. 5D). The remaining portion BL1 fills the first via 131 and is electrically connected to the first patterned conductive layer 120 (i.e., the common electrode cl shown in fig. 5D).
Referring to fig. 4 and 5D, the second patterned conductive layer 140 may include: the remaining portion of the second patterned conductive layer 140 is the bridging element BL1 filled in the first via 131, and the portion of the second patterned conductive layer 140 to be removed is the data line DL. The material and forming method of the second patterned conductive layer 140 may refer to the foregoing embodiments, and will not be repeated here.
Then, referring to fig. 5E to 5G, a patterned photoresist layer 150 is formed to cover the remaining portion BL1, and the portion to be removed (i.e., the data line DL) of the second patterned conductive layer 140 is removed.
Referring to fig. 5E, the method for forming the patterned photoresist layer 150 may include the following steps: first, a photoresist layer (not shown) is formed on a substrate 110; then, most of the photoresist layer is removed, and the photoresist layer above the remaining portion (i.e., the bridge element BL 1) remains to form the patterned photoresist layer 150.
Referring to fig. 5F, the second patterned conductive layer 140 (i.e., the data line DL) not covered by the patterned photoresist layer 150 is removed.
Then, referring to fig. 5G, the patterned photoresist layer 150 is removed.
Next, referring to fig. 4 and 5H, a third patterned conductive layer 160 is formed on the substrate 110, and the third patterned conductive layer 160 may include: the data line DL and a laminated portion (i.e., a bridge element BL 2), wherein the laminated portion BL2 is located on the remaining portion BL 1.
The third patterned conductive layer 160 may include: the bridge element BL2 and the data line DL, wherein the lamination portion of the third patterned conductive layer 160 is the bridge element BL2. Referring to fig. 5H, the bridge element BL2 is disposed on the remaining portion BL1 of the second patterned conductive layer 140 and is electrically connected to the common electrode cl through the remaining portion BL 1.
The steps shown in fig. 5E to 5H are generally called rework steps (rework steps). As shown in fig. 5E, since the patterned photoresist layer 150 is formed over the remaining portion BL1, the first patterned metal layer (i.e., the common electrode cl) and the second patterned metal layer 140 (i.e., the bridge element BL 1) at the first via 131 can be protected. Thus, as shown in fig. 5F, when the portion to be removed (i.e., the data line DL) of the second patterned conductive layer 140 is removed, for example, an etching solution is used, the etching solution does not attack the underlying first patterned metal layer (i.e., the common electrode cl) through the first via 131. As a result, the yield of the device array substrate 100 can be greatly improved.
Referring to fig. 5H, the material of the third patterned conductive layer 160 may be the same as or different from the material of the second patterned conductive layer 140. In the fabrication of the third patterned conductive layer 160 of fig. 5H, the same materials, mask and photolithography processes as the fabrication of the second patterned conductive layer 140 of fig. 5D may be used. Of course, materials, masks and photolithography processes that are different from those used to fabricate the second patterned conductive layer 140 of fig. 5D may also be used.
In addition, the thickness of the third patterned conductive layer 160 and the thickness of the second patterned conductive layer 140 may be the same or different. The thickness of the third patterned conductive layer 160 may be greater than, less than, or equal to the thickness of the second patterned conductive layer 140. In an embodiment, referring to fig. 4 and 5H, the line width W3 of the bridge element BL1 or the bridge element BL2 is larger than the line width W4 of the common electrode cl, but the invention is not limited thereto. As shown in fig. 4 and 5H, the area of the common electrode cl belonging to the first patterned conductive layer 120 is smaller than the area of the bridge element BL2 belonging to the third patterned conductive layer 160. The area of the bridge element BL is larger than the area of the through hole 131.
Next, referring to fig. 5I to 5K, a passivation layer 171, a color filter layer 172, and a planarization layer 173 are sequentially formed on the substrate 110. The materials and forming methods of the protective layer 171, the color filter layer 172, and the planarization layer 173 can refer to the foregoing embodiments, and will not be repeated here. Then, a photolithography process is performed on the passivation layer 171, the color filter layer 172, and the planarization layer 173, so as to form a patterned passivation layer 170.
Referring to fig. 5K, the bridge element BL includes: the total thickness of the remaining portion (i.e., the bridge element BL 1) and the stacked portion (i.e., the bridge element BL 2), the total thickness of the remaining portion and the stacked portion (i.e., the total thickness of the bridge element BL1 and the bridge element BL 2) is greater than the thickness of the data line DL of the third patterned conductive layer 160.
For example, referring to fig. 5K, the total thickness T5 of the bridge elements BL1 and BL2 and the thickness T6 of the data line DL are different from each otherTo->Between, that is,
in the embodiments of fig. 4 and 5A to 5K, since the patterned photoresist layer 150 is formed above the remaining portion BL1 during the reworking step, the first patterned metal layer (i.e., the common electrode cl) and the second patterned metal layer 140 (i.e., the bridge element BL 1) at the first via 131 can be protected. Thus, when the etching solution is used to remove the portion of the second patterned conductive layer 140 to be removed (i.e., the data line DL), the etching solution does not continuously attack the first patterned metal layer 120 (i.e., the common electrode cl) downward along the first via hole 131. Therefore, the manufacturing yield of the device array substrate 100 can be improved.
Referring to fig. 1, 4 and 5K, the first patterned conductive layer 120 may include a common electrode cl. The lamination portion includes a bridge element BL2. The bridge element BL2 is electrically connected to the common electrode cl through the remaining portion BL 1.
Referring to fig. 4, the common electrode cl is partially overlapped with the pixel electrode 122 to form a storage capacitor. For example, the plurality of second pixels 112B (112) may be arranged in a plurality of pixel columns, the plurality of second pixels 112B (112) of each pixel column being arranged in the first direction x; the common electrodes CL of the second pixels 112B (112) of the same pixel row may be directly connected to form the common electrode pattern CL. The plurality of common electrode patterns CL of the plurality of pixel columns are arranged in the second direction y.
In the device array substrate 100, a plurality of common electrode patterns CL of a plurality of pixel rows may be electrically connected to each other by a plurality of bridge elements BL arranged in the first direction x. That is, referring to fig. 4, in a top view of the device array substrate 100, a plurality of common electrode patterns CL and a plurality of bridge elements BL having the same reference potential may be interleaved into a conductive pattern similar to a mesh shape. However, the present invention is not limited thereto, and the common electrodes cl of the second pixels 112B (112) may be electrically connected to each other by a plurality of bridge elements arranged in other ways according to other embodiments.
For example, referring to fig. 4 and 5K, the common electrode cl may optionally belong to the first patterned conductive layer 120. The plurality of bridge elements BL may optionally belong to the second patterned conductive layer 160 and the third patterned conductive layer 170. The bridging elements BL may be electrically connected to the common electrodes cl through the first through holes 131 of the insulating layer 130, but the invention is not limited thereto. In addition, the bridging element BL can cover the gap between two adjacent pixel electrodes 122, so the bridging element BL can also be called a shielding metal (shielding metal), but the invention is not limited thereto.
Referring to fig. 5K, in the present embodiment, the device array substrate 100 may include: a substrate 110, a first patterned conductive layer 120, an insulating layer 130, a second patterned conductive layer 140, a third patterned conductive layer 160, and a patterned capping layer 170.
The first patterned conductive layer 120 includes a common electrode cl. The insulating layer 130 is disposed on the substrate 110 and covers the first patterned conductive layer 120. The insulating layer 130 has a first via 131. As can be seen from fig. 4 and 5K, the first through hole 131 is located at the position of the common electrode cl.
The second patterned conductive layer 140 has a remaining portion (i.e. the bridge element BL 1), and the remaining portion BL1 is filled into the first via 131 and electrically connected to the common electrode cl of the first patterned conductive layer 120.
The third patterned conductive layer 160 is disposed on the substrate 110, and the third patterned conductive layer 160 includes a data line DL and a stacked portion (i.e., the bridge element BL 2). The lamination portion BL2 is located on the remaining portion BL 1. The patterned coating 170 may include a protective layer 171, a color filter layer 172, and a planarization layer 173.
Referring to fig. 5K, it can be noted that the total thickness T5 of the remaining portion BL1 and the stacked portion BL2 (i.e., the total thickness of the bridge element BL) is greater than the thickness T6 of the data line DL of the third patterned conductive layer 160.
Referring to FIG. 5K, the difference between the total thickness T5 of the bridge element BL and the thickness T6 of the data line DL is betweenTo the point ofBetween them. In another embodiment, the difference between the total thickness T5 of the bridge element BL and the thickness T6 of the data line DL is between +.>To->Between them. In a further embodiment, the difference between the total thickness T5 of the bridge element BL and the thickness T6 of the data line DL can be between +.>To->Between them.
Referring to fig. 4 and 5K, the common electrode CL (common electrode pattern CL) extends in the first direction x, and the bridge element BLl (including the remaining portion BL1 and the stacked portion BL 2) extends in the second direction y intersecting the first direction x, and the bridge element BL can be connected to the common electrode CL through the first via 131.
As described above, at the position of the through hole 131, there are provided: the remaining portion gla1 of the second patterned conductive layer 140, and the stacked portion gla2 of the third patterned conductive layer 160. The total thickness T1 of the remaining portion gla1 and the stacked portion gla2 is greater than the thickness T2 of the data line DL, the thickness T3 of the drain electrode 121b, or the thickness T4 of the source electrode of the third patterned conductive layer 160. In this way, the patterned conductive layers of different layers can be electrically connected by the through holes 131, so as to achieve the design of a dual-layer metal trace, which is helpful for reducing the overall resistance of the trace, and the device array substrate 100 is easy to drive.
Fig. 6 is a schematic cross-sectional view of the device array substrate along the cross-sectional line C-C' of fig. 4. Referring to fig. 4 and 6, it can be seen that: the substrate 110, the first patterned conductive layer 120, the insulating layer 130, the second patterned conductive layer 140, the third patterned conductive layer 160, and the patterned capping layer 170.
The first patterned conductive layer 120 includes: and a gate line GL connected to the gate electrode 121 c. The insulating layer 130 covers the first patterned conductive layer 120. The insulating layer 130 has a first via 131. Note that, in this embodiment, the formation position of the first via hole 131 is located at a position where the gate line GL is exposed.
The second patterned conductive layer 140 has a remaining portion (i.e., a main portion gla1 of the interposer GL), and the remaining portion gla1 is filled into the first via 131 and electrically connected to the gate line GL of the first patterned conductive layer 120. The third patterned conductive layer 160 includes a data line DL and a stacked portion (i.e., a main portion gla2 of the patch cord gl), the stacked portion gla2 being located on the reserved portion gla 1. The main portion gla2 is electrically connected to the gate line GL through the remaining portion gla 1. The patterned coating 170 may include a protective layer 171, a color filter layer 172, and a planarization layer 173.
In the present embodiment, the main portion gla of the patch cord gl includes: the reserved portion (i.e., the main portion gla1 of the patch cord gl) and the laminated portion (i.e., the main portion gla2 of the patch cord gl). The total thickness of the remaining portion and the stacked portion (i.e., the total thickness of the main portions gla1 and gla 2) is greater than the thickness of the data line DL of the third patterned conductive layer 160.
Referring to fig. 6, the total thickness T7 of the main portions gla1 and gla2 is greater than the thickness T8 of the data line DL of the third patterned conductive layer 160. For example, the total thickness T7 of the main portions gla1 and gla2 (i.e. the total thickness of the main portions gla) and the thickness T8 of the data line DL are betweenTo->Between, that is,
in another embodiment, the difference between the total thickness T7 of the main portions gla1 and gla2 and the thickness T8 of the data line DL can be betweenTo->Between them. In a further embodiment, the difference between the total thickness T7 of the main portions gla1 and gla2 and the thickness T8 of the data line DL can be between + ->To->Between them.
Referring to fig. 4 and 6, the gate line GL extends in a first direction x, and a main portion gla (including a remaining portion gla1 and a stacked portion gla 2) of the switching line GL extends in a second direction y intersecting the first direction x. The main portion gla of the patch cord GL may be connected to the gate line GL through the first through hole 131. In other words, the gate line GL may be connected to the main portion gla of the patch line GL through the first through hole 131 to extend from the first direction x to the second direction y. In this way, the driving device 200 (as shown in fig. 1) can be disposed on only one side of the device array substrate 100, so that the gate line GL can be used to scan in the first direction x and the second direction y, which is helpful for reducing the layout area of the peripheral circuit region of the device array substrate 100, and further achieving the design of a narrow frame.
In the above-described element array substrate 100, a plurality of embodiments in which two conductive layers are connected through the first via 131 are described, that is: as shown in fig. 3N, the main portion gla of the patch cord gl and the auxiliary portion glb of the patch cord gl connected through the first through hole 131 are described; as shown in fig. 5K, the bridging element BL and the common electrode cl connected through the first through hole 131 are described; and, as shown in fig. 6, the main portion gla of the patch cord GL and the gate line GL connected through the first through-hole 131 are described, but the present invention is not limited thereto. The above embodiments of connecting two conductive layers through the first through hole 131 may be applied to the same element array substrate, or may be applied to different element array substrates, depending on design requirements.
In summary, the manufacturing method of the element array substrate and the element array substrate of the present invention have at least the following technical effects: before the second conductive layer is reworked, the through hole connecting the first conductive layer and the second conductive layer is covered with the patterned photoresist layer in advance, so that etching liquid can be prevented from corroding the second conductive layer at the through hole, and etching liquid is prevented from corroding the first conductive layer downwards. Therefore, the manufacturing yield of the element array substrate can be improved. In addition, the element array substrate of the embodiment of the invention can electrically connect the conductive layers of different film layers by using the through holes, thereby realizing the design of double-layer metal wiring and being beneficial to: the overall resistance of the wiring is reduced, so that the element array substrate is easy to drive, and the layout area of the peripheral circuit area of the element array substrate can be reduced, thereby achieving the design of a narrow frame.
Of course, the present invention is capable of other various embodiments and its several details are capable of modification and variation in light of the present invention, as will be apparent to those skilled in the art, without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. The manufacturing method of the element array substrate is characterized by comprising the following steps:
providing a substrate;
forming a first patterned conductive layer on the substrate, wherein the first patterned conductive layer comprises a grid electrode;
forming an insulating layer on the substrate to cover the first patterned conductive layer;
forming a semiconductor pattern on the insulating layer, wherein the semiconductor pattern is positioned above the grid electrode;
forming a first through hole in the insulating layer to expose the first patterned conductive layer;
forming a second patterned conductive layer on the insulating layer, wherein the second patterned conductive layer is provided with a part to be removed and a reserved part, and the reserved part is filled in the first through hole and is electrically connected with the first patterned conductive layer;
forming a patterned photoresist layer to cover the reserved portion and removing the portion to be removed of the second patterned conductive layer;
Removing the patterned photoresist layer;
forming a third patterned conductive layer on the substrate, wherein the third patterned conductive layer comprises a source electrode, a drain electrode and a lamination part, and the lamination part is positioned on the reserved part;
forming a patterned covering layer on the substrate, wherein the patterned covering layer is provided with a second through hole so as to expose the drain electrode; and
forming a pixel electrode on the substrate, wherein the pixel electrode is electrically connected with the drain electrode through the second through hole;
wherein the total thickness of the remaining portion and the stacked portion is greater than the thickness of the source electrode or the drain electrode of the third patterned conductive layer;
the first patterned conductive layer further comprises an auxiliary part of a patch cord, the laminated part comprises a main part of the patch cord, and the main part is electrically connected with the auxiliary part through the reserved part;
the first patterned conductive layer further comprises a common electrode, the laminated part comprises a bridging element, and the bridging element is electrically connected with the common electrode through the reserved part;
the first patterned conductive layer further comprises a gate line connected with the gate, the gate line extends in a first direction, and the patch cord extends in a second direction intersecting the first direction.
2. The method of claim 1, wherein the line width of the main portion of the patch cord is smaller than the line width of the auxiliary portion of the patch cord.
3. The method of claim 1, wherein the line width of the bridge element is greater than the line width of the common electrode.
4. The method of claim 1, wherein the stacked portion includes a main portion of a transfer line, the main portion being electrically connected to the gate line through the remaining portion.
5. The method of claim 1, wherein the material of the third patterned conductive layer is the same as the material of the second patterned conductive layer.
6. The method of manufacturing a device array substrate of claim 1, wherein the step of forming the patterned coating layer comprises:
forming a first protective layer, a color filter layer and a second protective layer on the substrate; and
and patterning the first protective layer, the color filter layer and the second protective layer.
7. An element array substrate, comprising:
A substrate;
a first patterned conductive layer on the substrate, the first patterned conductive layer including a gate;
an insulating layer on the substrate, wherein the insulating layer covers the first patterned conductive layer and has a first through hole;
a semiconductor pattern on the insulating layer, the semiconductor pattern being above the gate electrode;
the second patterned conductive layer is provided with a reserved part which is filled in the first through hole and is electrically connected with the first patterned conductive layer;
a third patterned conductive layer on the substrate, the third patterned conductive layer including a source electrode, a drain electrode, and a stacked portion, the stacked portion being on the remaining portion;
a patterned covering layer having a second through hole; and
a pixel electrode electrically connected with the drain electrode through the second through hole;
wherein the total thickness of the remaining portion and the stacked portion is greater than the thickness of the source electrode or the drain electrode of the third patterned conductive layer;
the first patterned conductive layer further comprises an auxiliary part of a patch cord, the laminated part comprises a main part of the patch cord, and the main part is electrically connected with the auxiliary part through the reserved part;
The first patterned conductive layer further comprises a common electrode, the laminated part comprises a bridging element, and the bridging element is electrically connected with the common electrode through the reserved part;
the first patterned conductive layer further includes: and a gate line connected to the gate electrode, the gate line extending in a first direction, the patch cord extending in a second direction intersecting the first direction.
8. The device array substrate of claim 7, wherein a difference between a total thickness of the remaining portion and the stacked portion and a thickness of the source electrode or the drain electrode is betweenTo->Between them.
9. The device array substrate of claim 7, wherein a line width of the main portion of the interposer is smaller than a line width of the auxiliary portion of the interposer.
10. The device array substrate of claim 7, wherein the third patterned conductive layer further comprises: and a data line connected with the source electrode.
11. The device array substrate of claim 7, wherein the line width of the bridge element is greater than the line width of the common electrode.
12. The device array substrate of claim 7, wherein the stacked portion includes a main portion of a transfer line, the main portion being electrically connected to the gate line through the retention portion.
13. The device array substrate of claim 7, wherein the material of the third patterned conductive layer is the same as the material of the second patterned conductive layer.
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| TW109124052A TWI754323B (en) | 2019-12-04 | 2020-07-16 | Device array substrate and manufacturing method thereof |
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| CN104201152A (en) * | 2014-06-17 | 2014-12-10 | 友达光电股份有限公司 | Method for manufacturing display panel |
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| KR101988522B1 (en) * | 2012-09-11 | 2019-06-12 | 엘지디스플레이 주식회사 | Method of forming low resistance wire and method of manufacturing thin film transistor using the same |
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