CN215183965U

CN215183965U - Pixel array substrate

Info

Publication number: CN215183965U
Application number: CN202121490248.2U
Authority: CN
Inventors: 许倩雯; 郑圣谚; 林弘哲; 徐雅玲; 黄俊儒; 何昇儒; 廖乾煌; 锺岳宏; 李珉泽; 郭子维; 侯舜龄; 王奕筑; 陈品妏; 廖烝贤
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-03
Filing date: 2021-07-01
Publication date: 2021-12-14
Anticipated expiration: 2031-07-01
Also published as: CN114068584A

Abstract

A pixel array substrate comprises a plurality of data lines, a plurality of gate lines, a plurality of pixel structures, a plurality of transfer lines and a common line. The plurality of data lines are arranged in a first direction. The plurality of gate lines are arranged in a second direction. The plurality of transfer lines are electrically connected to the plurality of gate lines and are arranged in the first direction. The first data line has a first portion disposed outside the pixel electrode of the first pixel structure and beside the active device of the first pixel structure. In a top view of the pixel array substrate, the active device of the first pixel structure has a first side and a second side opposite to each other, the first transfer line is disposed on the first side of the active device of the first pixel structure, and the first portion of the first data line and the common line are disposed on the second side of the active device of the first pixel structure.

Description

Pixel array substrate

Technical Field

The utility model relates to a pixel array substrate.

Background

With the development of display technologies, the demands of people for display devices are no longer satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle, and people expect that display devices have elegant appearance. For example, it is also desirable for display devices to have narrow, even no, borders.

Generally, a display device includes a plurality of pixel structures disposed in a display region, a data driving circuit disposed below the display region, and a gate driving circuit disposed on the left, right, or left and right sides of the display region. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit may be disposed at the lower side of the display region. When the gate driving circuit is disposed at the lower side of the display region, the gate line extending in the horizontal direction should be electrically connected to the gate driving circuit via the transfer line extending in the vertical direction. However, the patch cord is inserted between the pixel structures, and the signal variation of the patch cord easily affects the voltage of the pixel electrode, which is not favorable for the display quality of the display device.

SUMMERY OF THE UTILITY MODEL

The utility model provides a pixel array substrate, the characteristic is good.

The utility model provides another kind of pixel array substrate, the characteristic is good.

The utility model discloses a pixel array substrate of an embodiment includes basement, many data lines, many gate lines, a plurality of pixel structures, many patch cords and sharing line. The data lines are arranged on the substrate and are arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to the corresponding data line and the corresponding gate line. The plurality of patch cords are disposed on the substrate, electrically connected to the plurality of gate lines, and arranged in a first direction. The common line is disposed on the substrate, wherein the plurality of data lines and the common line are arranged in a first direction. The plurality of pixel structures includes a first pixel structure, the plurality of data lines includes a first data line electrically connected to the first pixel structure, and the plurality of transfer lines includes a first transfer line. The first data line is provided with a first part, is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure. Each pixel structure has a first side and a second side opposite to each other. In a top view of the pixel array substrate, the first transfer line is disposed on a first side of the active device of the first pixel structure, and the first portion of the first data line and the common line are disposed on a second side of the active device of the first pixel structure.

The utility model discloses a pixel array substrate of an embodiment includes basement, many data lines, many gate lines, a plurality of pixel structure and many patch cords. The data lines are arranged on the substrate and are arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. The pixel structures are arranged on the substrate, wherein each pixel structure comprises an active element and a pixel electrode electrically connected to the active element, and the active element is electrically connected to the corresponding data line and the corresponding gate line. The plurality of patch cords are disposed on the substrate, electrically connected to the plurality of gate lines, and arranged in a first direction. The plurality of patch cords includes a first patch cord. The plurality of pixel structures comprise a first pixel structure and a second pixel structure which are respectively arranged on two opposite sides of the first transfer line. The plurality of data lines comprise a first data line and a second data line which are respectively and electrically connected to the first pixel structure and the second pixel structure. The first data line is provided with a first part, is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure. The second data line is provided with a second part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure. In a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the second data line is disposed on the first side of the active device of the second pixel structure.

In an embodiment of the present invention, in the top view of the pixel array substrate, the first portion of the first data line and the first transfer line have a first distance in the first direction, the first portion of the first data line and the common line have a second distance in the first direction, and the first distance is greater than the second distance.

In an embodiment of the present invention, the plurality of pixel structures further includes a second pixel structure, and the first pixel structure and the second pixel structure are disposed adjacent to each other and arranged in the first direction; the plurality of data lines further comprise second data lines electrically connected to the second pixel structures; the plurality of patch cords further comprise a second patch cord; the second data line is provided with a first part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure; in a top view of the pixel array substrate, the first portions of the common line and the second data line are disposed on a first side of the active device of the second pixel structure, and the second patch line is disposed on a second side of the active device of the second pixel structure.

In an embodiment of the present invention, in the above-mentioned top view of the pixel array substrate, the first portion of the second data line and the common line have a third distance in the first direction, the first portion of the second data line and the second patch line have a fourth distance in the first direction, and the fourth distance is greater than the third distance.

In an embodiment of the present invention, the plurality of pixel structures further include a third pixel structure, and the first pixel structure, the second pixel structure and the third pixel structure are sequentially arranged in the first direction; the plurality of data lines further comprise third data lines electrically connected to the third pixel structures; the plurality of patch cords further comprise a third patch cord; the third data line has a first portion disposed outside the pixel electrode of the third pixel structure and beside the active device of the third pixel structure. In a top view of the pixel array substrate, the first portions of the second patch cord and the third data cord are disposed on a first side of the active device of the third pixel structure, and the third patch cord is disposed on a second side of the active device of the third pixel structure; or, in a top view of the pixel array substrate, the second patch cord is disposed on a first side of the active device of the third pixel structure, and the first portion of the third data line and the third patch cord are disposed on a second side of the active device of the third pixel structure.

In an embodiment of the present invention, the third pixel structure is used for displaying blue.

In an embodiment of the present invention, the pixel array substrate further includes: and the transparent conducting layer is arranged between the data line and the pixel electrode of the pixel structure. The transparent conductive layer is provided with a plurality of openings which are overlapped with the pixel electrodes of the pixel structure.

The utility model discloses a pixel array substrate of an embodiment includes basement, many data lines, many gate lines, a plurality of pixel structure and transparent conducting layer. The data lines are arranged on the substrate and are arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. The pixel structure comprises an active element and a pixel electrode which is electrically connected to the active element, and the active element is electrically connected to a corresponding data line and a corresponding gate line. The data line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is arranged between the data line and the pixel electrode of the pixel structure. The transparent conductive layer is provided with a plurality of openings which are overlapped with the pixel electrodes of the pixel structure.

In an embodiment of the invention, in the top view of the pixel array substrate, the openings of the transparent conductive layer are located at two opposite sides of the data line.

In an embodiment of the present invention, the pixel electrodes of the common line, the transparent conductive layer and the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

In an embodiment of the present invention, the pixel electrode of the pixel structure has a plurality of slits overlapping the plurality of openings of the transparent conductive layer.

In an embodiment of the present invention, in the above-mentioned top view of the pixel array substrate, the plurality of slits of the pixel electrode are disposed in the first range, the plurality of openings of the transparent conductive layer are disposed in the second range, the first range and the second range are overlapped, and an area of the second range is smaller than an area of the first range.

In an embodiment of the present invention, the pixel electrode of the pixel structure has a plurality of first branch portions, the first branch portions are spaced apart from each other to define a plurality of slits, the first branch portions have a first line width, and two adjacent first branch portions have a first distance; the transparent conducting layer is provided with a plurality of second branch parts which are spaced from each other to define a plurality of openings, each second branch part is provided with a second line width, and two adjacent second branch parts are provided with a second interval; the sum of the second line width and the second interval of the transparent conducting layer is larger than the sum of the first line width and the first interval of the pixel electrode.

In an embodiment of the invention, the transparent conductive layer has a first solid portion overlapping the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining a plurality of openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line.

In an embodiment of the present invention, the plurality of pixel structures further includes a fourth pixel structure. The first pixel structure and the fourth pixel structure are respectively arranged on two opposite sides of the first transfer line. The plurality of data lines further comprise a fourth data line electrically connected to the fourth pixel structure. The fourth data line has a first portion disposed outside the pixel electrode of the fourth pixel structure and beside the active device of the fourth pixel structure. In a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fourth data line is disposed on the first side of the active device of the fourth pixel structure.

In an embodiment of the present invention, the first pixel structure and the fourth pixel structure are respectively configured to display red and blue.

In an embodiment of the present invention, the plurality of pixel structures further includes a fifth pixel structure and a sixth pixel structure. The fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are sequentially arranged in the first direction. The fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are respectively used for displaying blue, red, green and blue. The plurality of data lines further include a fifth data line electrically connected to the fifth pixel structure. The fifth data line has a first portion disposed outside the pixel electrode of the fifth pixel structure and beside the active device of the fifth pixel structure. The plurality of data lines further comprise a sixth data line electrically connected to the sixth pixel structure. The sixth data line has a first portion disposed outside the pixel electrode of the sixth pixel structure and beside the active device of the sixth pixel structure. In a top view of the pixel array substrate, the first portion of the fifth data line is disposed on the second side of the active device of the fifth pixel structure, and the first portion of the sixth data line is disposed on the first side of the active device of the sixth pixel structure.

In an embodiment of the present invention, the plurality of pixel structures further includes a fifth pixel structure. The fourth pixel structure, the first pixel structure and the fifth pixel structure are sequentially arranged in the first direction. The fourth pixel structure, the first pixel structure and the fifth pixel structure are respectively used for displaying blue, red and green. The plurality of data lines further include a fifth data line electrically connected to the fifth pixel structure. The fifth data line has a first portion disposed outside the pixel electrode of the fifth pixel structure and beside the active device of the sixth pixel structure. In a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fifth data line is disposed on the first side of the active device of the fifth pixel structure.

In an embodiment of the invention, in the above-mentioned top view of the pixel array substrate, the edge of the solid portion of the transparent conductive layer has a minimum distance from the edge of the data line, and the minimum distance is greater than or equal to 5 μm and less than or equal to 8 μm.

In an embodiment of the invention, the plurality of openings of the transparent conductive layer are arranged in the first direction.

In an embodiment of the invention, the plurality of openings of the transparent conductive layer are arranged in the second direction.

In an embodiment of the present invention, the plurality of openings of the transparent conductive layer are arranged in a fourth direction, and the first direction, the second direction and the fourth direction are different from each other.

In an embodiment of the present invention, the pixel electrode of the pixel structure has a plurality of slits overlapping the plurality of openings of the transparent conductive layer; a plurality of slits arranged in a fifth direction; the fourth direction is substantially the same as the fifth direction.

In an embodiment of the present invention, the pixel electrode of the pixel structure has a plurality of slits overlapping the plurality of openings of the transparent conductive layer; a plurality of slits arranged in a fifth direction; the fourth direction and the fifth direction form an angle theta, and the angle theta is more than 0 degree and less than or equal to 90 degrees.

In an embodiment of the present invention, the transparent conductive layer has a plurality of second branch portions interlaced to form a mesh shape to define a plurality of openings.

Particularly, the utility model provides a pixel array substrate, a serial communication port, include:

a substrate;

a plurality of data lines disposed on the substrate and arranged in a first direction;

a plurality of gate lines disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered;

a plurality of pixel structures disposed on the substrate, wherein each pixel structure includes an active device and a pixel electrode electrically connected to the active device, and the active device is electrically connected to a corresponding data line and a corresponding gate line;

a plurality of patch cords disposed on the substrate, electrically connected to the gate lines, and arranged in the first direction; and

a common line disposed on the substrate, wherein the data lines and the common line are arranged in the first direction;

the pixel structures comprise a first pixel structure, the data lines are electrically connected to a first data line of the first pixel structure, and the transfer lines comprise first transfer lines;

the first data line is provided with a first part, is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure;

each of the pixel structures is provided with a first side and a second side which are opposite;

in a top view of the pixel array substrate, the first transfer line is disposed on the first side of the active device of the first pixel structure, and the first portion of the first data line and the common line are disposed on the second side of the active device of the first pixel structure.

Preferably, in a top view of the pixel array substrate, the first portion of the first data line and the first transfer line have a first distance in the first direction, the first portion of the first data line and the common line have a second distance in the first direction, and the first distance is greater than the second distance.

Preferably, the pixel structures further include a second pixel structure, and the first pixel structure and the second pixel structure are disposed adjacent to each other and arranged in the first direction; the data lines further comprise a second data line electrically connected to the second pixel structure; the patch cords also comprise a second patch cord; the second data line is provided with a first part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure; in a top view of the pixel array substrate, the first portions of the common line and the second data line are disposed on the first side of the active device of the second pixel structure, and the second patch line is disposed on the second side of the active device of the second pixel structure.

Preferably, in a top view of the pixel array substrate, the first portion of the second data line has a third distance from the common line in the first direction, the first portion of the second data line has a fourth distance from the second patch cord in the first direction, and the fourth distance is greater than the third distance.

Preferably, the pixel structures further include a third pixel structure, and the first pixel structure, the second pixel structure and the third pixel structure are sequentially arranged in the first direction; the data lines further comprise a third data line electrically connected to the third pixel structure; the patch cords also comprise a third patch cord; the third data line has a first portion disposed outside the pixel electrode of the third pixel structure and beside the active device of the third pixel structure;

in a top view of the pixel array substrate, the first portions of the second patch cord and the third data line are disposed on the first side of the active device of the third pixel structure, and the third patch cord is disposed on the second side of the active device of the third pixel structure;

or, in a top view of the pixel array substrate, the second patch cord is disposed on the first side of the active device of the third pixel structure, and the first portion of the third data line and the third patch cord are disposed on the second side of the active device of the third pixel structure.

Preferably, the pixel array substrate further includes:

a transparent conductive layer, wherein the data line, the transparent conductive layer and a pixel electrode of the pixel structure are stacked in a third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the data line and the pixel electrode of the pixel structure;

the transparent conductive layer has a plurality of openings overlapping the pixel electrode of the pixel structure.

Preferably, in a top view of the pixel array substrate, the openings of the transparent conductive layer are located at two opposite sides of the data line.

Preferably, the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in the third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

Preferably, the pixel electrode of the pixel structure has a plurality of slits overlapping the openings of the transparent conductive layer.

Preferably, in a top view of the pixel array substrate, the slits of the pixel electrode are disposed in a first range, the openings of the transparent conductive layer are disposed in a second range, the first range and the second range are overlapped, and an area of the second range is smaller than an area of the first range.

Preferably, the pixel electrode of the pixel structure has a plurality of first branch portions, the first branch portions are spaced apart from each other to define the slits, one first branch portion has a first line width, and two adjacent first branch portions have a first distance; the transparent conductive layer is provided with a plurality of second branch parts which are separated from each other to define the openings, one second branch part is provided with a second line width, and two adjacent second branch parts are provided with a second interval; the sum of the second line width and the second interval of the transparent conducting layer is larger than the sum of the first line width and the first interval of the pixel electrode.

Preferably, the transparent conductive layer has a first solid portion overlapping with the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining the openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line.

Preferably, the pixel structures further include a fourth pixel structure; the first pixel structure and the fourth pixel structure are respectively arranged at two opposite sides of the first transfer line; the data lines further comprise a fourth data line electrically connected to the fourth pixel structure; the fourth data line has a first portion disposed outside the pixel electrode of the fourth pixel structure and beside the active device of the fourth pixel structure; in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fourth data line is disposed on the first side of the active device of the fourth pixel structure.

Preferably, the first pixel structure and the fourth pixel structure are respectively used for displaying red and blue.

Preferably, the pixel structures further include a fifth pixel structure and a sixth pixel structure, and the fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are sequentially arranged in the first direction; the fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are respectively used for displaying blue, red, green and blue; the data lines further comprise a fifth data line electrically connected to the fifth pixel structure; the fifth data line has a first portion disposed outside the pixel electrode of the fifth pixel structure and beside the active device of the fifth pixel structure; the data lines further comprise a sixth data line electrically connected to the sixth pixel structure; the sixth data line has a first portion disposed outside the pixel electrode of the sixth pixel structure and beside the active device of the sixth pixel structure; in a top view of the pixel array substrate, the first portion of the fifth data line is disposed on the second side of the active device of the fifth pixel structure, and the first portion of the sixth data line is disposed on the first side of the active device of the sixth pixel structure.

Preferably, the pixel structures further include a fifth pixel structure, and the fourth pixel structure, the first pixel structure and the fifth pixel structure are sequentially arranged in the first direction; the fourth pixel structure, the first pixel structure and the fifth pixel structure are respectively used for displaying blue, red and green; the data lines further comprise a fifth data line electrically connected to the fifth pixel structure; the fifth data line has a first portion disposed outside the pixel electrode of the fifth pixel structure and beside the active device of the sixth pixel structure; in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fifth data line is disposed on the first side of the active device of the fifth pixel structure.

The utility model discloses still provide a pixel array substrate, include:

a substrate;

a plurality of pixel structures disposed on the substrate, wherein each pixel structure includes an active device and a pixel electrode electrically connected to the active device, and the active device is electrically connected to a corresponding data line and a corresponding gate line; and

a plurality of patch cords disposed on the substrate, electrically connected to the gate lines, and arranged in the first direction;

wherein, the transfer lines comprise a first transfer line; the pixel structures comprise a first pixel structure and a second pixel structure which are respectively arranged at two opposite sides of the first transfer line; the data lines comprise a first data line and a second data line which are respectively and electrically connected to the first pixel structure and the second pixel structure; the first data line is provided with a first part, is arranged outside the pixel electrode of the first pixel structure and is positioned beside the active element of the first pixel structure; the second data line is provided with a second part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure;

in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the second data line is disposed on the first side of the active device of the second pixel structure.

The utility model discloses still provide a pixel array substrate, include:

a substrate;

Preferably, the openings of the transparent conductive layer are arranged in a fourth direction, and the first direction, the second direction and the fourth direction are different from each other.

Preferably, the pixel electrode of the pixel structure has a plurality of slits overlapping the openings of the transparent conductive layer; the slits are arranged in a fifth direction; the fourth direction and the fifth direction form an angle theta, and the angle theta is more than 0 degree and less than or equal to 90 degrees.

Drawings

Fig. 1 is a schematic top view of a display device 10 according to an embodiment of the present invention.

Fig. 2 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 3 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 4 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional view of a display device 10 according to an embodiment of the present invention.

Fig. 6 is a schematic top view of a region of a pixel array substrate 100A according to an embodiment of the invention.

Fig. 7 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the invention.

Fig. 8 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the invention.

Fig. 9 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the invention.

Fig. 10 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention.

Fig. 11 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention.

Fig. 12 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention.

Fig. 13 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention.

Fig. 14 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention.

Fig. 15 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention.

Fig. 16 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention.

Fig. 17 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention.

Fig. 18 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention.

Fig. 19 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention.

Fig. 20 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention.

Fig. 21 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention.

Fig. 22 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention.

Fig. 23 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention.

Fig. 24 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention.

Fig. 25 is a schematic top view of a region of a pixel array substrate 100H according to an embodiment of the invention.

Fig. 26 is a schematic top view of a region of a pixel array substrate 100I according to an embodiment of the invention.

Fig. 27 is a schematic top view of a region of a pixel array substrate 100J according to an embodiment of the invention.

Description of reference numerals:

10: display device

100. 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J: pixel array substrate

110: substrate

120: pixel structure

120-1: first pixel structure

120-2: second pixel structure

120-3: third pixel structure

120-4: fourth pixel structure

120-5: fifth pixel structure

120-6: sixth pixel structure

120-7: seventh pixel structure

120-8: eighth pixel structure

120-9: ninth pixel structure

120-10: tenth pixel structure

120-11: eleventh pixel structure

120-12: twelfth pixel structure

121: active component

121 a: source electrode

121 b: drain electrode

121 c: grid electrode

121 d: semiconductor pattern

122: pixel electrode

122 a: a first trunk part

122 b: second trunk part

122 c: a first branch part

122s, 122s-1, 122s-2, 122s-3, 122 s-4: slit

130. 140, 170: insulating layer

140 a: through hole

150: transparent conductive layer

151: a first solid part

151e, DLe: edge of a container

152. 152-1, 152-2, 152-3, 152-4: opening of the container

153. 153C-1, 153C-2: second branch part

160: color filter pattern layer

200: opposite substrate

210: substrate

220: common electrode

300: display medium

CL: shared wire

CL': common electrode

CL' -1: at least one first part

CL' -2: at least one second part

D1: first distance

D2: second distance

D3: third distance

D4: a fourth distance

DL: data line

DL 1: first data line

DL 2: second data line

DL 3: third data line

DL4 fourth data line

DL 5: the fifth data line

DL 6: sixth data line

DLa: the first part

DLb: the second part

d 4: fourth direction

d 5: the fifth direction

GL: gate line

gl: adapter cable

gl 1: first transfer line

gl 2: second patch cord

gl 3: third patch cord

L1: first line width

L2: second line width

R: alignment zone

S1: first interval

S2: second pitch

RG 1: first range

RG 2: second range

W: minimum distance

x: a first direction

y: second direction

z: third direction

θ: angle of rotation

I-I': cutting line

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately" or "substantially" may be selected based on optical properties, etch properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 3 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the invention. Fig. 3 omits the transparent conductive layer 150 of fig. 2.

Fig. 4 is a schematic top view of a region of a pixel array substrate 100 according to an embodiment of the invention. Fig. 4 omits the plurality of pixel electrodes 122 of fig. 2.

Fig. 5 is a schematic cross-sectional view of a display device 10 according to an embodiment of the present invention. Fig. 5 corresponds to the section line I-I' of fig. 2.

Referring to fig. 1, 2 and 5, the display device 10 includes a pixel array substrate 100, an opposite substrate 200 opposite to the pixel array substrate 100, and a display medium 300 disposed between the pixel array substrate 100 and the opposite substrate 200. For example, in the present embodiment, the display medium 300 may be a liquid crystal. However, the present invention is not limited thereto, and in other embodiments, the display medium 300 may also be a plurality of organic electroluminescent patterns, a plurality of micro light emitting diode elements, or other applicable materials.

The pixel array substrate 100 includes a base 110. The base 110 is used for carrying a plurality of components of the pixel array substrate 100. For example, in the present embodiment, the material of the substrate 110 may be glass. However, the invention is not limited thereto, and according to other embodiments, the substrate 110 may be made of quartz, organic polymer, or opaque/reflective material (e.g., wafer, ceramic, etc.), or other applicable materials.

The pixel array substrate 100 includes a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate 110. The plurality of data lines DL are arranged in a first direction x, and the plurality of gate lines GL are arranged in a second direction y, wherein the first direction x and the second direction y are staggered. For example, in the present embodiment, the first direction x and the second direction y may be perpendicular, but the present invention is not limited thereto.

The data lines DL and the gate lines GL belong to different film layers. For example, in the present embodiment, the gate line GL may selectively belong to a first metal layer, and the data line DL may selectively belong to a second metal layer, but the present invention is not limited thereto.

In view of conductivity, in the present embodiment, a metal material is used for the data line DL and the gate line GL. However, the present invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the data lines DL and the gate lines GL, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.

The pixel array substrate 100 further includes a plurality of pixel structures 120 disposed on the substrate 110. Each pixel structure 120 includes an active device 121 and a pixel electrode 122 electrically connected to the active device 121, and the active device 121 is electrically connected to a corresponding data line DL and a corresponding gate line GL.

For example, in the present embodiment, the active device 121 includes a thin film transistor having a source 121a, a drain 121b, a gate 121c and a semiconductor pattern 121d, the insulating layer 130 is sandwiched between the gate 121c and the semiconductor pattern 121d, the source 121a and the drain 121b are respectively electrically connected to two different regions of the semiconductor pattern 121d, the source 121a is electrically connected to a corresponding data line DL, the gate 121c is electrically connected to a corresponding gate line GL, and the drain 121b is electrically connected to the pixel electrode 122.

Referring to fig. 2 and 3, in the present embodiment, the pixel electrode 122 may optionally have a plurality of slits 122s to define at least one alignment region R of the pixel structure 120. For example, in the present embodiment, the pixel electrode 122 may selectively include a first main portion 122a, a second main portion 122b and a plurality of first branch portions 122 c; the first main portion 122a and the second main portion 122b are staggered to divide a plurality of alignment regions R; in the same alignment region R, the first branch portions 122c extend in the same direction and are spaced apart from each other to define a plurality of slits 122 s; however, the present invention is not limited thereto.

In the present embodiment, a sub-pixel region where the pixel electrode 122 is located may selectively include four alignment regions R. However, the present invention is not limited thereto, and in another embodiment, a sub-pixel region may have other numbers (e.g., one, two, three or more than five) of alignment regions R. In addition, in another embodiment, the pixel electrode 122 may not have the slit 122 s.

Referring to fig. 2 and 5, in the present embodiment, the pixel array substrate 100 further includes a common line CL disposed on the substrate 110, wherein a plurality of data lines DL and the common line CL are arranged in the first direction x. The common line CL may partially overlap the pixel electrode 122 to form a storage capacitor.

In the embodiment, the gate electrode 121c and the gate line GL may selectively belong to a first metal layer, the source electrode 121a, the drain electrode 121b, the data line DL and the common line CL may selectively belong to a second metal layer, the pixel array substrate 100 may further include an insulating layer 140 disposed on the second metal layer, and the pixel electrode 122 may be disposed on the insulating layer 140 and electrically connected to the drain electrode 121b of the thin film transistor through the through hole 140a of the insulating layer 140, but the invention is not limited thereto.

In the present embodiment, the pixel electrode 122 is, for example, transparent, and the material of the transparent pixel electrode 122 may include metal oxides, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stack of at least two of the foregoing. It should be noted that the present invention does not limit the pixel electrode 122 to be transparent; in other embodiments, the pixel electrode 122 may also be reflective or partially reflective and partially transmissive.

Referring to fig. 1 and 2, the pixel array substrate 100 further includes a plurality of patch cords gl disposed on the substrate 110 and arranged in a first direction x. The plurality of patch lines GL arranged in the first direction x are electrically connected to the plurality of gate lines GL arranged in the second direction y, and are interposed between the plurality of pixel structures 120.

For example, in the present embodiment, the gate line GL may selectively belong to a first metal layer, and the via line GL may selectively belong to a second metal layer. However, the present invention is not limited thereto, and in other embodiments, the patch cord gl may include a plurality of portions respectively belonging to the first metal layer and the second metal layer.

Referring to fig. 2, 3 and 4, the plurality of pixel structures 120 includes a first pixel structure 120-1, the plurality of data lines DL includes a first data line DL1 electrically connected to the first pixel structure 120-1, and the plurality of patch cords gl includes a first patch cord gl 1. The first data line DL1 has a first portion DLa disposed outside the pixel electrode 122 of the first pixel structure 120-1 and beside the active device 121 of the first pixel structure 120-1.

The active device 121 of each pixel structure 120 has a first side (such as but not limited to a left side) and a second side (such as but not limited to a right side) opposite to each other. It is noted that, in the top view of the pixel array substrate 100, the active device 121 of the first pixel structure 120-1 has a first side (for example, but not limited to, a left side) and a second side (for example, but not limited to, a right side), the first transfer line gl1 is disposed on the first side (for example, but not limited to, the left side) of the active device 121 of the first pixel structure 120-1, and the first portion DLa of the first data line DL1 and the common line CL are disposed on the second side (for example, but not limited to, the right side) of the active device 121 of the first pixel structure 120-1. In other words, when the switching line gl and the common line CL are disposed on two opposite sides of a pixel structure 120, respectively, a portion (i.e., the first portion DLa) of the data line DL bypassing the active device 121 is disposed closer to the common line CL and farther from the switching line gl. Therefore, the coupling capacitance between the data line DL and the switching line gl can be reduced, the influence of the signal change of the switching line gl on the potential of the pixel electrode 122 can be reduced, and the display quality can be improved.

Referring to fig. 2, in the top view of the pixel array substrate 100, the first portion DLa of the first data line DL1 and the first transition line gl1 have a first distance D1 in the first direction x, the first portion DLa of the first data line DL1 and the common line CL have a second distance D2 in the first direction x, and the first distance D1 is greater than the second distance D2.

Referring to fig. 2, in the present embodiment, the plurality of pixel structures 120 further includes a second pixel structure 120-2, and the first pixel structure 120-1 and the second pixel structure 120-2 are disposed adjacent to each other and arranged in the first direction x; the plurality of data lines DL further includes a second data line DL2 electrically connected to the second pixel structure 120-2; the plurality of patch cords gl further include a second patch cord gl 2; the second data line DL2 has a first portion DLa disposed outside the pixel electrode 122 of the second pixel structure 120-2 and beside the active device 121 of the second pixel structure 120-2.

In a top view of the pixel array substrate 100, the active device 121 of the second pixel structure 120-2 has a first side (for example, but not limited to, a left side) and a second side (for example, but not limited to, a right side), the first portion DLa of the common line CL and the second data line DL2 is disposed on the first side (for example, but not limited to, the left side) of the active device 121 of the second pixel structure 120-2, and the second patch line gl2 is disposed on the second side (for example, but not limited to, the right side) of the active device 121 of the second pixel structure 120-2. In other words, when the common line CL and the transfer line gl are disposed on two opposite sides of the pixel structure 120, respectively, a portion (i.e., the first portion DLa) of the data line DL bypassing the active device 121 is disposed closer to the common line CL and farther from the transfer line gl. Therefore, the coupling capacitance between the data line DL and the switching line gl can be reduced, the influence of the signal change of the switching line gl on the potential of the pixel electrode 122 can be reduced, and the display quality can be improved.

In the top view of the pixel array substrate 100, the first portion DLa of the second data line DL2 has a third distance D3 with the common line CL in the first direction x, the first portion DLa of the second data line DL2 has a fourth distance D4 with the second transfer line gl2 in the first direction x, and the fourth distance D4 is greater than the third distance D3.

Referring to fig. 2, in the present embodiment, the plurality of pixel structures 120 further includes a third pixel structure 120-3, and the first pixel structure 120-1, the second pixel structure 120-2 and the third pixel structure 120-3 are sequentially arranged in the first direction x; there are no other pixel structures 120 between the first pixel structure 120-1, the second pixel structure 120-2, and the third pixel structure 120-3; the plurality of data lines DL further includes a third data line DL3 electrically connected to the third pixel structure 120-3; the plurality of patch cords gl further include a third patch cord gl 3; the third data line DL3 has a first portion DLa disposed outside the pixel electrode 122 of the third pixel structure 120-3 and beside the active device 121 of the third pixel structure 120-3.

In a top view of the pixel array substrate 100, the active device 121 of the third pixel structure 120-3 has a first side (for example, but not limited to, a left side) and a second side (for example, but not limited to, a right side) opposite to each other, the second patch cord gl2 and the first portion DLa of the third data line DL3 are disposed on the first side (for example, but not limited to, the left side) of the active device 121 of the third pixel structure 120-3, and the third patch cord gl3 is disposed on the second side (for example, but not limited to, the right side) of the active device 121 of the third pixel structure 120-3. When the patch lines gl are disposed on two opposite sides of a pixel structure 120, a portion of the data line DL (i.e., the first portion DLa) bypassing the active device 121 can be arbitrarily disposed closer to one of the patch lines gl.

In the present embodiment, the third pixel structure 120-3 is used for displaying blue. In other words, the pixel structure 120 having the transfer line gl on two opposite sides is preferably used for displaying blue. Therefore, the adverse effect of the transfer line gl on the display quality can be reduced. In addition, in the embodiment, the first pixel structure 120-1 and the second pixel structure 120-2 are for displaying red and green, respectively, for example, but the invention is not limited thereto.

Referring to fig. 2, fig. 4 and fig. 5, in the present embodiment, the pixel array substrate 100 further includes a transparent conductive layer 150, wherein the data line DL, the transparent conductive layer 150 and the pixel electrode 122 of the pixel structure 120 are stacked in a third direction z perpendicular to the substrate 110, and the transparent conductive layer 150 is disposed between the data line DL and the pixel electrode 122 of the pixel structure 120. In addition, in the present embodiment, the common line CL, the transparent conductive layer 150 and the pixel electrode 122 of the pixel structure 120 are stacked in the third direction z perpendicular to the substrate 110, and the transparent conductive layer 150 is disposed between the common line CL and the pixel electrode 122 of the pixel structure 120.

In brief, in the present embodiment, the transparent conductive layer 150 is disposed between the film layer to which the pixel electrode 122 belongs and the second metal layer to cause a shielding effect on the components of the second metal layer (such as, but not limited to, the patch line gl); therefore, the adverse effect of the signal of the second metal layer (such as but not limited to the bonding wire gl) on the pixel electrode 122 can be reduced, thereby improving the display quality.

In the present embodiment, the potential of the transparent conductive layer 150 and the potential of the common line CL can be substantially equal. In the present embodiment, the opposite substrate 200 may selectively include a common electrode 220 (shown in fig. 5) disposed on the base 210 in addition to the base 210, the common electrode 220 overlaps the plurality of pixel electrodes 122 of the plurality of pixel structures 120, the display medium 300 is disposed between the common electrode 220 and the plurality of pixel electrodes 122, and a potential difference between the common electrode 220 and each pixel electrode 122 may be used to drive the display medium 300, so that the display apparatus 10 can display a picture. In the embodiment, the potential of the transparent conductive layer 150 of the pixel array substrate 100 and the potential of the common electrode 220 of the opposite substrate 200 may be substantially equal, but the invention is not limited thereto.

In the present embodiment, the pixel array substrate 100 may optionally further include a color filter pattern layer 160 (shown in fig. 5), wherein the color filter pattern layer 160 is disposed on the insulating layer 140, and the transparent conductive layer 150 is disposed on the color filter pattern layer 160; the pixel array substrate 100 further includes an insulating layer 170, the insulating layer 170 is disposed on the transparent conductive layer 150, and the pixel electrode 122 is disposed on the insulating layer 170.

Referring to fig. 2 and fig. 4, it is noted that in the present embodiment, the transparent conductive layer 150 may have a plurality of openings 152 overlapping the pixel electrodes 122 of the pixel structures 120. The openings 152 of the transparent conductive layer 150 help to reduce interference of the transparent conductive layer 150 with an electric field formed by the pixel electrode 122, thereby increasing liquid crystal efficiency and improving transmittance of the display device 10.

In the present embodiment, the transparent conductive layer 150 has a first solid portion 151 overlapping the data line DL; in a top view of the pixel array substrate 100, the first solid portion 151 of the transparent conductive layer 150 has an edge 151e defining the plurality of openings 152, and the edge 151e of the first solid portion 151 of the transparent conductive layer 150 is located outside the data line DL. In other words, although the transparent conductive layer 150 has the plurality of openings 152, the first solid portion 151 of the transparent conductive layer 150 still well shields the second portion DLb where the data line DL overlaps the pixel electrode 122.

For example, in the embodiment, in the top view of the pixel array substrate 100, the edge 151e of the first solid portion 151 of the transparent conductive layer 150 has a minimum distance W with the edge DLe of the data line DL, and the minimum distance W is greater than or equal to 5 μm and less than or equal to 8 μm, but the invention is not limited thereto.

Referring to fig. 2, fig. 3 and fig. 4, in the embodiment, in the top view of the pixel array substrate 100, the plurality of slits 122s of the pixel electrode 122 are disposed in the first range RG1, the plurality of openings 152 of the transparent conductive layer 150 are disposed in the second range RG2, the first range RG1 and the second range RG2 overlap, and the area of the second range RG2 is smaller than the area of the first range RG 1.

In the present embodiment, the pixel electrode 122 of the pixel structure 120 has a plurality of first branch portions 122c, the plurality of first branch portions 122c are spaced apart from each other to define a plurality of slits 122S, a first branch portion 122c has a first line width L1, and two adjacent first branch portions 122c have a first distance S1; the transparent conductive layer 150 has a plurality of second branches 153, the plurality of second branches 153 are spaced apart from each other to define a plurality of openings 152, a second branch 153 has a second line width L2, two adjacent branches 153 of the plurality of second branches 153 have a second spacing S2; the sum of the second line width L2 and the second interval S2 of the transparent conductive layer 150 is greater than the sum of the first line width L1 and the first interval S1 of the pixel electrode 122.

In the present embodiment, in the top view of the pixel array substrate 100, the openings 152 of the transparent conductive layer 150 are located at two opposite sides of the data line DL. In the present embodiment, the plurality of slits 122s of the pixel electrode 122 include a plurality of slits 122s-1, a plurality of slits 122s-2, a plurality of slits 122s-3, and a plurality of slits 122s-4, which are respectively disposed in the plurality of alignment regions R partitioned by the first trunk portion 122a and the second trunk portion 122b of the pixel electrode 122; the plurality of openings 152 of the transparent conductive layer 150 may include a plurality of openings 152-1, a plurality of openings 152-2, a plurality of openings 152-3, and a plurality of openings 152-4, which are respectively overlapped with the plurality of slits 122s-1, the plurality of slits 122s-2, the plurality of slits 122s-3, and the plurality of slits 122s-4 of the pixel electrode 122.

In the present embodiment, the plurality of openings 152-1, 152-2, 152-3, or 152-4 of the transparent conductive layer 150 may be arranged in the first direction x. In the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 may extend in the second direction y. In other words, in the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 may be straight openings. However, the present invention is not limited thereto, and in other embodiments, the plurality of openings 152 may have other shapes and/or be arranged in other manners, and will be described in conjunction with other figures.

It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, which will not be repeated below.

The pixel array substrate 100A of fig. 6 is similar to the pixel array substrate 100 of fig. 2, and the difference therebetween is: in the embodiment of FIG. 2, the first portion DLa of the third data line DL3 is disposed on a first side (e.g., but not limited to, the left side) of the active device 121 of the third pixel structure 120-3; however, in the embodiment of fig. 6, the first portion DLa of the third data line DL3 is disposed on a second side (e.g., but not limited to, the right side) of the active device 121 of the third pixel structure 120-3.

Fig. 8 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the invention. Fig. 8 omits the transparent conductive layer 150 of fig. 7.

Fig. 9 is a schematic top view of a region of a pixel array substrate 100B according to an embodiment of the invention. Fig. 9 omits the pixel electrode 122 of fig. 7.

The pixel array substrate 100B of fig. 7 to 9 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference therebetween is: the openings 152 of the transparent conductive layer 150 are different between the two.

Referring to fig. 7 to 9, in the present embodiment, specifically, the openings 152 of the transparent conductive layer 150 are arranged in the second direction y. Each opening 152 of the transparent conductive layer 150 may extend in the first direction x. In other words, in the present embodiment, the plurality of openings 152 of the transparent conductive layer 150 may be a plurality of lateral openings.

Fig. 11 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention. Fig. 11 omits the transparent conductive layer 150 of fig. 10.

Fig. 12 is a schematic top view of a region of a pixel array substrate 100C according to an embodiment of the invention. Fig. 12 omits the pixel electrode 122 of fig. 10.

The pixel array substrate 100C of fig. 10 to 12 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference therebetween is: the openings 152 of the transparent conductive layer 150 are different between the two.

Referring to fig. 10 to 12, in the present embodiment, the transparent conductive layer 150 has a plurality of second branch portions 153C-1 and 153C-2, which are interlaced with each other to form a mesh shape, so as to define a plurality of openings 152 (shown in fig. 12). Furthermore, in the present embodiment, the plurality of second branch portions 153C-1 and 153C-2 may include a plurality of second branch portions 153C-1 and a plurality of second branch portions 153C-2 interlaced with each other, wherein the plurality of second branch portions 153C-1 may be selectively parallel to the second portion DLb of the data line DL, and the plurality of second branch portions 153C-1 may be selectively perpendicular to the second portion DLb of the data line DL.

Fig. 14 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention. Fig. 14 omits the transparent conductive layer 150 of fig. 13.

Fig. 15 is a schematic top view of a region of a pixel array substrate 100D according to an embodiment of the invention. Fig. 15 omits the pixel electrode 122 of fig. 13.

The pixel array substrate 100D of fig. 13 to 15 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference therebetween is: the openings 152 of the transparent conductive layer 150 are different between the two.

Referring to fig. 13 to 15, in the present embodiment, a plurality of data lines DL are arranged in a first direction x, a plurality of gate lines GL are arranged in a second direction y, a plurality of openings 152 of the transparent conductive layer 150 are arranged in a fourth direction d4, and the first direction x, the second direction y and the fourth direction d4 are different from each other.

Furthermore, in the present embodiment, the pixel electrode 122 of the pixel structure 120 has a plurality of slits 122s, the plurality of slits 122s of the pixel electrode 122 overlap the plurality of openings 152 of the transparent conductive layer 150, the plurality of slits 122s of the pixel electrode 122 are arranged in the fifth direction d5, the plurality of openings 152 of the transparent conductive layer 150 are arranged in the fourth direction d4, and the fourth direction d4 is substantially the same as the fifth direction d 5.

Fig. 17 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention. Fig. 17 omits the transparent conductive layer 150 of fig. 16.

Fig. 18 is a schematic top view of a region of a pixel array substrate 100E according to an embodiment of the invention. Fig. 18 omits the pixel electrode 122 of fig. 16.

The pixel array substrate 100E of fig. 16 to 18 is similar to the pixel array substrate 100D of fig. 13 to 15, and the main difference therebetween is that: the openings 152 of the transparent conductive layer 150 are different between the two.

Referring to fig. 16 to 18, in the present embodiment, specifically, the plurality of slits 122s of the pixel electrode 122 are arranged in the fifth direction d5, the plurality of openings 152 of the transparent conductive layer 150 are arranged in the fourth direction d4, and the fourth direction d4 and the fifth direction d5 form an angle θ, where 0 ° < θ ≦ 90 °.

Fig. 20 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention. Fig. 20 omits the transparent conductive layer 150 of fig. 19.

Fig. 21 is a schematic top view of a region of a pixel array substrate 100F according to an embodiment of the invention. Fig. 21 omits the pixel electrode 122 of fig. 19.

The pixel array substrate 100F of fig. 19 to 21 is similar to the pixel array substrate 100 of fig. 10 to 12, and the main difference therebetween is: the openings 152 of the transparent conductive layer 150 are different between the two.

Referring to fig. 19 to 21, similarly, in the present embodiment, the transparent conductive layer 150 has a plurality of second branch portions 153C-1 and 153C-2 (shown in fig. 21) interlaced with each other to form a mesh shape to define a plurality of openings 152; the plurality of second branch portions 153C-1 and 153C-2 of the transparent conductive layer 150 may include a plurality of second branch portions 153C-1 and a plurality of second branch portions 153C-2 that are staggered with each other. Unlike the embodiment of fig. 10 to 12, in the present embodiment, the plurality of second branch portions 153C-1 are not parallel to and not perpendicular to the second portion DLb of the data line DL, and the plurality of second branch portions 153C-1 are not parallel to and not perpendicular to the second portion DLb of the data line DL. In brief, in the embodiment, the plurality of second branch portions 153C-1 and 153C-2 of the transparent conductive layer 150 can be interwoven into a mesh pattern disposed obliquely.

Fig. 23 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention. Fig. 23 omits the transparent conductive layer 150 of fig. 22.

Fig. 24 is a schematic top view of a region of a pixel array substrate 100G according to an embodiment of the invention. Fig. 24 omits the pixel electrode 122 of fig. 22.

The pixel array substrate 100G of fig. 22 to 24 is similar to the pixel array substrate 100 of fig. 2 to 4, and the main difference therebetween is: the openings 152 of the transparent conductive layer 150 are different between the two.

Referring to fig. 22 to 24, in the present embodiment, the transparent conductive layer 150 does not have the opening 152 of the pixel array substrate 100, and the entity of the transparent conductive layer 150 may overlap the pixel electrode 122.

Fig. 25 is a schematic top view of a region of a pixel array substrate 100H according to an embodiment of the invention. The pixel array substrate 100H of fig. 25 is similar to the pixel array substrate 100 of fig. 2, and the main differences between the two will be described below, and reference is made to the foregoing description for the same or similar points, so that the description is not repeated here.

Referring to fig. 25, in the present embodiment, the plurality of pixel structures 120 further includes a fourth pixel structure 120-4; the first pixel structure 120-1 and the fourth pixel structure 120-4 are respectively disposed on two opposite sides of the first junction line gl 1; the plurality of data lines DL further includes a fourth data line DL4 electrically connected to the fourth pixel structure 120-4; the fourth data line DL4 has a first portion DLa disposed outside the pixel electrode 122 of the fourth pixel structure 120-4 and beside the active device 121 of the fourth pixel structure 120-4. In particular, in the top view of the pixel array substrate 100H, the first portion DLa of the first data line DL1 is disposed on the second side (for example, but not limited to, the right side) of the active device 121 of the first pixel structure 120-1, and the first portion DLa of the fourth data line DL4 is disposed on the first side (for example, but not limited to, the right side) of the active device 121 of the fourth pixel structure 120-4. That is to say, in the present embodiment, two pixel structures 120 are adjacent to the same patch cord gl and located at two opposite sides of the same patch cord gl respectively, and two first portions DLa of two data lines DL electrically connected to the two pixel structures 120 respectively are both disposed at positions far away from the patch cord gl.

Referring to fig. 25, in the present embodiment, the first pixel structure 120-1 and the fourth pixel structure 120-4 are respectively used for displaying red and blue. That is, in the top view of the pixel array substrate 100, a transfer line gl is disposed between the pixel structures 120 for displaying red and blue colors, respectively.

Referring to fig. 25, in the present embodiment, the plurality of pixel structures 120 further includes a fifth pixel structure 120-5, a sixth pixel structure 120-6, a seventh pixel structure 120-7 and an eighth pixel structure 120-8. The seventh pixel structure 120-7, the eighth pixel structure 120-8, the fourth pixel structure 120-4, the first pixel structure 120-1, the fifth pixel structure 120-5, and the sixth pixel structure 120-6 are sequentially arranged in the first direction x. The seventh pixel structure 120-7, the eighth pixel structure 120-8, the fourth pixel structure 120-4, the first pixel structure 120-1, the fifth pixel structure 120-5 and the sixth pixel structure 120-6 are respectively used for displaying red, green, blue, red, green and blue. The plurality of data lines DL further includes a fifth data line DL5 electrically connected to the fifth pixel structure 120-5. The fifth data line DL5 has a first portion DLa disposed outside the pixel electrode 122 of the fifth pixel structure 120-5 and beside the active device 121 of the fifth pixel structure 120-5. The plurality of data lines DL further includes a sixth data line DL6 electrically connected to the sixth pixel structure 120-6. The sixth data line DL6 has a first portion DLa disposed outside the pixel electrode 122 of the sixth pixel structure 120-6 and beside the active device 121 of the sixth pixel structure 120-6.

In particular, in the top view of the pixel array substrate 100H, the first portion DLa of the fifth data line DL5 is disposed on the second side (for example, but not limited to, the right side) of the active device 121 of the fifth pixel structure 120-5, and the first portion DLa of the sixth data line DL6 is disposed on the first side (for example, but not limited to, the left side) of the active device 121 of the sixth pixel structure 120-6. That is, the two first portions DLa of the two data lines DL electrically connected to the two pixel structures 120 for displaying green and blue colors are disposed adjacent to each other.

Fig. 26 is a schematic top view of a region of a pixel array substrate 100I according to an embodiment of the invention. The pixel array substrate 100I of fig. 26 is similar to the pixel array substrate 100H of fig. 25, and the difference therebetween is that: in the top view of the pixel array substrate 100I of fig. 26, the first portion DLa of the first data line DL1 is disposed on the second side (for example, but not limited to, the right side) of the active device 121 of the first pixel structure 120-1, and the first portion DLa of the fifth data line DL5 is disposed on the first side (for example, but not limited to, the left side) of the active device 121 of the fifth pixel structure 120-5. That is, in the embodiment of fig. 26, the two first portions DLa of the two data lines DL electrically connected to the two pixel structures 120 for displaying red and green colors are disposed adjacent to each other.

Fig. 27 is a schematic top view of a region of a pixel array substrate 100J according to an embodiment of the invention. The pixel array substrate 100J of fig. 27 is similar to the pixel array substrate 100 of fig. 2, and the main differences between the two will be described below, and reference is made to the foregoing description for the same or similar points, so that the description is not repeated here.

Referring to fig. 27, in the present embodiment, the first pixel structure 120-1 and the second pixel structure 120-2 are respectively disposed on two opposite sides of the first transfer line gl 1. The plurality of data lines DL includes a first data line DL1 and a second data line DL2 electrically connected to the first pixel structure 120-1 and the second pixel structure 120-2, respectively. The first data line DL1 has a first portion DLa disposed outside the pixel electrode 122 of the first pixel structure 120-1 and beside the active device 121 of the first pixel structure 120-1. The second data line DL2 has a first portion DLa disposed outside the pixel electrode 122 of the second pixel structure 120-2 and beside the active device 121 of the second pixel structure 120-2.

In particular, in the top view of the pixel array substrate 100J, the first transfer line gl1 is disposed on a first side (for example, but not limited to, the left side) of the active device 121 of the first pixel structure 120-1, the first portion DLa of the first data line DL1 is disposed on a second side (for example, but not limited to, the right side) of the active device 121 of the first pixel structure 120-1, the first transfer line gl1 is disposed on a second side (for example, but not limited to, the right side) of the active device 121 of the second pixel structure 120-2, and the first portion DLa of the second data line DL2 is disposed on a first side (for example, but not limited to, the left side) of the active device 121 of the second pixel structure 120-2. That is, in the present embodiment, two pixel structures 120 are adjacent to the same patch cord g1 and located on two opposite sides of the same patch cord g1, and two first portions DLa of two data lines DL electrically connected to the two pixel structures 120 are disposed far away from the patch cord gl.

Referring to fig. 27, in the present embodiment, the plurality of pixel structures 120 further includes a ninth pixel structure 120-9, a tenth pixel structure 120-10, an eleventh pixel structure 120-11, and a twelfth pixel structure 120-12. The eleventh pixel structure 120-11, the twelfth pixel structure 120-12, the second pixel structure 120-2, the first pixel structure 120-1, the ninth pixel structure 120-9, and the tenth pixel structure 120-10 are sequentially arranged in the first direction x. The eleventh pixel structure 120-11, the twelfth pixel structure 120-12, the second pixel structure 120-2, the first pixel structure 120-1, the ninth pixel structure 120-9 and the tenth pixel structure 120-10 can be respectively used for displaying red, green, blue, red, green and blue.

In addition, the pixel array substrate 100J of fig. 27 does not include the common line CL of the pixel array substrate 100 of fig. 2, but includes the common electrode CL'. Referring to fig. 27, in the present embodiment, the common electrode CL 'includes at least one first portion CL' -1, the at least one first portion CL '-1 of the common electrode CL' is aligned with the gate line GL in the second direction y, and the at least one first portion CL '-1 of the common electrode CL' partially overlaps the pixel electrode 122. In the present embodiment, the common electrode CL 'further includes at least one second portion CL' -2, the at least one second portion CL '-2 of the common electrode CL' is aligned with the data line DL in the first direction x, and the at least one second portion CL '-2 of the common electrode CL' partially overlaps the pixel electrode 122. Furthermore, the pixel array substrate 100J of fig. 27 may not include the transparent conductive layer 150 of the pixel array substrate 100 of fig. 2.

Claims

1. A pixel array substrate, comprising:

a substrate;

2. The pixel array substrate of claim 1, wherein in a top view of the pixel array substrate, the first portion of the first data line and the first transfer line have a first distance in the first direction, the first portion of the first data line and the common line have a second distance in the first direction, and the first distance is greater than the second distance.

3. The pixel array substrate of claim 1, wherein the pixel structures further comprise a second pixel structure, the first pixel structure and the second pixel structure being disposed adjacent to each other and arranged in the first direction; the data lines further comprise a second data line electrically connected to the second pixel structure; the patch cords also comprise a second patch cord; the second data line is provided with a first part, is arranged outside the pixel electrode of the second pixel structure and is positioned beside the active element of the second pixel structure; in a top view of the pixel array substrate, the first portions of the common line and the second data line are disposed on the first side of the active device of the second pixel structure, and the second patch line is disposed on the second side of the active device of the second pixel structure.

4. The pixel array substrate of claim 3, wherein in a top view of the pixel array substrate, the first portion of the second data line and the common line have a third distance in the first direction, the first portion of the second data line and the second transfer line have a fourth distance in the first direction, and the fourth distance is greater than the third distance.

5. The pixel array substrate of claim 3, wherein the pixel structures further comprise a third pixel structure, the first pixel structure, the second pixel structure, and the third pixel structure being sequentially arranged in the first direction; the data lines further comprise a third data line electrically connected to the third pixel structure; the patch cords also comprise a third patch cord; the third data line has a first portion disposed outside the pixel electrode of the third pixel structure and beside the active device of the third pixel structure;

6. The pixel array substrate of claim 1, further comprising:

7. The pixel array substrate of claim 6, wherein the openings of the transparent conductive layer are located on opposite sides of the data line in a top view of the pixel array substrate.

8. The pixel array substrate of claim 6, wherein the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in the third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

9. The pixel array substrate of claim 6, wherein the pixel electrode of the pixel structure has a plurality of slits overlapping the openings of the transparent conductive layer.

10. The pixel array substrate of claim 9, wherein in a top view of the pixel array substrate, the slits of the pixel electrode are disposed in a first area, the openings of the transparent conductive layer are disposed in a second area, the first area and the second area overlap, and an area of the second area is smaller than an area of the first area.

11. The pixel array substrate of claim 9, wherein the pixel electrode of the pixel structure has a plurality of first branch portions spaced apart from each other to define the slits, one first branch portion having a first line width, two adjacent first branch portions having a first pitch; the transparent conductive layer is provided with a plurality of second branch parts which are separated from each other to define the openings, one second branch part is provided with a second line width, and two adjacent second branch parts are provided with a second interval; the sum of the second line width and the second interval of the transparent conducting layer is larger than the sum of the first line width and the first interval of the pixel electrode.

12. The pixel array substrate of claim 6, wherein the transparent conductive layer has a first solid portion overlapping the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining the openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line.

13. The pixel array substrate of claim 1, wherein the pixel structures further comprise a fourth pixel structure; the first pixel structure and the fourth pixel structure are respectively arranged at two opposite sides of the first transfer line; the data lines further comprise a fourth data line electrically connected to the fourth pixel structure; the fourth data line has a first portion disposed outside the pixel electrode of the fourth pixel structure and beside the active device of the fourth pixel structure; in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fourth data line is disposed on the first side of the active device of the fourth pixel structure.

14. The pixel array substrate of claim 13, wherein the first pixel structure and the fourth pixel structure are configured to display red and blue colors, respectively.

15. The pixel array substrate of claim 13, wherein the pixel structures further comprise a fifth pixel structure and a sixth pixel structure, the fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure being sequentially arranged in the first direction; the fourth pixel structure, the first pixel structure, the fifth pixel structure and the sixth pixel structure are respectively used for displaying blue, red, green and blue; the data lines further comprise a fifth data line electrically connected to the fifth pixel structure; the fifth data line has a first portion disposed outside the pixel electrode of the fifth pixel structure and beside the active device of the fifth pixel structure; the data lines further comprise a sixth data line electrically connected to the sixth pixel structure; the sixth data line has a first portion disposed outside the pixel electrode of the sixth pixel structure and beside the active device of the sixth pixel structure; in a top view of the pixel array substrate, the first portion of the fifth data line is disposed on the second side of the active device of the fifth pixel structure, and the first portion of the sixth data line is disposed on the first side of the active device of the sixth pixel structure.

16. The pixel array substrate of claim 13, wherein the pixel structures further comprise a fifth pixel structure, the fourth pixel structure, the first pixel structure, and the fifth pixel structure being sequentially arranged in the first direction; the fourth pixel structure, the first pixel structure and the fifth pixel structure are respectively used for displaying blue, red and green; the data lines further comprise a fifth data line electrically connected to the fifth pixel structure; the fifth data line has a first portion disposed outside the pixel electrode of the fifth pixel structure and beside the active device of the sixth pixel structure; in a top view of the pixel array substrate, the first portion of the first data line is disposed on the second side of the active device of the first pixel structure, and the first portion of the fifth data line is disposed on the first side of the active device of the fifth pixel structure.

17. A pixel array substrate, comprising:

a substrate;

18. A pixel array substrate, comprising:

a substrate;

19. The pixel array substrate of claim 18, wherein the common line, the transparent conductive layer and the pixel electrode of the pixel structure are stacked in the third direction perpendicular to the substrate, and the transparent conductive layer is disposed between the common line and the pixel electrode of the pixel structure.

20. The pixel array substrate of claim 18, wherein the pixel electrode of the pixel structure has a plurality of slits overlapping the openings of the transparent conductive layer.

21. The pixel array substrate of claim 20, wherein in a top view of the pixel array substrate, the slits of the pixel electrode are disposed in a first area, the openings of the transparent conductive layer are disposed in a second area, the first area and the second area overlap, and an area of the second area is smaller than an area of the first area.

22. The pixel array substrate of claim 20, wherein the pixel electrode of the pixel structure has a plurality of first branch portions spaced apart from each other to define the slits, one first branch portion having a first line width, two adjacent first branch portions having a first pitch; the transparent conductive layer is provided with a plurality of second branch parts which are separated from each other to define the openings, one second branch part is provided with a second line width, and two adjacent second branch parts are provided with a second interval; the sum of the second line width and the second interval of the transparent conducting layer is larger than the sum of the first line width and the first interval of the pixel electrode.

23. The pixel array substrate of claim 18, wherein the transparent conductive layer has a first solid portion overlapping the data line; in a top view of the pixel array substrate, the first solid portion of the transparent conductive layer has an edge defining the openings, and the edge of the first solid portion of the transparent conductive layer is located outside the data line.

24. The pixel array substrate of claim 18, wherein the openings of the transparent conductive layer are arranged in a fourth direction, and the first direction, the second direction and the fourth direction are different from each other.

25. The pixel array substrate of claim 18, wherein the pixel electrode of the pixel structure has a plurality of slits overlapping the openings of the transparent conductive layer; the slits are arranged in a fifth direction; the fourth direction and the fifth direction form an angle theta, and the angle theta is more than 0 degree and less than or equal to 90 degrees.