KR20130010774A - Manufacturing method of thin film transisotr array substrate - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film transistor array substrate is provided to simplify a manufacturing process by simultaneously etching an amorphous silicon layer and a metal layer of a channel part in a thin film transistor. CONSTITUTION: A gate line and a gate electrode(102) are formed on an insulation substrate(101). A gate insulation layer(103) is formed on the insulation substrate and the gate electrode. A semiconductor layer(104) is formed on the gate insulation layer. A source electrode(106) and a drain electrode(108) are formed on the semiconductor layer. A protection layer(105) is formed on the source electrode and the drain electrode. A pixel electrode(120) made of reflective conductive materials is formed on the protection layer.

Description

Manufacturing method of thin film transistor array substrate {MANUFACTURING METHOD OF THIN FILM TRANSISOTR ARRAY SUBSTRATE}

The present invention relates to a method of manufacturing a thin film transistor array substrate, and to a method of manufacturing a thin film transistor array substrate that can simplify the process.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the highest resolution and video performance. I am getting it.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the cell process through liquid crystal in the process.

The manufacturing method of the array substrate is as follows.

After depositing the first metal material on the substrate, the gate wiring extending in one direction and the gate electrode connected to the gate wiring are formed by performing the first mask process.

A gate insulating layer, an amorphous silicon material layer, an impurity amorphous material layer, and a second metal material layer are sequentially formed on the substrate on which the gate wiring and the gate electrode are formed.

Next, a photoresist is applied onto the second metal material layer and patterned to form a photoresist pattern. In the first wet etching process using an etchant, the second metal material layer exposed to the outside of the photoresist pattern is etched to form a data line and a source / drain pattern.

Dry etching the substrate on which the data line and the source / drain pattern are formed to remove the impurity amorphous silicon layer exposed to the outside of the photoresist pattern and the pure amorphous silicon layer below the active layer, and an upper portion thereof. To form an ohmic contact layer connected to each other.

Ashing is performed to remove the photoresist pattern to expose a portion of the source / drain pattern.

A second wet etching process is performed on the exposed source / drain pattern through exposure to an etchant to form source and drain electrodes.

The source and drain electrodes are formed to dry-etch and remove the newly exposed ohmic contact pattern to form an ohmic contact layer spaced apart from each other under the source and drain electrodes.

Next, the remaining photoresist pattern is stripped and removed, a protective layer having a drain contact hole exposing the drain electrode is formed, and then the pixel is connected to the drain electrode through the drain contact hole. The array substrate is completed by forming the electrode.

In the case of the array substrate having such a configuration, two wet etching processes and two dry etching processes are performed to form the source and drain electrodes and the ohmic contact layer.

In particular, during the dry etching process, the static electricity is generated in the upper and lower electrodes and the etching mechanism in the process equipment, and the static electricity may cause a defect in which the overlap between the gate electrode and the source / drain electrode formed on the substrate is shorted. do.

Due to this defect, the reliability of the product is lowered, and the manufacturing process time is increased due to two wet etching processes and two dry etching processes.

An object of the present invention is to provide a method of manufacturing a thin film transistor array substrate that can simplify the manufacturing process and improve the reliability of the product by simultaneously etching the channel portion metal layer and the impurity amorphous silicon layer of the thin film transistor.

A method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention includes the steps of forming a gate line extending in one direction and a gate electrode connected to the gate line on the substrate, the gate insulating film and the pure amorphous on the entire surface above the gate electrode Sequentially forming a silicon layer, an impurity amorphous silicon layer and a first metal layer, forming first and second photoresist patterns over the first metal layer, and out of the first and second photoresist patterns Performing a first wet etching process on the exposed first metal layer to form a data line and a source drain pattern, and performing ashing to expose the data line and a portion of the source drain pattern to the outside; The dry etching is performed on the pure amorphous silicon layer and the impurity amorphous silicon layer to Forming a completely overlapping ohmic contact pattern and an active layer having the same shape and area under the lane pattern, and removing the source drain pattern exposed to the outside using a fluorine etchant to form source and drain electrodes spaced apart from each other; And simultaneously removing the ohmic contact pattern under the source drain pattern to form an ohmic contact layer and exposing the active layer under the source to the outside.

In the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention, the channel part metal layer and the impurity amorphous silicon layer of the thin film transistor may be simultaneously etched using an etching solution having an increased content of fluorine compound to simplify the manufacturing process.

In addition, the manufacturing method of the thin film transistor array substrate according to the embodiment of the present invention can reduce the number of dry etching to minimize the short failure caused by static electricity generated in the dry etching process to improve the reliability of the product.

1 is a schematic plan view of a thin film transistor array substrate according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.
3A to 3I are diagrams sequentially illustrating a manufacturing process of the thin film transistor array substrate of FIG. 1.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic plan view of a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

The thin film transistor array substrate according to the embodiment of the present invention includes a thin film transistor formed on an insulating substrate and a protective film covering the thin film transistor. The thin film transistor includes a gate electrode, a source and a drain electrode, and a semiconductor layer. The gate electrode forms the control terminal of the thin film transistor, the source electrode forms the input terminal of the thin film transistor, the drain electrode forms the output terminal of the thin film transistor, and the semiconductor layer forms a channel region of the thin film transistor.

1 and 2, the thin film transistor array substrate 100 according to the embodiment of the present invention will be described in more detail. The insulating substrate 101 supports the thin film transistor TFT, for example, transparent glass or It is made of plastic.

The gate line GL, the gate pad lower electrode 130, and the gate electrode 102 are formed on the insulating substrate 101.

A plurality of gate lines GL is provided on the insulating substrate 101. Each gate line GL may be spaced apart from each other, and may extend in parallel in a first direction, such as the horizontal direction of FIG. 1. Alternatively, although not shown, they may extend in parallel in the vertical direction.

One end of each gate line GL has a gate pad lower electrode 130a extending in width.

The gate electrode 102 is connected to the gate line GL.

A plurality of gate electrodes 102 may be connected to one gate line GL. Each gate electrode 102 may be formed to extend from the gate line GL.

Although not shown, the gate electrode 102 may be formed to be separated from the gate line GL, and the gate electrode 102 and the gate line GL may be electrically connected through separate contact holes.

In the present specification, the gate electrode 102, the gate line GL, and the gate pad lower electrode 130 are sometimes referred to collectively as 'gate wiring' for convenience of description.

In addition, a storage electrode (not shown) made of the same material as the gate wires 102, GL and 130a may be formed on the insulating substrate 101.

The gate wirings 102, GL, and 130a may be formed of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and ITO (Indium-). Tin-Oxide), IZO (Indium-Zinc-Oxide), or a single film made of an alloy thereof, or the like, or a multi-film consisting of a combination thereof, the present invention is not limited to the above examples.

The gate lines 102, GL, and 130a may be formed of silicon nitride (SiNx) or the like except for a region in which the gate contact portion H1 is formed in which the gate pad lower electrode 130a contacts the gate pad upper electrode 130b. It may be covered by the gate insulating film 103.

The gate insulating layer 103 may include a silicon nitride layer or a silicon oxide layer. The gate insulating layer 103 may be formed in multiple layers such as a silicon nitride film covering the gate wirings 102, GL, and 130a as well as a silicon oxide film structure formed on the silicon nitride film.

An active layer 104a made of hydrogenated amorphous silicon and the like and an ohmic contact layer 104b made of n + hydrogenated amorphous silicon and the like doped with n-type impurities may be formed on the gate insulating layer 103.

The active layer 104a and the ohmic contact layer 104b constitute a semiconductor layer 104.

The semiconductor layer 104 may be formed in substantially the same pattern as the data line described later except for the channel region. The channel region of the thin film transistor TFT is formed by the active layer 104a overlapping the gate electrode 102.

The data line DL, the data pad lower electrode 140a, the source electrode 106, and the drain electrode 108 are formed on the semiconductor layer 104.

The data lines DL may be provided in plural, and each of the data lines DL may be spaced apart from each other, and for example, may extend in parallel in a second direction such as the vertical direction of FIG. 1 to cross the gate line GL. can do.

At one end of each data line DL, a data pad lower electrode 140a having a wider width is formed.

The source electrode 106 is connected to the data line DL. A plurality of source electrodes 106 may be connected to one data line DL. Each source electrode 106 faces a drain electrode 108 spaced apart from it.

The active layer 104a is exposed in the space between the source electrode 106 and the drain electrode 108.

In the present specification, the data line DL, the data pad lower electrode 140a, the source electrode 106, and the drain electrode 108 are sometimes referred to collectively as a “data line” for convenience of description.

The data lines DL, 140a, 106, and 108 are not limited thereto, but may include aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), and tantalum ( It may be a single film made of Ta), Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), an alloy thereof, or the like, or a multilayer formed of a combination thereof.

The protective layer 105 is formed on the data lines DL, 140a, 106, and 108.

The protective layer 105 may include a first contact portion H1 that contacts the drain electrode 108 and the pixel electrode 120, and a data pad lower electrode 140a that contacts the data pad upper electrode 140b. Most of the data lines DL, 140a, 106, and 108 except for the third contact portion H3 are positioned on the exposed active layer 104a of the channel region.

The protective layer 105 protects lower structures such as the data lines DL, 140a, 106, and 108, the active layer 104a, and the gate lines 102, GL, and 130a.

In the region where the gate pad lower electrode 130a is formed, a second contact portion H2 penetrating through the gate insulating layer 103 and the protective layer 105 is formed, and in the region where the data pad lower electrode 140a is formed. A third contact portion H3 is formed through the layer 105.

The gate pad lower electrode 130a and the gate pad upper electrode 130b electrically connected through the second contact portion H2 constitute the gate pad 130. The data pad lower electrode 140a and the data pad upper electrode 140b electrically connected through the third contact portion H3 form the data pad 140.

The pixel electrode 120 made of a transparent conductive material such as ITO or IZO or a reflective conductive material such as copper (Cu) or silver (Ag) is formed on the insulating substrate 101 on which the protective layer 105 is formed.

The pixel electrode 120 extends to the first contact hole H1 and is electrically connected to the drain electrode 108.

In addition, in the gate pad 130 forming region, a gate pad upper electrode 130b electrically connected to the gate pad lower electrode 130a is formed at the same time as the pixel electrode 120.

Similarly, in the data pad 140 forming region, a data pad upper electrode 140b electrically connected to the data pad lower electrode 140a is formed at the same time as the pixel electrode 120.

3A to 3I are diagrams sequentially illustrating a manufacturing process of the thin film transistor array substrate of FIG. 1.

First, referring to FIG. 3A, after depositing a metal material on the insulating substrate 101 to form a first metal layer (not shown), coating of photoresist, exposure using a mask, development of photoresist, etching, A first mask process including a strip of photoresist is performed to form a gate line (GL in FIG. 1) extending in one direction, and at the same time, a gate connected to the gate line (GL in FIG. 1). Electrode 102 is formed.

In this case, the first metal layer (not shown) may be formed of two or more layers by continuously depositing different metal materials to form a gate line (GL of FIG. 1) and a gate electrode 102 having a double layer or a multilayer structure. In the drawings, the gate line (GL in FIG. 1) and the gate electrode 102 having a single layer structure are shown for convenience.

Next, referring to FIG. 3B, an inorganic insulating material such as silicon oxide (SiO 2) or silicon nitride (SiN x) is deposited on the entire surface of the insulating substrate 101 on which the gate line GL and the gate electrode 102 are formed. Thus, the gate insulating film 103 is formed.

Subsequently, the pure amorphous silicon layer 114a and the impurity amorphous silicon layer 114b are sequentially deposited on the gate insulating layer 103, and the second metal layer 107 is formed on the impurity amorphous silicon layer 114b.

Thereafter, a photoresist is applied on the second metal layer 107 to form a photoresist layer 150.

In this case, the photoresist layer 150 will be described by using a positive type (Positive type) having a characteristic that the light-receiving portion is removed during development.

However, in the case where the light-receiving part has a negative type that remains during development, the positions of the transmission area TA and the blocking area BA in the exposure mask 200 will be described later. The same result can be obtained by using the exposure mask of the form which changed to.

 Next, the exposure mask 200 is positioned on the insulating substrate 101 on which the photoresist layer 150 is formed. The exposure mask 200 has a transmissive area TA that transmits light, a blocking area BA that blocks light, and a transflective area having a light transmittance smaller than the transmissive area TA and larger than the blocking area BA. (HTA).

The transflective area HTA may be formed in a slit form or may have multiple coating layers.

In this case, the blocking area BA of the exposure mask 200 corresponds to a portion where the data line (DL of FIG. 1) and the source and drain electrodes 106 and 108 are to be formed, and the transflective area HTA is a source. And a portion where a spaced area between the drain electrode 108 is to be formed and the transmission area TA corresponds to the remaining area.

Next, as shown in FIG. 3C, development is performed on the photoresist layer 150 (FIG. 3B) exposed by the exposure mask 200.

In this case, a first photo having a first thickness corresponding to a portion where the data line (DL of FIG. 1) is to be formed and a portion where the source and drain electrodes 106 and 108 are to be formed on the second metal layer 107 by the developing process. The resist pattern 200a is formed. In addition, a second photoresist pattern 200b having a second thickness that is thinner than the first thickness may correspond to a portion to be a spaced area between the source and drain electrodes 106 and 108, that is, a portion where the gate electrode 102 is formed. Is formed.

Corresponding to regions other than the above, the photoresist layer (150 in FIG. 3B) is removed to expose the second metal layer 107.

Next, as illustrated in FIG. 3D, wet etching using the etchant is performed to remove the exposed second metal layer 107. In this case, when the second metal layer 107 is made of copper or a copper alloy, the etching rate is larger than that of the case of the other metal material.

A source drain pattern 107a is formed under the first and second photoresist patterns 200a and 200b.

As shown in FIG. 3E, ashing is performed on the insulating substrate 101 on which the first and second photoresist patterns 200a and 200b and the source drain pattern 107a are formed.

The ashing process is to remove the second photoresist pattern 200b and to reduce the width of the first photoresist pattern 200a.

By removing the second photoresist pattern 200b by ashing, a part of the source drain pattern 107a is exposed, and at the same time, the thickness and width of the first photoresist pattern 200a are reduced. The third photoresist pattern 200c is formed.

Subsequently, as shown in FIG. 3F, dry etching is successively performed on the insulating substrate 101 on which a part of the source drain pattern 107a is formed to expose the impurity amorphous silicon exposed to the outside of the third photoresist pattern 200c. The layer (114b of FIG. 3) and the pure amorphous silicon layer (114a of FIG. 3e) below it are removed.

Therefore, in the region where the thin film transistor TFT is formed, an ohmic contact layer 104b and an active layer 104a having the same area and overlapping the same may be formed under the source drain pattern 107a.

The active layer 104a, the ohmic contact layer 104b, and the source drain pattern 107a, which are sequentially stacked at this stage, have their ends coincident with each other.

Subsequently, as shown in FIG. 3G, the source drain pattern 107a exposed to the outside of the third photoresist pattern 200c by wet etching the substrate 101 on which the ohmic contact layer 104b is formed. The source electrode 106 and the drain electrode 108 are formed to be spaced apart from each other.

In this case, the etching process is performed using an etching solution in which the fluorine (F) component is increased compared to the etching solution used in the conventional wet etching. Specifically, the content of NH4F (Ammonium Fluoride) having a odorless, corrosive, non-flammable property as a clean aqueous solution of the main components of the etching solution to be approximately 0.3.

As described above, when wet etching is performed using an etchant in which fluorine (F) is increased, the ohmic contact layer 104b between the spaced source electrode 106 and the drain electrode 108 is removed together.

In the wet etching process using an etchant having an increased fluorine (F) component, the ohmic contact layer 104b disposed under the source drain pattern 107a and the source drain pattern 107a is removed together to form the active layer 104a. A portion of the ohmic contact layer 104b is formed below the source and drain electrodes 106 and 108 and is spaced apart from each other.

The ohmic contact layer 104b and the active layer 104a below the semiconductor layer 104 form the gate electrode 102, the gate insulating layer 103, the semiconductor layer 104, and the source and drain electrodes 106. 108 forms a thin film transistor (TFT).

Subsequently, as illustrated in FIG. 3H, a strip is applied to the substrate 101 on which the ohmic contact layer 104b is formed below the source electrode 106 and the drain electrode 108 to form the third photoresist. The pattern (200c in Fig. 3g) is removed.

Thereafter, an inorganic insulating material, for example, silicon oxide (Si02) or silicon nitride (SiNx) is deposited on the source and drain electrodes 106 and 108 to form a protective layer 105, and the mask process is performed to perform the mask process. A first contact hole H1 exposing the drain electrode 108 is formed.

Next, as illustrated in FIG. 3I, a transparent conductive material such as indium tin oxide or indium zinc oxide is deposited on the entire surface of the protective layer 105 having the first contact portion H1. A material layer (not shown) is formed.

Subsequently, the thin film transistor array substrate 100 according to the present invention may be completed by forming the pixel electrode 120 in contact with the drain electrode 108 through the first contact portion H1 by patterning the mask process. Can be.

As described above, the present invention can simplify the manufacturing process by simultaneously removing the source drain pattern and the ohmic contact layer formed under the wet etching process using an etchant having an increased fluorine (F) component.

In addition, the present invention can improve the reliability of the product by minimizing the defects caused by static electricity generated during the dry etching process by reducing the number of dry etching process.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive.

100: thin film transistor array substrate 101: insulating substrate
102 gate electrode 103 gate insulating film
104: semiconductor layer 104a: active layer
104b: ohmic contact layer 105: protective layer
106: source electrode 108: drain electrode
120: pixel electrode

Claims (7)

Forming a gate line extending in one direction on the substrate and a gate electrode connected to the gate line;
Sequentially forming a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a first metal layer over the gate electrode;
Forming first and second photoresist patterns over the first metal layer;
Performing a first wet etching process on the first metal layer exposed to the outside of the first and second photoresist patterns to form a data line and a source drain pattern;
Exposing the data line and a portion of the source drain pattern to the outside by ashing;
Dry etching the pure amorphous silicon layer and the impurity amorphous silicon layer to form an ohmic contact pattern and an active layer having the same shape and area under the source drain pattern and completely overlapping each other;
The source drain pattern exposed to the outside is removed using a fluorine etchant to form source and drain electrodes spaced apart from each other, and at the same time, an ohmic contact pattern disposed under the source drain pattern is removed to form an ohmic contact layer. And exposing the active layer located outside to the thin film transistor array substrate. The method according to claim 1,
And forming a passivation layer exposing the drain electrode over the source and drain electrodes. The method of claim 2,
And forming a pixel electrode in contact with the exposed drain electrode over the passivation layer. The method according to claim 1,
The method of manufacturing a thin film transistor array substrate, characterized in that the content of NH4F (Ammonium Fluoride) in the fluorine etching solution is 0.3. The method according to claim 1,
The first metal layer is a method of manufacturing a thin film transistor array substrate, characterized in that made of copper or copper alloy. The method according to claim 1,
The first and second photoresist pattern is a method of manufacturing a thin film transistor array substrate, characterized in that having a different thickness. The method according to claim 1,
The ashing may further include removing the second photoresist pattern and simultaneously forming a third photoresist pattern having a width smaller than the width of the first photoresist pattern. Manufacturing method.

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