TW201124784A - Double gate pixel array substrate - Google Patents

Abstract

A double gate pixel array substrate including a substrate, a first conductive layer, a gate insulator, a semiconductor layer, a second conductive layer, a passivation layer and a transparent conductive layer is provided. The first conductive layer constitutes a plurality of gate electrodes and a plurality of scan lines. The gate insulator covers the first conductive layer. The semiconductor layer is disposed on the gate insulator, and constitutes a plurality of channel regions, a plurality of first common lines, and a plurality of capacitor electrodes. The first common lines intersect with the scan lines, and connect with capacitor electrodes. The second conductive layer is disposed in a part of the semiconductor layer and the gate insulator. The second conductive layer constitutes a plurality of source electrodes, a plurality of drain electrodes and a plurality of data lines, wherein the data lines are parallel to the first common lines. The transparent conductive layer is electrically connected to each drain electrodes through each contact window of the passivation layer. The transparent conductive layer is overlapped with the passivation layer and each capacitor electrode of the semiconductor layer, so as to constitute a storage capacitor.

Description

201124784 /uuy-i-r-u-027TW 32970twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a display array substrate, and more particularly to a dual scan line halogen array substrate. [Prior Art] With the development of large-size display panels, among the pixeUrray structures of today's liquid crystal display panels, one type is called half source driving (hereinafter referred to as Xing (1) architecture^ The truss can make the number of data lines halved, so the source driver (the price of squatting will also be relatively reduced. In more detail, the two adjacent sub-alloys in the alizarin array of the Hsd frame (Qin pixd) ) is a capital line, which allows the number of data lines to be halved. 'Although HSD-based display panels can be used for rugged drives, the number of moving channels is halved, but due to the odd-numbered two-even numbers in the same-listin The individual elements are connected to different scan lines, so the _ architecture is swept, so the (four) architecture of the pixel array substrate is also called double scan: the line board. As a result, the *ca architecture of the 昼 Array _ ( F_e) The frequency 'source driver halved will reduce the recovery time of the fresh bit by half. In detail, the electrode used to transfer the common power M (__ V Vcom) in the array is doubled due to the scan line = complex = only half of the general architecture, so easy = 曰(cross-talk)' affects the display quality of the overall face. 201124784 2009-IPD-027TW 32970twf.doc/n SUMMARY OF THE INVENTION The present invention provides a dual scan line halogen array substrate which can reduce the resistance of the shared line. The value 'solves the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The first conductive layer is disposed on the substrate and has a structure: a gate insulating layer covers the first conductive layer and a gate insulating layer, and the semiconductor layer constitutes a plurality of channels and a plurality of capacitor electrodes, wherein the channel region is located; , the car pull the first: the common line and the scan line intersect, and the first-common line and the capacitor t-conductor layer constitute a plurality of sources, and the plurality of sources and the respective drains are located on both sides of each channel area, the second hill a bulk layer, wherein the second conductive layer and the semi-conducting layer are formed; the protective layer and each of the capacitive electrodes of the semiconductor layer are in the embodiment of the present invention, the upper=pole, and each pixel electrode is located in each of the two electrodes The storage capacitor of the invention. The proposed data line, each of the proposed data lines and each - Cao Ri further includes a multi-element electrode. Two adjacent 琛 electrically connected to the bamboo 琛 昼 201124784 2uyy-ij^-u-027TW 32970twf.doc/n in the present invention In one embodiment, the above-mentioned serially connected pattern, each of the series of patterns spans each of the data γ layers and further includes capacitor electrodes on both sides of the plurality of lines, and is located in the same column. The Ray is located at each of the data poles connected in series to form a - Two common lines: When the capacitor 2 is open, the opening is located in the tandem pattern and the capacitance of the capacitor electrode:: more = the pattern is in ::: in each case, "the case and == to a steel object - in the embodiment" The material of the semiconductor layer is included in the ttr-implementation of the above-mentioned body of the resistivity of the resistivity. In the embodiment, the above-mentioned capacitor electrodes are along each drawing: = ΐ ΐ array ί plate r side circuit area τ In order to use the 仃, the younger brother is in parallel with the data line, the first address is connected to the first shared bus line, and the peripheral power (4) is connected to the second shared bus line. Line full symplectic (four) f-type double (four) line 昼 scale column substrate, the double scan number Γ ΐ ΐ 双 双 double scan line, multiple data lines, reset data (four) = strip first - common line and a plurality of capacitor electrodes. A plurality of bars and lines are perpendicular to the double-sweeping bribes. A plurality of 201124784 2009-I-P-D-027TW 32970twf.doc/n Alizarin is located in the Alizarin District, where each element has a halogen element and an active element. The plurality of first lines are formed by a semiconductor, and the first common line is alternately arranged with the tilt lines and perpendicularly intersects the double scan lines, and the first common lines are electrically connected to each other. The plurality of capacitors are composed of semi-conducting faces, and the capacitor electrodes are made of a capacitor. The capacitances of the capacitors f and the respective pixel electrodes are formed. The storage capacitors are located along the capacitor electrodes below the same-linarin electrodes.

The column directions are formed in series with each other - a second common line, and the first common line and the first common line are electrically connected to each other. In the embodiment of the present invention, each of the halogen electrodes and each of the capacitor electrodes has only a protective layer, and the storage capacitor is composed of a pixel electrode, a protective layer, and a capacitor electrode. In the embodiment of the present invention, the dual scan line pixel array substrate further includes a plurality of serial patterns, wherein each series pattern crosses two sides of each data line and connects two of the two data lines respectively a capacitor electrode on the side, and a capacitor electrode located under the same-linorin electrode is connected to the pattern by a tandem pattern, and the above-mentioned halogen includes a protective layer, and the protective layer has a plurality of openings The opening is located at the tandem pattern and the capacitor electrode (4), and each-series pattern connects two capacitor electrodes respectively located on one side of the F data line via the two openings. In the present invention, the above-mentioned double-sweeping slab further includes a plurality of anti-patterns, which are respectively touched between each opening and the capacitor electrode, wherein the anti-(four) pattern and the data line are the same film sound. In an embodiment of the invention, the material of the above semiconductor comprises 曰-201124784 2Uuy-i-^.L).〇27Tw 32970twf.doc/n steel erbium compound. The resistivity is substantially in the embodiment of the invention, wherein the semiconductor is ΙΟ-3 Ω-m. In the present invention, the peripheral arrangement of each of the capacitor electrode electrodes described above is employed. In the embodiment of the present invention, the above-mentioned dual scan line $ $ includes a -th-command bus line and a second common-stack line, and the peripheral circuit area of the line-argument array substrate is also known. A common sink line is parallel to the double scan line, the second common dragon is parallel to the data line, and the first: f line extends into the peripheral circuit area and is connected to the first shared bus line, and the second common line extends to the peripheral circuit In the region and in connection with the second shared bus line, based on the above, the dual scan line halogen array substrate of the present invention uses the material of the same film layer as the channel of the active device to fabricate the capacitor electrode and the ^=line' and the capacitor electrode The protective layer and the halogen electrode constitute a storage capacitor, 攸=increasing the capacitance value of the storage capacitor, and the common-line forming a criss-crossing network in the display area by serially connecting the capacitor electrodes of the halogen, thereby greatly reducing the sharing_resistance value. Thereby, the time for the common line to return to the level can be accelerated, the crosstalk phenomenon can be reduced, the data signal voltage can be stabilized, and the display quality can be improved. The above features and advantages of the present invention will become more apparent and understood. [Embodiment] 201124784 /uUy-i-^D-027TW 32970twf.doc/n A double-scan line pixel array two-parameter (4) 1A' double-scan line stack substrate circuit area in a Utr embodiment 200^ It is better to smell _ and a peripheral scoop in the display area 2〇〇D, including the household A certificate, as shown in Figure ,, the double scan line halogen array substrate 200 = multiple scanning, longitudinally extending multiple data Line, 个 里 素 220 and - shared wiring 21 〇. In detail, the data line d

"The line G is intersected, and the dioxane area 22〇r located on opposite sides of each data line D and adjacent to each other is defined in the display area D, and each element 220 is located in each pixel area. 220R N. It is worth noting that the two adjacent scan lines G are electrically connected to a column of halogens 22 位于 between them, and the odd-numbered pixels 220 of the same column are connected to one of the scan lines, and the even columns of the same column The individual pixels 220 are connected to another scanning line G. For example, the scanning lines G1, G2 are connected to the first column R1 element 220 located therebetween, and the odd number of pixels 22 of the first column R1 are connected to the scanning line G1. And the even number of cells 22 of the first column R1 are connected to the scanning line G2, so the unit of such a group of scanning lines G1, G2 is also called a double scanning line. It is worth noting that the common wiring 210 includes a plurality of longitudinal lines. The first common line 21 〇 C 'and in some embodiments 'the common wiring 210 may further include a plurality of lateral second common lines 210R that intersect the first common line 210C in the display area 200D And connected to each other at the intersection" such that the shared wiring 210 In a crisscross network, as shown in the figure, the thicker lines represent the layout of the common wiring, whereby the resistance value of the entire shared wiring 210 can be greatly reduced. In other words, the second common lines 210R and the data lines d are staggered. And the first common line 210C intersects the double scan line vertically, and the second common lines 210R are electrically connected to the 9201124784 <iViwi-r-_u/-027TW 32970twf.doc/n first common line 210C In addition, in the embodiment, the first common bus line 21A and the second common bus line 210B surrounding the display area 200D are further disposed in the peripheral circuit area 2〇〇p, wherein the two first common bus lines 21 are provided. 〇A is located above and below the display area 200D, respectively, and two first common bus lines 21〇8 are respectively connected to the top end and the end of each-to-common line 210C, and the two second common bus lines 210B are respectively located in the display area 2〇左D to the left and right, and - strip-common bus 2 brain connected to each second common line 2 ship ^ end 舆 right end. By the first - shared bus 2 and the second common sink = line 21GB can be horizontally the second shared line 2 Further connected in series with the first collinear line 210C in the longitudinal direction, such as 屮n 〆, _ _ w (4), so as to further reduce the continuation of the common wiring 210, as shown in FIG. 1A, in the present embodiment, when double scanning ^ When the prime array substrate is applied to the display panel, the check in 2 = represents the positive and negative polarity, so in the present embodiment - the display is used, and the present invention is not working: for the color and the driving mode. The apparent etc. of the application of the alizarin is a graph, and several alizarins in the substrate of the 3 働 昼 阵列 阵列 array

Connected pixels 22. 2 and FIG. 1B ' and the same - the data line D are different from Q _, = ^, and the dioxin (10) is traced G(n+1). Each of the pixels 22Q has a description, a line G (8) and a sweep 226 and a halogen electrode 224. Pixel power ^ 224 = 222, capacitor 222D, to receive "---, electric + 224 electrical connection to the 汲 续 电压 voltage and the halogen electrode with and located on it 201124784 ^uv-irD^TTWsigTOtwf.doc/ n : Pair: A liquid crystal capacitor CL is formed between the electrodes CF_Vc〇m. . Further, these capacitor electrodes are connected to each other to form a common wiring and are supplied with a common voltage: FT_:com ' The capacitance electrode C226 is formed between the capacitor electrode 226 and the halogen electrode 224 in parallel with the liquid capacitance cLC. In particular, the adjacent capacitor electrodes 226 intersect each other and are connected to each other between the deniers 220, thereby forming a common wiring 21〇 having a low resistance value, so that under the hsd architecture, the conventional double scan line can be avoided. The display caused by the substrate sound phenomenon is not a good problem. In detail, the capacitor electrode 226 is located below the pixel electrode 224 and forms a storage capacitor with the pixel electrode 224, and the capacitor electrode 226 is electrically connected to each other across the data line D to form a second common line 2, and is first The common line 210C is electrically connected in a longitudinal direction. To further illustrate the features of the present invention, FIG. 2 further illustrates a pixel layout diagram labeled as box π in the Sweep & 昼 阵列 Array substrate of FIG. 1A. In the present embodiment, the second row R2 halogen 220 in the figure ία is taken as an example for detailed description. As shown in Fig. 2, the halogen 22〇Α and the halogen 220 are respectively located on both sides of the data line D2 and connected to the data line D2. • In more detail, the element 22 22 includes an active element 222, a capacitor electrode 226A and a halogen electrode 224A, and the active element 222A includes a gate 222GA, a channel 222CA, a source 222SA, and a drain 222DA. On the other hand, the pixel 220B includes an active element 222B, a capacitor electrode 226B and a halogen electrode 224B, and the active element 222B includes a gate 222GB, a channel 222CB, a source 222SB, and a drain 222DB. As shown in FIG. 2, the gate 222GA can actually be regarded as a part of the scan line G4, and the gate 222GB can only be regarded as a part of the scan line G3, which is located in FIG. 2a 11 201124784 027TW 32970twf.doc /n In one of the left group of pixels 220, the source 222SA and the source 222sb are connected to the same data line D2, and the pixel electrode 224A is connected to the drain 222〇α to be turned on by the scanning line G4 at the active element 222A. At this time, the data element 224B received from the data line D2 is connected to the drain 222DB to receive the data voltage transmitted from the data line when the active element 222B is turned on by the scanning line G3. In the continuous operation, the storage capacitor formed between the pixel electrode and the capacitor electrode is used to stabilize the level of the written sin data voltage during the active component off period. The following describes the configuration of the storage capacitor of the halogen in the double-scan==# array substrate of the present invention. 3A is a cross-sectional view of the double-scan line pixel array substrate of FIG. 2 taken along the line A1_A1 and the line A2-A2. Referring to FIG. 2 and FIG. 3A simultaneously, in the embodiment, the pixel 22A is representative. The active device 222A is mainly composed of a gate 222GA, a gate insulating layer 230, a channel 222CA, a source 222SA, and a drain 222DA. The gate electrode 222GA is connected to the corresponding scan line G4, the gate insulating layer 23 〇 covers the gate 222GA' channel 222CA is located on the gate insulating layer 230 above the gate 222GA, and the source 222SA and the drain 222DA are respectively located in the channel 222CA's call on both sides. The structure and film relationship of the halogen array substrate will be described in detail below. The halogen array substrate includes a substrate 202, a first conductive layer M1, a gate insulating layer η, a semiconductor layer S, a second conductive layer M2, a protective layer 12, and a transparent electrode layer T. The first conductive layer M1 is disposed on the substrate 202, and the gate 222GA and the scan line are composed of the first conductive layer M1. The gate insulating layer 11 covers the first conductive layer M1. The semiconductor layer S is disposed. On the gate insulating layer II' and a portion of the semiconductor layer s (such as the channel layer 222CA) is located on the gate 222GA of a conductive layer M1 of the 12th 201124784 2009-1-FD-027TW 32970twf.doc/n and the other part The semiconductor layer $ (such as the capacitor electrode 226A and the capacitor electrode 226B and the first common line 210C) is disposed on the gate insulating layer II, wherein the first common line 21 (κ: intersects with the scan line G, and the first shared line 210C is connected to the capacitor electrodes 226A, 226B. The second conductive layer M2 is disposed on the portion of the semiconductor layer s and the gate insulating layer 12 and has a source 222SA, a drain 222DA and a data line D, and the first common line 210C Parallel to the data line d. The protective layer ο covers the gate insulating layer II, the second conductive layer M2 and the semiconductor layer 3, and a contact window W1 is disposed on the drain 222DA of the second conductive layer M2. The transparent layer τ is disposed in the protective layer In the county u, part of the semiconductor layer s (such as capacitor electrode 226A and capacitor electrode 226B) is transparent The contact layer W1 on the protective layer 12 and the contact layer W1 on the protective layer 12 are electrically connected to the gate 126DA of the 'electrode layer M2, and the transparent layer τ is overlapped with the protective layer 12 and a portion of the semiconductor s. The structure of the ' ' wire Β 222 与 and the active element Μ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ 。 。 。 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且W1, and 耵I and 222DA, 222DB are connected. Please continue to refer to Figure 3A, in the inspection of the capacitor electrode 226 eight, and the capacitor electrode 2 electrode 224A (5). It is worth mentioning that the capacitor is stored , channel _ is the same - film layer,

In other words, in the case of + 胆 S 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 Therefore, it is not necessary to additionally increase the used wiring 210 in the trimming process step. In particular, between the halogen element capacitor electrode 226 and the total 224A and the capacitor electrode 226A, only the ancient element, since the halogen element can increase the storage capacitance value of the element, and the layer is shaken, the elemental electrode 224A The protective layer 24q is in the center of the heart. In the present embodiment, the information written in the element electrode 224 of the storage red red st header _ large_storage ^^\226 有助于 helps to stabilize the display quality. In addition, in the actual choice Π 'can provide a better application - negative voltage, dreaming that the shared wiring 210 can be found by the moon-powered 疋 疋 电极 电极 electrode 224 and Rayleigh Reto private storage capacitor Cst The single read capacitor value is maximized. In order to clearly illustrate the features of the present invention, the following

In the double-sweep main line array substrate, the configuration pattern of the common wiring is shown in FIG. 2. In the present embodiment, the capacitor electrode 226A is disposed along the periphery of the θ electrode 224A, and the capacitor electrode 2 is applied along the edge. The peripheral arrangement of the crucible is configured to connect the capacitor electrodes of the same column of halogens 220 and the electrode 226B in series along the extending direction of each scanning line 则 to form a second common line 2 in the lateral direction, and - the capacitor electrode 226A of the row element 220 and the capacitor electrode 2 are connected in series with each other along the extending direction of each data line 则 to form a longitudinal first common line 21 〇 c, as shown in the first common line 2i 〇 ci 〜2i〇C3, and each of the first common lines 21〇c is located between two adjacent cells 22〇 electrically connected to different data lines D. For example, the common line 210C2 is electrically connected to the data line D2. Between the element 220B and the halogen 22〇A electrically connected to the data line D3. It is worth 201124784 2009-iPD.〇27TW 32970twf.doc/n ^, in this embodiment, the composition of the first common line 21()c is, for example, the same as the composition of the germanium electrode 226, that is, the first common line 21〇c It is constructed by directly using the capacitor electrode 224 of the same row of pixels 22G. The special S'capacitor electrode 226, the second common line 2, and the first: common line 21GC include, for example, a semiconductor layer, and the composition of the semiconductor layer "channel 222C" has the same composition. In this embodiment, the material of the semiconductor is, for example, indium. Zinc oxynitride (In_Ga_Zn_〇, deuterium), because of the high carrier mobility and low resistance of the samarium oxide compound, the resistivity of the common wiring 210 is further reduced by 3, for example The permeation is 4 10·3 Ω-Π1. When such an indium antimony zinc oxide compound is used as the channel 222C of the active device 222, 'the active element 222 can be given a higher turn-on current OU current) and the lower driving voltage is advantageous. It should be particularly noted that the capacitor electrode 226 of the present invention and the channel 222C (222CA, 222CB) of the main element 222 are the same film layer, since the film layer constituting the capacitor electrode 226 is different from the scanning line G and the closed electrode. The first conductive layer of 222G is different from the second conductive layer constituting the data line d, the source work $ and the pole 222D, so that the display area 2_ the electric valley electrode 226 can be directly connected in series to form the first in the vertical direction. Shared line 2 And forming a horizontal (four) second common line 2 ship by a simple jumper method. In order to clarify how the capacitor electrode of the same type of the present invention is connected in series with each other in the extending direction of each scanning line to form a second The common line, the text will be combined with FIG. 3B, FIG. 4A and FIG. 4B, and the configuration will be described in detail. FIG. 3B is the double-scan line pixel array substrate of FIG. 2 labeled as ^201124784 2Wy-iru-027TW 32970hvf.doc/ A partial enlarged view of n, FIG. 4A is a schematic diagram of a face-to-face along the line IV-IV of FIG. 3B. Please refer to FIG. 3B and FIG. 4A simultaneously, and the second common line 2 leg has a intersection with each data line D. The serial pattern 25 is, for example, the data line D2 in the figure, wherein each of the series patterns 25 跨越 spans each side of each data line d, and each of the series patterns 25 〇 connects two of them respectively on the same material line D Capacitor electrodes 226a, 22 〇β on both sides, so that even if the plexes are interdigitated with IF and D, the second hunger line & and the greedy line D can be electrically insulated from each other. ^ Specifically, 昼The protective layer 240 of the element 220 has a plurality of openings H, and the openings Η are located in the series pattern 250 and the capacitor electrode 226Α The overlap and the overlap of the series pattern 25G and the capacitor electrode 226 , expose the capacitor electrodes 226 Α , 226 以 in cents, so the series pattern 25Q is connected to the capacitor electrode 226A and the capacitor electrode 2 via the opening H1 and the opening H2, respectively. In addition, in the fabrication, the tandem pattern 25 can be fabricated with the halogen electrode 224B using the same-pass mask process. In other words, the series pattern and the pixel electrodes 224A, 2 can be the same film layer, so the string The pattern 250 is compatible with the original process without additional processing. When the -iff is made at the opening of the protective layer 24G, the capacitor electrode 226 U protects the network of the layer 24G from being damaged. Therefore, some applications may also be used between the series pattern 25G and the capacitor electrode 226. Assume

The primary anti-etching pattern 260' is as shown in Fig. 4B. Fig. 4B is a schematic cross-sectional view showing another section of the Iv IV section of Fig. 3B. Please refer to 4B, double scan. The array substrate further includes a plurality of anti-瞧260, each of which is located at each opening η, and the series pattern 〇 is connected between the capacitor electrode 16 and the capacitor electrode 16 201124784 2009-IPD-027TW 32970twf.doc/n 226. In practice, the anti-etching pattern 260 can be fabricated using the same mask process as the source, drain, and data lines. In other words, the anti-etching pattern 260 can be the same film layer as the source, drain, and data lines. The exact connection between the capacitor electrodes 226A, 226B and the series pattern 25A can be achieved by the anti-etching pattern 260. It is worth mentioning that, in addition to the above-mentioned manner, the second common line 210R in the horizontal direction and the first common line 2i〇c in the vertical direction are connected to each other in the display area 200D, thereby forming a network which is criss-crossed, and the present embodiment For example, the first shared bus line 210A and the second shared bus line 21〇B as shown in FIG. 1A can be disposed around the display area, as shown in FIG. 1A, and the first shared bus line 210A is disposed. Parallel to the scanning line G and located in the peripheral circuit region 200P, and the second common bus line 21〇B is parallel to the data line D and located in the peripheral circuit region 200P, thereby allowing the common voltage transmitted by the shared wiring 21〇 to be more smoothly Being transmitted. Specifically, FIG. 5A further illustrates a specific layout of the upper half of the dual scan line pixel array substrate of FIG. 5A, and FIG. 5B further illustrates a partial enlarged view of FIG. Referring to FIG. 5A and FIG. 5B simultaneously, in the dual scan line pixel array substrate 2 of the embodiment, the longitudinal first common lines 210C1 210 210C6 are outwardly directed from the display area 200D along the data line D. Extending, and connecting the top ends of each of the first common lines 21〇C1 to 21〇C6 to each other in the peripheral circuit area 2〇〇p by the first common bus line 210A, since the present invention constitutes the first common line 21〇cl The film layer of ~21〇C6 is different from the film layer constituting the scanning line G, and the film layer constituting the first common line 210C1 210210C6 and the film layer constituting the scanning line G have - 17 201124784 z.uu^- irL/-027TW 32970twf.doc/n gate insulating layer 230, so when the first common line 210C1 210210C6 crosses the scanning line G, it is not necessary to use the jumper design', thereby further reducing the resistance value of the first common line 210C1 210210C6. It helps to reduce the resistance value of the entire shared wiring 210. Similarly, with the concept of FIG. 5A and FIG. 5B, the ends of the longitudinal first common lines 2i 〇 c can be further connected to each other by another first common bus line 210A' or according to the above concept. The left end or the right end of each second horizontal common line 21GR may be connected in series with each other on the two sides of the display area 200D by using the second common bus line 21〇B (shown in FIG. 1A) to form a structure as shown in FIG. 1A. The first-common bus line 21A and the second common bus line 210B are shown. In addition to the dual scan line pixel array substrate 2 (8) as described above, FIG. 6 further illustrates another embodiment of the above design concept, which is not based on the present invention. . The components in which the aforementioned actual wipes have appeared will not be repeatedly described below, and the related description will be omitted. As shown in FIG. 6 , the dual scan line pixel array substrate 300 of the present embodiment further sets a == 330 between two adjacent and different data lines, wherein the pseudo data line 33 () is a light. The mask process is patterned, the two belong to the same film layer and have the same composition. FIG. 7 is the T of FIG. 6 along the AA section line. Specifically, in the present embodiment, the double: two array resistance values are Respond to the standard in a limited time 201124784 2009-1-PD-027TW 32970twf.doc/n Improve the display quality. In summary, the storage capacitor of the dual scan line halogen array substrate of the present invention can obtain a large storage capacitor value and help stabilize the level of the data voltage written in the pixel electrode, and utilize The channel of the active element belongs to the same material of the film layer to form a common wiring, and the capacitor electrode connected to the pixel is used to form a crisscross signal transmission network, thereby reducing the resistance value of the entire shared wiring. Therefore, the dual scan line # 昼 阵列 array substrate of the invention not only has the effect of halving the data line of the HSO structure, but also stabilizes the data signal voltage, and the mesh common wiring with low resistance can be coupled for a limited time. Quick response, effectively solve the problem of horizontal crosstalk' and thus improve the overall display quality. The present invention has been disclosed in the above embodiments, and it is not intended to limit the invention to those skilled in the art, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a top plan view of a dual scan line halogen array substrate according to an embodiment of the invention. 1B is an equivalent circuit diagram of several elements in the dual scan line halogen array substrate of FIG. 1A. FIG. 2 is further a schematic diagram showing the layout of the pixel in the double-scan line pixel array substrate of FIG. 3A is a cross-sectional view of the double scan line halogen array substrate of FIG. 2 taken along line AA 19 201124784 2〇uy-i-F-u-027TW 32970twf.doc/n. Fig. 3B is a partial enlarged view of Fig. 2. The double scanning line halogen array substrate is denoted as B. Fig. 4A is a schematic cross-sectional view of the WV_IV sectional line of Fig. 3B. 4B is another schematic cross-sectional view of FIG. 3B taken along the line IV-IV. Fig. 5A is a partial schematic view showing the boundary between a display area and a peripheral circuit area in a dual scan line pixel array substrate according to an embodiment of the present invention. Figure 5B is a partial enlarged view of B in a further green view.

6 is a schematic diagram showing the layout of a pixel of a dual scan line halogen array substrate in the embodiment of the present invention. Figure 7 is a cross-sectional view of Figure 6 taken along line AA. [Description of main component symbols] 200, 300: Dual scan line halogen array substrate 200D: display area

200P: peripheral circuit area 210: common wiring 210A: first common bus line 210B: second common bus line 210R: second common line 210C, 210C1 to 210C6, 320: first common line 220, 220A, 220B: Alizarin 220R : 昼素区222, 222A, 222B: active components 222C, 222CA, 222CB: channel 20 201124784 2009-IPD-027TW 32970twf.doc/n 222D, 222DA, 222DB: bungee 222GA, 222GB: gate 222SA, 222SB: source Pole 224, 224A, 224B: halogen electrode 226, 226A, 226B: capacitor electrode 230: gate insulating layer 240: protective layer 250: series pattern m W 260: anti-etching pattern 330: pseudo data line CF_Vcom: counter electrode Clc :Liquid crystal capacitor Cst : Storage capacitor D, D1 to D6 : Data line G, G1 to G6, G(n), G(n+1): Scan line Η, HQ, H2: Opening φ R1 : First column TFT_Vcom : Common voltage W, W Bu W2: contact window 21

Claims (1)

201124784 ^uuy-ir.JU.〇27TW 32970twf.doc/n VII. Patent Application Range: 1. A dual scan line halogen array substrate comprising: a substrate; a first conductive layer 'disposed on the substrate' Forming a plurality of gates and a plurality of scan lines; a gate insulating layer covering the first conductive layer; a semiconductor layer disposed on the gate insulating layer, the semiconductor layer forming a plurality of channel regions, a plurality of first common lines, and a plurality of capacitor electrodes: wherein the channel regions are located on the gates to allow the first common lines Intersecting the scan line, and the first common line and the capacitor electrodes are connected with a second conductive m on a portion of the semiconductor layer and the insulating layer, the second conductive layer forming a plurality of sources a pole, a plurality of drains, and a plurality of data lines, wherein each of the source and each of the drains are located on opposite sides of each of the channel regions, and the first common lines are parallel to the data lines; An insulating layer, the second conductive layer, and the two body layer, wherein the protective layer is provided with a contact window on each of the gates; a transparent electrode layer is disposed on the pith layer, and a contact window of the Qianming electrode is electrically connected to each of the drain electrodes. The transparent electrode layer is stacked on the capacitor electrode 4 of the + conductor layer. 2,.=, the double-touch book of the patent 1 item: the Zhong Qianming conductive layer constitutes a plurality of halogen electrodes, each of which is located above each of the capacitor electrodes, and each of them Alizarin, only between the poles and the composition of the system _ storage ς: /, each of the electricity (four) 22 201124784 20U9-1-FD-027TW 32970twf.doc / n 3. Doubles as described in claim 2 Scanning the substrate, the second conductive layer further comprises a plurality of pseudo-data lines, wherein the material line overlaps with each of the first common lines and is electrically connected in parallel, and each of the two: the two connected to the different (four) lines Adjacent painting money door door material line 4 such as applying for full-time (four) 2 Lai double sweeping _ substrate 'the towel' of the dialo electric layer also includes multiple j = == data line and connected on both sides of each data line = serially connected to the bottom of the same pixel electrode, the capacitor electrodes are connected in series to form a two-common line. Μ 5· The double scan line halogen array according to item 4 of the patent scope, wherein the protective layer further has a plurality of openings, the openings being located at an overlap of the connection patterns and the capacitor electrodes, and each connected Two == substrate & 5 double-sweeping aldarin arrays respectively located on the two sides of the same data line include four anti-(four) patterns in each of the openings, and the tandem pattern between the two positions Between the capacitor electrode and the capacitor. The double scan line halogen array described by you in the first place. Soil 8: The second half is used to check the conductor, and the material includes an indium zinc oxy compound. The substrate has a resistivity of substantially 10·3 Ω-ιη. Substrate, (4) A double-sweeping nucleus array of one item. Each electrode is arranged along the periphery of each of the element electrodes. The substrate further includes a double scan line pixel array shared bus line and a second common bus line as described in item 1, 23 201124784 is called (10) small Bu U-027TW 32970twf.d〇c/n is located in the double scan line. a peripheral circuit region of the array substrate, wherein the first i=line is parallel to the scan lines, the second common bus line and the second; the first common line extends to the peripheral circuit area The brothers are connected by a common bus line, and the second circuit area is connected to the second common bus line 1. The shape is extended to the periphery I1. The double scan line pixel array substrate, the package. a scanning line; a plurality of pixels of the greedy line 'peripherally intersecting the two scanning lines to form a multi-primary drawing plurality of first common lines, arranged by a half-error and co-located with the double scanning lines /, the wires are electrically connected to each other; and the semiconductors are formed by the semiconductors, and the capacitor electrodes are formed into a contact capacitance, and the pixel electrode structure lines and the second common lines are electrically connected to each other. a line, and the first conjugated substrate The 昼 阵 保护 , , , , 保护 保护 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 阵 保护 阵 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护 保护D-027TW 32970twf.doc/n The two sides of the data line are connected to two sub-capacitors, and the poles on both sides of the same data line are connected to each other by the series of patterns. The capacitors are electrically D: the openings are located in the series of patterns; the two sides of the strip data lines are connected to the two-scan line array of the two-character array Each of the data in the opening = between the electrodes, wherein the anti-(four) pattern and the column:::: ratio:: quality 11:, the scanning line pixel matrix n material includes - indium oxo compound. Column substrate: its double scan line 昼 阵 is “ 率 率 率 率 率 率 率 率 率 率 率 率 率 率 率 率 率 率 率 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列 列Peripheral configuration. The board further includes the double-female line of the matrix described in the first paragraph, and the second bust line, and the second periphery of the substrate. a circuit area, which is parallel to the middle of the hill, the second common bus line leg is used by the first hill, and the line extends to the peripheral circuit area and is connected to the circuit area, and These second common lines extend to the perimeter of the Guardian - the shared bus line connection.