CN102566168A - Array substrate, manufacturing method thereof, and liquid crystal display device - Google Patents
Array substrate, manufacturing method thereof, and liquid crystal display device Download PDFInfo
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- CN102566168A CN102566168A CN2010106166093A CN201010616609A CN102566168A CN 102566168 A CN102566168 A CN 102566168A CN 2010106166093 A CN2010106166093 A CN 2010106166093A CN 201010616609 A CN201010616609 A CN 201010616609A CN 102566168 A CN102566168 A CN 102566168A
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Abstract
The invention provides an array substrate, a manufacturing method thereof, and a liquid crystal display device, wherein the array substrate comprises a display area and a border area surrounding the display area; the display area comprises a plurality of orthorhombic and insulated data lines and scanning lines; the data lines and the scanning lines divide the display area into a plurality of pixel areas with ordered arrays; each pixel area internally comprises a pixel electrode, a common electrode, a thin film transistor, a first transparent electrode arranged above the pixel electrode and equipotential with the pixel electrode, a second transparent electrode arranged above the common electrode and equipotential with the common electrode, and a plurality of scanning connection lines which are used for electrically connecting each scanning line with an external drive chip; and the second transparent electrodes are located above the scanning connection lines. The area of the border area can be saved, and the utilization rate of the substrate is improved.
Description
Technical field
The present invention relates to liquid crystal indicator, particularly dwindle array base palte and the liquid crystal indicator and preparation method thereof of narrow frame design of the border width of coplane conversion type liquid crystal display device.
Background technology
Flat-panel screens is at present main popular display, and wherein LCD is more frivolous because have external form, power saving and characteristic such as radiationless, and be widely used on the electronic products such as computer screen, mobile phone, personal digital assistant, flat-surface television.
Fig. 1 is the diagrammatic cross-section of existing liquid crystal indicator, and is as shown in Figure 1, the array base palte 3 that liquid crystal indicator generally includes color membrane substrates 1, is oppositely arranged with color membrane substrates 1, and liquid crystal layer 2 clampings are between color membrane substrates 1 and array base palte 3.Said array base palte 3 is provided with pixel electrode and thin film transistor (TFT) with respect to the inboard of color membrane substrates 1; And public electrode is set on array base palte 3 or color membrane substrates 1; Between said pixel electrode and public electrode, form and drive the electric field that the liquid crystal molecule in the liquid crystal layer 2 turns to, just can realize the demonstration of image.
Receive the mechanism that electric field driven turns to different according to liquid crystal molecule, liquid crystal indicator generally include coplane conversion type (In-Plane Switching, IPS) and twisted nematic (Twisted Nematic, TN).
Fig. 2 is the cross-sectional view of coplane conversion type liquid crystal display device in the prior art.As shown in Figure 2; Two electrodes that are different from the twisted nematic liquid crystals display device are respectively at two substrates up and down; And between upper and lower base plate, form electric field; Two the electrode 16A and the 16B of IPS liquid crystal indicator are positioned on the array base palte 14B, and color membrane substrates 14A is a upper substrate, and polaroid 10,12 sticks respectively in the outside of array base palte 14B and color membrane substrates 14A.All liquid crystal molecules all are to be arranged in parallel with array base palte 14B; Electrode 16A, 16B making alive respectively form electric field; Under effect of electric field, the direction deflection that liquid crystal molecule will be parallel with array base palte 14B, such arrangement has improved the visual angle of liquid crystal display device greatly.
Fig. 3 is the schematic top plan view of coplane conversion type liquid crystal display device in the prior art, divides liquid crystal indicator according to function and comprises viewing area 20 and frame region 30.Comprise in length and breadth the sweep trace and the data line that are provided with in the said viewing area 20, and by the pixel cell of its definition.Said frame region 30 comprises multi-strip scanning connecting line 21, and said scanning connecting line 21 is used for being connected with corresponding scanning line and the signal of external drive circuit 40 is transferred to corresponding sweep trace.
There is following problem in prior art: frame region 30 is used to hold scanning connecting line 21, and along with the raising day by day of liquid crystal display resolution and the miniaturization of liquid crystal indicator, the area that need dwindle frame region 30 is to improve the utilization factor of liquid crystal panel.Therefore just there are not enough spaces to hold multi-strip scanning connecting line 21 in frame region 30.
How to realize the narrow typeization of frame region 30, the utilization factor that improves liquid crystal panel becomes the technical matters that those skilled in the art need to be resolved hurrily.
Summary of the invention
The technical matters that the present invention solves has provided a kind of array base palte and preparation method thereof, display panels, has reduced the area of the frame region of array base palte and display panels, has improved the utilization factor of array base palte and display panels.
The array base palte of coplane conversion type liquid crystal display device provided by the invention, the frame region that comprises the viewing area and surround said viewing area, said viewing area comprises:
The data line and the sweep trace of many quadratures and mutually insulated;
Said many data lines and sweep trace are divided into the viewing area pixel region of a plurality of array arrangements; Comprise pixel electrode, public electrode, thin film transistor (TFT) in each pixel region, also comprise be arranged on the pixel electrode and with equipotential first transparency electrode of pixel electrode be arranged on the public electrode also and equipotential second transparency electrode of public electrode;
Also comprise the multi-strip scanning connecting line, each bar sweep trace of correspondence be electrically connected with the external drive chip that said second transparency electrode also is positioned on the said scanning connecting line.
Said public electrode and pixel electrode have overlapping, are used to constitute MM CAP.
Optional, said scanning connecting line and data line laterally arrange.Said scanning connecting line and data line equal in length in the viewing area.Said scanning connecting line and data line are with one deck metal.The live width of said scanning connecting line is less than the width of second transparency electrode of its top, and covered by said second transparency electrode.
Said scanning connecting line is connected in the viewing area with sweep trace.
Optional, the insulating medium layer that is formed with via hole is set between said scanning connecting line and the sweep trace, said scanning connecting line directly is connected with the scanning connecting line in via hole.
Optional, said scanning connecting line and sweep trace connect through position via hole and other layers intermetallic that is positioned at via hole on it in succession.
Optional, said pixel electrode is divided into first pixel electrode and second pixel electrode, and said scanning connecting line is between first pixel electrode and second pixel electrode.Said public electrode is divided into first public electrode and second public electrode, and said first public electrode and second public electrode lay respectively at the outside of first pixel electrode and second pixel electrode.
Optional, said scanning connecting line is between the data line in pixel electrode and neighbor district.
Optional, the material of said first transparency electrode and second transparency electrode is tin indium oxide or zinc paste.
Optional, the public electrode in colleague and the adjacent pixels district interconnects.Said public electrode adopts direct voltage drive.
The grid of the thin film transistor (TFT) in every capable pixel region is corresponding to be electrically connected with a sweep trace; The source electrode of the thin film transistor (TFT) in every row pixel region is corresponding to be electrically connected with a data line, and drain electrode is corresponding to be electrically connected with the interior pixel electrode of this pixel region.
Coplane conversion type liquid crystal display device of the present invention comprises liquid crystal layer and color membrane substrates, also comprises above-mentioned array base palte, and said liquid crystal layer is between said array base palte and color membrane substrates.
The present invention also provides the method for making of above-mentioned array base palte, comprising:
Substrate is provided, the frame region that said substrate is divided into the viewing area and surrounds said viewing area;
In said viewing area, form the first metal layer, and adopt the first road mask, the graphical said the first metal layer of photoetching process to form the grid of thin film transistor (TFT), sweep trace and the public electrode that is connected with said grid;
Form first insulating medium layer;
Adopt the second road mask, said first insulating medium layer of photoetching process etching forms first via hole, and said first via hole exposes said sweep trace;
Form amorphous silicon layer, doped amorphous silicon layer, and adopt the 3rd road mask, photoetching process etching to form the active layer of said thin film transistor (TFT);
Form second metal level; Adopt the 4th road mask, graphical said second metal level of photoetching process to form the source-drain electrode metal of data line, pixel electrode, scanning connecting line and thin film transistor (TFT); Said data line is connected with the source metal of thin film transistor (TFT), and said scanning connecting line directly is connected with sweep trace in first via hole;
Form second insulating medium layer, adopt the 5th road mask, said second insulating medium layer of photoetching process etching to form second via hole that exposes said thin film transistor (TFT) drain metal;
Said data line and sweep trace are divided into the viewing area pixel region of array arrangement; Form first transparency electrode and second transparency electrode on the said structure surface; Said first transparency electrode is connected with the drain electrode of thin film transistor (TFT) in second via hole, and said second transparency electrode covers the scanning connecting line and the public electrode of its below.
Optional; Said formation first transparency electrode and second transparency electrode comprise: at the said second insulating medium layer surface deposition electrode material, adopt the 6th road mask, photoetching process in said pixel region, to form first transparency electrode and second transparency electrode simultaneously.Said electrode material is tin indium oxide or zinc paste.
Compared with prior art; The present invention has following advantage: will scan connecting line and be arranged at the viewing area, and with the second transparency electrode overlaid, and second transparency electrode and public electrode equipotential; Utilize the scanning connecting line that the scan drive circuit signal is transferred to corresponding sweep trace; Practice thrift the area of frame region, do not influenced the aperture opening ratio of viewing area simultaneously, improved the utilization factor of substrate.
Further optimally, said scanning connecting line and data line are with one deck metal, are easy to make; And do not take pixel region, therefore can not influence the aperture opening ratio of viewing area.
Public electrode can adopt DC driven in the course of work of liquid crystal indicator in addition, to avoid interference the voltage of sweep trace or scanning connecting line.
Description of drawings
Fig. 1 is the diagrammatic cross-section of existing display panels;
Fig. 2 is the diagrammatic cross-section of existing coplane conversion type liquid crystal display device;
Fig. 3 is the schematic top plan view of existing coplane conversion type liquid crystal display device;
Fig. 4 is the array base palte plan structure synoptic diagram of first embodiment of the invention;
Fig. 5 is the cross-sectional view of array base palte shown in Figure 4 along the A-B hatching line;
Fig. 6 to Figure 17 is the diagrammatic cross-section of each step of the first embodiment method for making;
Fig. 6 a to Figure 17 a is the schematic top plan view of the part steps of the first embodiment method for making;
Figure 18 is the array base palte plan structure synoptic diagram of second embodiment of the invention;
Figure 19 is the cross-sectional view of array base palte shown in Figure 180 along the C-C hatching line;
Figure 20 to Figure 23 is the diagrammatic cross-section of the part steps of the second embodiment method for making;
Figure 24 is the array base palte plan structure synoptic diagram of third embodiment of the invention.
Embodiment
To combine specific embodiment that technical scheme of the present invention is carried out detailed explanation below.
First embodiment
With reference to figure 4, be the array base palte plan structure synoptic diagram of first embodiment of the invention.
The frame region that said array base palte is divided into the viewing area and centers on the viewing area is simplicity of illustration, and the subregional schematic top plan view in middle part, viewing area only is shown among Fig. 4.Comprise in the said viewing area: the glass substrate (not shown); Be positioned at the multi-strip scanning line on the glass substrate: sweep trace 101, sweep trace 103, sweep trace 105 etc.; Many data lines: data line 102, data line 104, data line 106 etc.; Each sweep trace and data line quadrature and mutually insulated; Data line and sweep trace be the different layers metal and between be separated with insulating medium layer, said data line bit is in sweep trace top, both are divided into the viewing area a plurality of pixel regions of array arrangement; In each pixel region, include thin film transistor (TFT) 110 and pixel electrode, public electrode, said public electrode and sweep trace are with one deck metal.
Said pixel electrode and public electrode have overlapping region to form MM CAP 1213, form two pole plates up and down of MM CAP 1213 respectively at said overlapping region pixel electrode and public electrode, and the centre accompanies insulation course.
Concrete; Constitute shape zone, loop between said pixel electrode and the public electrode; Said pixel electrode is divided into first pixel electrode 1201 and second pixel electrode 1202; And the top of said pixel electrode is provided with has first transparency electrode 120, and said first transparency electrode 120 is with first pixel electrode 1201 and second pixel electrode, 1202 electrical connection and said first transparency electrode 120 and first pixel electrode 1201 and second pixel electrode, 1202 equipotentials.
Said public electrode also is divided into first public electrode 1301 and second public electrode 1302; And said public electrode top is provided with has second transparency electrode 130; Said second transparency electrode 130 is electrically connected first public electrode 1301 and second public electrode 1302 and said second transparency electrode 130 and first public electrode 1301 and second public electrode, 1302 equipotentials, and said first public electrode 1301 and second public electrode 1302 lay respectively at the outside of first pixel electrode 1201 and second pixel electrode 1202.
Add pixel voltage for first pixel electrode 1201 and second pixel electrode 1202; Add common electric voltage for first public electrode 1301 and second public electrode 1302; Said first transparency electrode 120 also has pixel voltage simultaneously; Said second transparency electrode 130 also has common electric voltage, forms the required transverse electric field of coplane conversion type liquid crystal display device drives liquid crystal molecules horizontal deflection between first transparency electrode 120 that just can be in pixel region and second transparency electrode 130.
Array structure among Fig. 4 has 2 row, 2 row, is merely signal.Wherein, The grid of the thin film transistor (TFT) 110 in every capable pixel region is corresponding to be electrically connected with a sweep trace; The source electrode of the thin film transistor (TFT) 110 in every row pixel region is corresponding to be electrically connected with a data line, and the drain electrode of each thin film transistor (TFT) 110 is electrically connected with the interior pixel electrode of this pixel region through via hole 121.Concrete connected mode is identical with prior art, and the common practise as those skilled in the art repeats no more here.
In addition, in the viewing area, also comprise the multi-strip scanning connecting line: scanning connecting line 202, scanning connecting line 203 etc., said scanning connecting line is electrically connected sweep trace with external drive chip (not shown on the figure).
Concrete, in the present embodiment, said scanning connecting line and data line, pixel electrode are that same metal level etching forms, the material of said metal level can be aluminium or molybdenum aluminium alloy.Said scanning connecting line is arranged in parallel between first pixel electrode and second pixel electrode and with first pixel electrode and second pixel electrode.Concrete, with reference to figure 4, scanning connecting line 202 is arranged in parallel between first pixel electrode 1201 and second pixel electrode 1202 and with first pixel electrode 1201 and second pixel electrode 1202.
What above scanning connecting line 202, also be provided with has an insulation course; The top of said insulation course also is provided with has second transparency electrode 130; Said second transparency electrode 130 and first public electrode 1301, second public electrode 1302 are equipotential, said second transparency electrode 130 between first pixel electrode 1201 and second pixel electrode 1202 and with the required transverse electric field of its formation coplane conversion type liquid crystal display device drives liquid crystal molecules horizontal deflection.
Said scanning connecting line 202 be positioned at second transparency electrode 130 the below and with its electrical isolation, the live width of said scanning connecting line 202 makes it covered by second transparency electrode 130 less than the width of second transparency electrode 130.The benefit that is provided with like this is: the voltage that said transparency electrode 130 can shield on the scanning connecting line 202 impacts the deflection of liquid crystal molecule.Scanning connecting line 202 is positioned at the below of second transparency electrode 130; Rather than be positioned at the below of pixel electrode or first transparency electrode 120; Avoided existing stray capacitance excessive between scanning connecting line and pixel electrode or first transparency electrode 120, influenced display effect, for example scintillation.
Each bar scanning connecting line directly is connected through via hole in the viewing area with corresponding sweep trace: for example scan connecting line 202 and be connected through via hole 141 with sweep trace 101, scanning connecting line 203 is connected through via hole 142 with sweep trace 103.
For the structure of above-mentioned via hole is described better, please refer to Fig. 5, be the cross-sectional view of array base palte shown in Figure 4 along the A-B hatching line.Because said sweep trace is a underlying metal, therefore said scanning connecting line is positioned at the top of sweep trace.With via hole 141 is example, has insulating medium layer between said scanning connecting line 202 and the sweep trace 101, but at via hole 141 places, sweep trace 101 has been exposed in the bottom.When the surface deposition metal level at said insulating medium layer, said metal will fill up via hole 141.Graphical then said metal level forms scanning connecting line 202, just makes said scanning connecting line 202 directly be connected in via hole 141 with sweep trace 101.
Said second transparency electrode, 130 belows that are positioned at of present embodiment; By the scanning connecting line of second transparency electrode, 130 coverings; Make sweep trace be electrically connected with outside chip for driving; Thereby the drive signal of scanning drive chip is transferred on the sweep trace, choose the pixel region of corresponding line, control the unlatching of thin film transistor (TFT) 110 in each pixel region or close.
As preferred scheme, in the present embodiment, said scanning connecting line and data line are with one deck metal; And be arranged in parallel; Can utilize same metallic layer graphic to complete, thereby simplify the structure of array base palte, and reduce the manufacture craft difficulty of array base palte.Further preferred, said scanning connecting line can equate with the length of data line in the viewing area, can keep the homogeneity that pixel shows in the viewing area.
As preferred scheme, in the present embodiment, also the public electrode in each row neighbor district is interconnected.Because the public electrode of colleague's pixel region current potential when work is identical, the benefit that therefore is provided with like this is to simplify the connection of public electrode, avoids taking the area of more viewing area, thereby improves aperture opening ratio.Further, said public electrode can adopt DC driven in the course of work of liquid crystal indicator, to avoid and below it, to be produced crosstalking of voltage between the scanning connecting line that it covered.
For making the array base palte of said structure, present embodiment also provides corresponding method for making.Fig. 6 to Figure 17 is the diagrammatic cross-section of said each step of method for making of present embodiment; Corresponding with it, Fig. 6 a to Figure 17 a is the schematic top plan view of said method for making part steps, and its Vertical Centre Line is A '-B ' hatching line.For ease of explanation, metal level only is shown in the above-mentioned schematic top plan view, and has omitted the insulating medium structure.In addition, following synoptic diagram and not drawn on scale, emphasis only is to illustrate the purport of method for making of the present invention.For clarity sake, amplified the size of layer, and each structure has been numbered again with the zone.
At first, shown in figure 6 and vertical view Fig. 6 a thereof, glass substrate 400 is provided, said glass substrate 400 is divided into viewing area and frame region, and said frame region is surrounded said viewing area.Be simplified illustration, subsequent figures only illustrates the section or the schematic top plan view of viewing area.
With reference to shown in Figure 7, form the first metal layer 500 on the surface of said glass substrate 400, said the first metal layer can utilize physical vapor deposition (PVD) or chemical vapor deposition (CVD) or metal organic compound chemical vapor deposition methods such as (MOCVD) to form.
Shown in figure 8 and vertical view Fig. 8 a thereof; Adopt the first road mask; Use photoetching process; Graphical said the first metal layer 500 forms the grid 501 of plurality of thin film transistor, the sweep trace 502 that is electrically connected with said grid and as the public electrode 503 (an other electrode is a pixel electrode) of the electrode of MM CAP.Said sweep trace 502 is electrically connected with grid 501 with the thin film transistor (TFT) of delegation's pixel region, is used to choose this row pixel, is parallel to each other between each bar sweep trace 502.Said MM CAP is used for stored charge, so that liquid crystal indicator when work, the demonstration that between the consecutive frame picture, keeps pixel.
With reference to shown in Figure 9, form first insulating medium layer 600 on the surface of structure shown in Figure 8.Said first insulating medium layer 600 can utilize chemical vapor deposition to form, and material can be conventional insulating material such as silicon nitride, monox or silicon oxynitride.
With reference to shown in Figure 10, adopt the surface of the second road mask, said first insulating medium layer 600 of photoetching process etching to form first via hole 801.Said sweep trace 502 is exposed in the bottom of said first via hole 801.And said first insulating medium layer 600 is positioned at the part on grid 501 surfaces, can be used as the gate dielectric layer of thin film transistor (TFT).
With reference to shown in Figure 11; On the basis of structure shown in Figure 10; Form amorphous silicon layer 601, doped amorphous silicon layer 602 continuously; Adopt the island zone of the 3rd road mask, photoetching process etching amorphous silicon layer 601, doped amorphous silicon layer 602 formation thin film transistor (TFT)s then, expose the sweep trace 502 of first via hole 801 and bottom thereof simultaneously.Wherein, amorphous silicon layer 601 can be used to form the active layer of thin film transistor (TFT), for example source-drain electrode and between conducting channel; And doped amorphous silicon layer 602 is used for being convenient to be electrically connected with the data line or the pixel electrode of follow-up formation with said source-drain electrode formation Ohmic contact.
With reference to shown in Figure 12; On the basis of structure shown in Figure 11, form second metal level 700, said second metal level 700 also can utilize physical vapor deposition (PVD) or chemical vapor deposition (CVD) or metal organic compound chemical vapor deposition methods such as (MOCVD) to form.Said second metal level 700 is filled in first via hole 801 and directly is connected with sweep trace 502.
Shown in Figure 13 and vertical view Figure 13 a thereof; Adopt the 4th road mask, graphical said second metal level 700 of photoetching process to form some data lines 701, scanning connecting line 702 and source electrode 703 and drain 704, also form first pixel electrode and second pixel electrode that is connected with said drain electrode 704 simultaneously.
Wherein, During etching second metal level 700; Over etching can be carried out in island zone at thin film transistor (TFT), doped amorphous silicon layer 602 etchings is broken off, and expose the amorphous silicon layer 601 that is positioned at its below; Simultaneously amorphous silicon 601 also can be fallen a part by over etching, makes source electrode 703 and drain electrode 704 mutually insulateds like this.
The source electrode 703 of the thin film transistor (TFT) in every data line 701 and the same column pixel region is connected.Vertical each other between said many data lines 701 and its below multi-strip scanning line 502, the formation quadrature promptly can demarcate each pixel region.
Said scanning connecting line 702 laterally arranges with data line 701, and in the viewing area both equal in length.Said scanning connecting line 702 in first via hole 801 with it below corresponding sweep trace 502 directly be connected.
With reference to shown in Figure 14, form second insulating medium layer 800 on the surface of structure shown in Figure 13, said second insulating medium layer 800 also can utilize chemical vapor deposition to form, and material can be conventional insulating material such as silicon nitride, monox or silicon oxynitride.
With reference to shown in Figure 15, adopt the 5th road mask, said second insulating medium layer 800 of photoetching process etching to form second via hole 802 that exposes said thin film transistor (TFT) drain electrode 704.
With reference to shown in Figure 16, at the surface deposition indium tin oxide layer 900 of said second insulating medium layer 800.Can utilize chemistry or physical vapour deposition (PVD) to form.Above-mentioned indium tin oxide layer 900 also is filled in second via hole 802, is connected with drain electrode 704.
Shown in Figure 17 and vertical view 17a thereof, adopt the 6th road mask, the said indium tin oxide layer 900 of photoetching process etching to form first transparency electrode 901 and second transparency electrode 902.Said first transparency electrode 901 directly is connected with drain electrode 704 in said second via hole 802, and then is electrically connected with first pixel electrode and second pixel electrode, realizes equipotential.
Said second transparency electrode 902 also is electrically connected through the via hole (not shown) with said public electrode 503, and the said scanning connecting line 702 of said second transparency electrode, 902 coverings, and its width is greater than the live width of said scanning connecting line 702.Second transparency electrode 902 in colleague and the adjacent pixels district can interconnect.
The material of above-mentioned in addition first transparency electrode 901 and second transparency electrode 902 can also adopt zinc paste except using tin indium oxide.Only needing to replace above-mentioned indium tin oxide layer 900 at the surface deposition zinc oxide film of second insulating medium layer 800 gets final product.
Through above-mentioned manufacture craft, just formed the described array base palte of present embodiment.
Second embodiment
In the above-described embodiments, the scanning connecting line directly is connected through via hole in the viewing area with sweep trace, when the manufacturing of reality, and the restriction of being connected up easily.As another optional embodiment, said scanning connecting line and sweep trace can also connect through position via hole and other layers intermetallic that is positioned at via hole on it in succession.
Concrete, with reference to shown in Figure 180, be the array base palte plan structure synoptic diagram of second embodiment of the invention.Figure 18 and Fig. 4 is relatively more visible, and the difference of the present embodiment and first embodiment only is: the syndeton between scanning connecting line and the sweep trace connects via other metal interlevels in succession.
Above-mentioned syndeton please refer to Figure 19 for better explaining, be the cross-sectional view of array base palte shown in Figure 180 along the C-C line.Is example with sweep trace 101 with the syndeton that scans connecting line 202, the bridge joint metal level 160 that said syndeton comprises the via hole 151 that is positioned on the sweep trace 101 and is positioned at the via hole 152 on the scanning connecting line 202 and deposits and cover above-mentioned via hole.
Because scanning connecting line 202 is not to be positioned at one deck metal with sweep trace 101; Therefore can corresponding sweep trace 101 and scanning connecting line 202 be led on the same bridge joint metal level 160 through via hole 151 and the via hole 152 that is filled with metal; Utilize the bridge joint metal level 160 that covers via hole, will scan connecting line 202 and be electrically connected with sweep trace 101.Said via hole 151 has penetrated between scanning connecting line 202 and the sweep trace 101 and the insulating medium layer that scans connecting line 202 surfaces; Via hole 152 has then only penetrated the insulating medium layer on scanning connecting line 202 surfaces, and 160 of said bridge joint metal levels can be made at the top of array base palte separately.Above-mentioned via hole all need be avoided pixel electrode and public electrode when making, to avoid interference the demonstration of pixel.
For making the array base palte of present embodiment, the method for making of respective array substrate is provided also.Because present embodiment and first embodiment difference only are to scan the syndeton between connecting line and the sweep trace.The formation technology of relevant connection structure is only described therefore.Please refer to Figure 20 to Figure 23, be the synoptic diagram of the said method for making of present embodiment.Be simplified illustration, present embodiment is the basis with the diagrammatic cross-section of the first embodiment method for making.
At first omit in the method for making of first embodiment about the relative production technology of first via hole, form array base-plate structure shown in Figure 20.Shown in figure 20, different with first embodiment, completely cut off by first insulating medium layer 140 between said scanning connecting line 202 and the sweep trace 101, both are separate metal level.
With reference to shown in Figure 21, form the 3rd insulating medium layer 150 on the surface of structure shown in Figure 20, the material of said the 3rd insulating medium layer 150 can be identical with first insulating medium layer 600, adopts chemical vapor deposition to form.
With reference to shown in Figure 22, aim at the scanning connecting line 702 and the sweep trace 502 of bottom, adopt different mask, photoetching process, etching forms and is positioned at the via hole 151 on the sweep trace 101 and is positioned at the via hole 152 on the scanning connecting line 202 respectively.When forming above-mentioned via hole, need avoid penetrating pixel electrode, common electrode layer and other metal levels.
With reference to shown in Figure 23, form bridge joint metal level 160 on the surface of said the 3rd insulating medium layer 150, said bridge joint metal level 160 is connected with sweep trace 101 in via hole 151 respectively, in via hole 152, is connected with scanning connecting line 202.The final said syndeton of present embodiment that forms.
Present embodiment and the first embodiment difference only are not make at needs to be connected first via hole that scans connecting line and sweep trace, those skilled in the art should be easily according to the disclosed scheme of first embodiment push away the practical implementation method of all the other steps.
The 3rd embodiment
Among the above embodiment; The scanning connecting line is all between first pixel electrode and second pixel electrode, i.e. the center of pixel region is as the optional embodiment of another kind; Said scanning connecting line can also be positioned at a side of pixel region, and closes on the data line in neighbor district.
Figure 24 is the plan structure synoptic diagram of the array base palte of third embodiment of the invention.In conjunction with Figure 24 and shown in Figure 4, the difference of the present embodiment and first embodiment only is that said scanning connecting line is between the data line in pixel electrode and neighbor district.Concrete, scan connecting line 202 between first pixel electrode 1201 and data line 104, and be in second transparency electrode, 130 belows and parallel with data line 104; Scanning connecting line 203 and is in second transparency electrode, 130 belows and parallel with data line 106 equally between first pixel electrode 1201 and adjacent data line 106.
Present embodiment is similar with first example structure, has only changed the position of scanning connecting line, and therefore forming technology does not have bigger difference, only needs when graphical respective metal layers forms the scanning connecting line, and change domain figure gets final product.Those skilled in the art should be easily according to the disclosed scheme of first embodiment push away the formation technology of present embodiment.
To sum up, array base palte provided by the invention will scan connecting line and be arranged at the viewing area, through the scanning connecting line sweep trace will be electrically connected with the external drive chip.Because frame region need not to be provided with the scanning connecting line, thereby has reduced the scanning connecting line area of frame region, has improved the area of viewing area, has improved the utilization factor of glass substrate.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical scheme of the present invention according to technical spirit of the present invention.
Claims (20)
1. the array base palte of a coplane conversion type liquid crystal display device, the frame region that comprises the viewing area and surround said viewing area is characterized in that, said viewing area comprises:
The data line and the sweep trace of many quadratures and mutually insulated;
Said many data lines and sweep trace are divided into the viewing area pixel region of a plurality of array arrangements; Comprise pixel electrode, public electrode, thin film transistor (TFT) in each pixel region, also comprise be arranged on the pixel electrode and with equipotential first transparency electrode of pixel electrode be arranged on the public electrode also and equipotential second transparency electrode of public electrode;
Also comprise the multi-strip scanning connecting line, each bar sweep trace of correspondence be electrically connected with the external drive chip that said second transparency electrode also is positioned on the said scanning connecting line.
2. array base palte as claimed in claim 1 is characterized in that said public electrode and pixel electrode have overlapping, is used to constitute MM CAP.
3. array base palte as claimed in claim 1 is characterized in that, said scanning connecting line and data line laterally arrange.
4. array base palte as claimed in claim 3 is characterized in that, said scanning connecting line and data line equal in length in the viewing area.
5. array base palte as claimed in claim 1 is characterized in that, said scanning connecting line and data line are with one deck metal.
6. array base palte as claimed in claim 1 is characterized in that, the live width of said scanning connecting line is less than the width of second transparency electrode of its top, and is covered by said second transparency electrode.
7. array base palte as claimed in claim 1 is characterized in that, said scanning connecting line is connected in the viewing area with sweep trace.
8. array base palte as claimed in claim 7 is characterized in that, the insulating medium layer that is formed with via hole is set between said scanning connecting line and the sweep trace, and said scanning connecting line directly is connected with the scanning connecting line in via hole.
9. array base palte as claimed in claim 7 is characterized in that, said scanning connecting line and sweep trace connect through position via hole and other layers intermetallic that is positioned at via hole on it in succession.
10. array base palte as claimed in claim 1 is characterized in that, said pixel electrode is divided into first pixel electrode and second pixel electrode, and said scanning connecting line is between first pixel electrode and second pixel electrode.
11. array base palte as claimed in claim 10 is characterized in that, said public electrode is divided into first public electrode and second public electrode, and said first public electrode and second public electrode lay respectively at the outside of first pixel electrode and second pixel electrode.
12. array base palte as claimed in claim 1 is characterized in that, said scanning connecting line is between the data line in pixel electrode and neighbor district.
13. array base palte as claimed in claim 1 is characterized in that, the material of said first transparency electrode and second transparency electrode is tin indium oxide or zinc paste.
14. array base palte as claimed in claim 1 is characterized in that, the public electrode in colleague and the adjacent pixels district interconnects.
15. array base palte as claimed in claim 1 is characterized in that, said public electrode adopts direct voltage drive.
16. array base palte as claimed in claim 1 is characterized in that, the grid of the thin film transistor (TFT) in every capable pixel region is corresponding to be electrically connected with a sweep trace; The source electrode of the thin film transistor (TFT) in every row pixel region is corresponding to be electrically connected with a data line, and drain electrode is corresponding to be electrically connected with the interior pixel electrode of this pixel region.
17. a coplane conversion type liquid crystal display device comprises liquid crystal layer and color membrane substrates, it is characterized in that, also comprises arbitrary described array base palte like claim 1-16, said liquid crystal layer is between said array base palte and color membrane substrates.
18. the method for making of an array base palte is characterized in that, comprising:
Substrate is provided, the frame region that said substrate is divided into the viewing area and surrounds said viewing area;
In said viewing area, form the first metal layer, and adopt the first road mask, the graphical said the first metal layer of photoetching process to form the grid of thin film transistor (TFT), sweep trace and the public electrode that is connected with said grid;
Form first insulating medium layer;
Adopt the second road mask, said first insulating medium layer of photoetching process etching forms first via hole, and said first via hole exposes said sweep trace;
Form amorphous silicon layer, doped amorphous silicon layer, and adopt the 3rd road mask, photoetching process etching to form the active layer of said thin film transistor (TFT);
Form second metal level; Adopt the 4th road mask, graphical said second metal level of photoetching process to form the source-drain electrode metal of data line, pixel electrode, scanning connecting line and thin film transistor (TFT); Said data line is connected with the source metal of thin film transistor (TFT), and said scanning connecting line directly is connected with sweep trace in first via hole;
Form second insulating medium layer, adopt the 5th road mask, said second insulating medium layer of photoetching process etching to form second via hole that exposes said thin film transistor (TFT) drain metal;
Said data line and sweep trace are divided into the viewing area pixel region of array arrangement; Form first transparency electrode and second transparency electrode on the said structure surface; Said first transparency electrode is connected with the drain electrode of thin film transistor (TFT) in second via hole, and said second transparency electrode covers the scanning connecting line and the public electrode of its below.
19. the method for making of array base palte as claimed in claim 18; It is characterized in that; Said formation first transparency electrode and second transparency electrode comprise: at the said second insulating medium layer surface deposition electrode material, adopt the 6th road mask, photoetching process in said pixel region, to form first transparency electrode and second transparency electrode simultaneously.
20. the method for making of array base palte as claimed in claim 18 is characterized in that, said electrode material is tin indium oxide or zinc paste.
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