CN114185458A - Display device and display panel thereof - Google Patents

Display device and display panel thereof Download PDF

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Publication number
CN114185458A
CN114185458A CN202111504272.1A CN202111504272A CN114185458A CN 114185458 A CN114185458 A CN 114185458A CN 202111504272 A CN202111504272 A CN 202111504272A CN 114185458 A CN114185458 A CN 114185458A
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China
Prior art keywords
layer
pixel electrode
array substrate
display panel
common electrode
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Granted
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CN202111504272.1A
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Chinese (zh)
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CN114185458B (en
Inventor
陆志涛
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TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Abstract

The embodiment of the application discloses display device and display panel thereof, wherein, display panel includes: a pixel electrode and an array substrate side common electrode. The array substrate side public electrode is arranged right opposite to the pixel electrode, the periphery of the array substrate side public electrode is wider than the pixel electrode, and a transparent conducting layer is arranged in a region where the array substrate side public electrode is right opposite to the pixel electrode. In the embodiment of the application, the transparent conducting layer opposite to the pixel electrode is arranged on the array substrate side common electrode, and the transparent conducting layer is opposite to the pixel electrode.

Description

Display device and display panel thereof
Technical Field
The application relates to the field of display, in particular to display equipment and a display panel thereof.
Background
The liquid crystal display panel, referred to as a liquid crystal panel for short, has many advantages of thin body, power saving, no radiation, etc., and is widely used, for example: liquid crystal televisions, smart phones, digital cameras, tablet computers, computer screens, or notebook computer screens, etc., are dominant in the field of flat panel displays.
The liquid crystal display panel is composed of a color film substrate, a thin film transistor array substrate and a liquid crystal layer arranged between the two substrates. The liquid crystal display panel is internally provided with a plurality of pixels which are arranged in an array mode, and when driving voltage is applied to the two substrates, each pixel displays under the driving of the pixel circuit.
For a vertically aligned liquid crystal display panel, the touch surface can be placed only on the array substrate side due to the presence of the common electrode on the entire color film substrate side. Therefore, the common electrode on the array substrate side can be reused as the touch electrode plate. However, the touch electrode plate has a small area and a small inductive capacitance with a finger, which results in limited touch performance.
Disclosure of Invention
The embodiment of the application provides a display device and a display panel thereof, which can solve the technical problem that after an array substrate side common electrode is reused as a touch electrode plate in the prior art, the touch electrode plate has a small area and small inductive capacitance with fingers, so that the touch performance is limited.
An embodiment of the present application provides a display panel, including:
a pixel electrode;
the array substrate side common electrode is arranged right opposite to the pixel electrode and is wider at the periphery than the pixel electrode, and a transparent conducting layer is arranged in a region where the array substrate side common electrode is right opposite to the pixel electrode.
In some embodiments of the present application, the array substrate-side common electrode includes:
the metal lattice layer is arranged opposite to the pixel electrode, and an opening is formed in the area, opposite to the pixel electrode, of the metal lattice layer;
and the transparent conducting layer is arranged right opposite to the opening and is in electrical signal connection with the metal grid layer.
In some embodiments of the present application, the transparent conductive layer is disposed on a side of the metal lattice layer facing the pixel electrode, and covers the opening.
In some embodiments of the present application, the transparent conductive layer is disposed on a side of the metal lattice layer facing away from the pixel electrode, and covers the opening.
In some embodiments of the present application, the transparent conductive layer is embedded in the opening and forms at least one gap with the metal grid layer.
In some embodiments of the present application, the transparent conductive layer comprises:
the main body layer is arranged on one side of the metal grid layer and covers the opening;
and the embedded layer is arranged on one surface of the main body layer facing the metal lattice layer and is embedded into the opening so as to connect the main body layer with the metal lattice layer.
In some embodiments of the present application, at least one gap is formed between the embedded layer and the metal lattice layer.
In some embodiments of the present application, two intersecting stripe-shaped holes are etched in a region of the array substrate side common electrode facing the pixel electrode.
In some embodiments of the present application, two first stripe holes disposed opposite to each other and a second stripe hole disposed vertically between the two first stripe holes are etched in a region of the array substrate side common electrode facing the pixel electrode.
Correspondingly, an embodiment of the present application further provides a display device, including:
a housing;
the display panel as described above, which is mounted in the housing.
In the embodiment of the application, the transparent conducting layer opposite to the pixel electrode is arranged on the array substrate side common electrode, and the transparent conducting layer is opposite to the pixel electrode.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display device provided in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a display panel provided in an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of an array substrate-side common electrode provided in the first embodiment of the present application.
Fig. 5 is a schematic structural diagram of a metal lattice layer provided in an embodiment of the present application.
Fig. 6 is a schematic structural diagram of an array substrate-side common electrode provided in a second embodiment of the present application.
Fig. 7 is a schematic structural diagram of an array substrate-side common electrode provided in a third embodiment of the present application.
Fig. 8 is a schematic structural view of an array substrate-side common electrode provided in a fourth embodiment of the present application.
Fig. 9 is a schematic structural view of an array substrate-side common electrode provided in a fifth embodiment of the present application.
Fig. 10 is a schematic structural view of an array substrate-side common electrode provided in a sixth embodiment of the present application.
Fig. 11 is a schematic structural view of an array substrate-side common electrode provided in a seventh embodiment of the present application.
Fig. 12 is a schematic structural view of an array substrate-side common electrode provided in an eighth embodiment of the present application.
Description of reference numerals:
10. a display panel; 20. a housing; 100. a glass panel; 200. a first metal layer; 300. a first insulating layer; 400. a second metal layer; 500. a second insulating layer; 600. a pixel electrode; 210. a gate layer; 220. an array substrate-side common electrode; 410. a source layer; 420. a drain layer; 430. reading a wire layer; 401. a silicon base layer; 221. a transparent conductive layer; 222. a metal grid layer; 224. a strip-shaped hole; 225. a first bar-shaped hole; 226. a second bar-shaped hole; 2211. a body layer; 2212. an embedding layer; 2221. an opening; 2201. a gap.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a display device and a display panel 10 thereof. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The present application provides a display device that can be mounted in various products having a display function. For example, the electronic product may be a smart terminal, a notebook computer, a photographing apparatus, a wearable apparatus, an electronic scale, a vehicle-mounted display, a television, and the like.
Referring to fig. 1 and 2, the display device includes a housing 20 and a display panel 10 installed in the housing 20. The display panel 10 includes a glass panel 100, a first metal layer 200, a first insulating layer 300, a second metal layer 400, a second insulating layer 500, and a pixel electrode 600. The first metal layer 200 is disposed on a side of the glass panel 100, the first insulating layer 300 is disposed on a side of the first metal layer 200 away from the glass panel 100, the second metal layer 400 is disposed on a side of the first insulating layer 300 away from the first metal layer 200, the second insulating layer 500 is disposed on a side of the second metal layer 400 away from the silicon-based layer 401, and the pixel electrode 600 is disposed on a side of the second insulating layer 500 away from the second metal layer 400.
Referring to fig. 3, the first metal layer 200 includes a gate layer 210 and an array substrate-side common electrode 220 disposed at the same layer. The array substrate-side common electrode 220 is disposed opposite to the pixel electrode 600 and is wider at the periphery than the pixel electrode 600 to cover the pixel electrode 600. The gate layer 210 is provided on one side of the array substrate-side common electrode 220, and is isolated from the array substrate-side common electrode 220 by a first insulating layer 300.
The second metal layer 400 includes a source layer 410, a drain layer 420, and a read line layer 430, which are disposed in the same layer. The read line layer 430 is disposed on a side opposite to the array substrate side common electrode 220, and is electrically connected to the array substrate side common electrode 220 through the first insulating layer 300 to output a touch signal of the display panel 10 from the array substrate side common electrode 220 to a corresponding processing module for processing. A silicon-based layer 401 is further disposed between the source layer 410, the drain layer 420 and the first insulating layer 300, and the silicon-based layer 401 is disposed opposite to the gate layer 210. The drain layer 420 is disposed on a side of the silicon substrate 401 facing the read line layer 430 and isolated from the read line layer 430 by the second insulating layer 500, and the source layer 410 is disposed on a side of the silicon substrate 401 facing away from the read line layer 430 and isolated from the drain layer 420 by the second insulating layer 500.
The pixel electrode 600 is electrically connected to the drain layer 420 through the second insulating layer 500, and the region thereof facing the array substrate-side common electrode 220 is shielded by the array substrate-side common electrode 220 to form a storage capacitor together with the array substrate-side common electrode 220.
In an embodiment of the present application, referring to fig. 4, the array substrate-side common electrode 220 includes a transparent conductive layer 221. The transparent conductive layer 221 is made of a transparent conductive material and is disposed opposite to the pixel electrode 600, and since the transparent conductive layer 221 is transparent, the pixel point is not shielded under the condition of covering the pixel electrode 600, and the display is not affected. Meanwhile, compared with the scheme that the area of the common electrode on the array substrate side, which is just opposite to the pixel electrode 600, in the common electrode on the array substrate side is hollowed out in the prior art, the area of the common electrode on the array substrate side serving as a touch electrode plate is increased, and further touch capacitance is increased, so that the technical problem that after the common electrode on the array substrate side is reused as the touch electrode plate in the prior art, the area of the touch electrode plate is small, and the sensing capacitance of a finger is small, so that the touch performance is limited is solved. The array substrate side common electrode 220 and the pixel electrode 600 jointly form a storage capacitor, and the increase of the overlapping area of the array substrate side common electrode 220 and the pixel electrode 600 can also increase the storage capacitor, so that the crosstalk generated on the picture display by the array substrate side common electrode 220 under the influence of voltage jump is avoided, and the display effect is further optimized.
In some embodiments of the present application, the transparent conductive layer 221 is made of Indium Tin Oxide (ITO). The ITO has good transparency and high conductivity, and can keep good conductivity on the premise of ensuring the display effect.
In some embodiments of the present application, the array substrate side common electrode includes only the transparent conductive layer 221 using an ITO material. The transparent conductive layer 221 directly contacts the read line layer 430, and realizes electrical signal connection, so that the touch signal of the display panel 10 is output to the relevant processing module through the read line layer 430 for processing. When the array substrate side common electrode is made of transparent electrode materials such as ITO, the transparent area on the array substrate side common electrode can be maximized, and then the transparent area is matched with the pixel points with larger size, so that the display effect of the whole display panel 10 is improved.
In other embodiments of the present application, referring to fig. 5, the array substrate-side common electrode 220 further includes a metal lattice layer 222 in addition to the transparent conductive layer 221.
The metal lattice layer 222 is disposed opposite to the pixel electrode 600, and an opening 2221 is disposed in an area opposite to the pixel electrode 600. The metal lattice layer 222 contacts the read line layer 430 and makes electrical signal connections. Transparent conductive layer 221 is disposed opposite opening 2221 and is in electrical signal connection with metal grid 222. In this embodiment, the metal lattice layer 222 is made of a material with good conductivity, such as copper and silver, and the transparent conductive layer 221 is electrically connected to the read line layer 430 through the metal lattice layer 222, so that the conductivity of the common electrode 220 on the whole array substrate side is improved, and the touch sensitivity of the display panel 10 is ensured. Meanwhile, since the metal lattice layer 222 is provided with the opening 2221 in the area facing the pixel electrode 600, the pixel is not shielded, and the display effect is not affected.
In the embodiment of the present application, please refer to fig. 4, the transparent conductive layer 221 and the metal lattice layer 222 are disposed on the same layer, the transparent conductive layer 221 is embedded in the opening 2221, and the outer sidewall of the transparent conductive side contacts with the inner sidewall of the metal lattice layer 222 to realize electrical signal connection. In the embodiment, the transparent conductive layer 221 and the metal grid layer 222 are disposed on the same layer, so that the thickness of the display panel 10 is not increased, and the transparent conductive layer 221 is embedded in the opening 2221, so that the transparent conductive layer 221 can be directly fixed in the metal grid layer 222.
In some embodiments of the present application, referring to fig. 6, a plurality of trenches are etched on the outer sidewall of the transparent conductive layer 221, so that at least one gap 2201 is formed between the transparent conductive layer 221 and the metal lattice layer 222, so as to reduce the overlapping area between the array substrate-side common electrode 220 and the pixel electrode 600, and avoid the storage capacitor from being too high, which may result in a long time to charge the storage capacitor in the frame idle stage, and especially in a case where the frame idle time is short in the high frame rate mode, the storage capacitor may be too high, which may result in too little charge amount of the storage capacitor and affect the display effect.
In other embodiments of the present application, referring to fig. 7, the transparent conductive layer 221 is disposed on a side of the metal grid layer 222 away from the pixel electrode 600, and covers the opening 2221. In this embodiment, the periphery of the transparent conductive layer 221 may be flush with the periphery of the metal lattice layer 222, so as to increase the contact area with the metal lattice layer 222 and ensure the conductivity of the array substrate-side common electrode 220. Meanwhile, the transparent conductive layer 221 is overlapped on one side of the metal lattice layer 222 away from the pixel electrode 600, so that the transparent conductive layer is closer to the glass panel 100 which can be touched by a finger and farther from the pixel electrode 600, and the capacitance of the transparent conductive layer is smaller as the distance between the two electrode plates is larger, so that the structure of the embodiment can increase the touch capacitance between the array substrate side common electrode 220 and the finger and reduce the storage capacitance between the pixel electrode 600 and the array substrate side common electrode 220. When the touch sensitivity of the display panel 10 is improved, the storage capacitor is controlled within a reasonable range, the phenomenon that the storage capacitor is too small, the array substrate side common electrode 220 is easily affected by voltage jump and generates crosstalk on image display, and then the display effect is affected is avoided, the phenomenon that the storage capacitor is too large, the storage capacitor needs to be charged for a long time in a frame idle stage is also avoided, especially, the display effect is affected due to the fact that the storage capacitor is too high and the storage capacitor is too small in charging amount under a high frame rate mode.
In still other embodiments of the present application, referring to fig. 8, the transparent conductive layer 221 is disposed on a side of the metal grid layer 222 facing the pixel electrode 600, and covers the opening 2221. In this embodiment, the periphery of the transparent conductive layer 221 may be flush with the periphery of the metal lattice layer 222, so as to increase the contact area with the metal lattice layer 222 and ensure the conductivity of the array substrate-side common electrode 220. Meanwhile, in the present embodiment, the transparent conductive layer 221 is disposed on a side of the metal lattice layer 222 facing the pixel electrode 600. That is, the metal grid layer 222 is disposed on one side of the glass panel 100, and the transparent conductive layer 221 is disposed on one side of the metal grid layer 222 away from the glass panel 100. When assembling, the metal grid layer 222 is firstly arranged on the glass panel 100, then the transparent conductive layer 221 is arranged on the metal grid layer 222, and the metal grid layer 222 can be used as a positioning mark for mounting the transparent conductive layer 221 and even a scanning line layer and a pixel electrode 600 at the back, so that the subsequent assembling process can be more accurate, and the tolerance in the assembling process is reduced.
In some embodiments of the present application, referring to fig. 9 in combination, the transparent conductive layer 221 includes a body layer 2211 and an embedded layer 2212, the embedded layer 2212 is disposed on one side of the body layer 2211, and the periphery of the embedded layer 2212 is narrower than the body layer 2211. The embedding layer 2212 is embedded in the opening 2221 of the metal lattice layer 222 and abuts against the inner side surface of the metal lattice layer 222, thereby achieving connection with the metal lattice layer 222. The main body layer 2211 is located on one side of the metal grid layer 222, and overlaps the metal grid layer 222 and covers the opening 2221. In this embodiment, the contact area between the transparent conductive layer 221 and the metal lattice layer 222 is larger, increasing the conductive performance of the array substrate-side common electrode 220. Meanwhile, by embedding the embedding layer 2212 into the opening 2221 of the metal lattice layer 222, a firm connection with the metal lattice layer 222 can also be achieved.
In some embodiments of the present application, referring to fig. 10, a plurality of trenches are etched on the outer sidewall of the embedded layer 2212, so that at least one gap 2201 is formed between the embedded layer 2212 and the metal lattice layer 222, so as to reduce the overlapping area between the array substrate-side common electrode 220 and the pixel electrode 600, and avoid the over-high storage capacitor, which may cause a long time to charge the storage capacitor in the frame idle stage, especially for the short frame idle time in the high frame rate mode, which may cause the too-high storage capacitor to have too little charge amount and affect the display effect.
In some embodiments of the present application, please refer to fig. 11 and 12 in combination, various patterns are etched in the region of the array substrate-side common electrode 220 facing the pixel electrode 600, so as to reduce the overlapping area between the array substrate-side common electrode 220 and the pixel electrode 600, thereby reducing the storage capacitance and avoiding the storage capacitance being too high, which may result in a long time to charge the storage capacitance in the frame idle stage, especially in the case of a short frame idle time in the high frame rate mode, which may result in too low charge amount of the storage capacitance and affect the display effect. Typically, the pattern is etched on the transparent conductive layer 221, which may also extend to the metal grid layer 222 in some embodiments. In one embodiment, the array substrate side common electrode 220 is etched with two intersecting bar-shaped holes 224 to form a cross-shaped pattern. In another embodiment, the array substrate-side common electrode 220 is etched with two first bar-shaped holes 225 disposed opposite to each other and a second bar-shaped hole 226 vertically disposed between the two first bar-shaped holes 225, and the two first bar-shaped holes 225 are communicated with each other by the second bar-shaped hole 226 to form a gate-shaped pattern or an i-shaped pattern.
The display device and the display panel 10 thereof provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A display panel, comprising:
a pixel electrode;
the array substrate side common electrode is arranged right opposite to the pixel electrode and is wider at the periphery than the pixel electrode, and a transparent conducting layer is arranged in a region where the array substrate side common electrode is right opposite to the pixel electrode.
2. The display panel according to claim 1, wherein the array substrate-side common electrode includes:
the metal lattice layer is arranged opposite to the pixel electrode, and an opening is formed in the area, opposite to the pixel electrode, of the metal lattice layer;
the transparent conducting layer is arranged opposite to the opening and is in electrical signal connection with the metal grid layer.
3. The display panel according to claim 2, wherein the transparent conductive layer is provided on a side of the metal lattice layer facing the pixel electrode and covers the opening.
4. The display panel according to claim 2, wherein the transparent conductive layer is disposed on a side of the metal grid layer facing away from the pixel electrode and covers the opening.
5. The display panel of claim 2, wherein the transparent conductive layer is embedded in the opening and forms at least one gap with the metal grid layer.
6. The display panel according to claim 2, wherein the transparent conductive layer comprises:
the main body layer is arranged on one side of the metal grid layer and covers the opening;
and the embedded layer is arranged on one surface of the main body layer facing the metal lattice layer and is embedded into the opening so as to connect the main body layer with the metal lattice layer.
7. The display panel of claim 6, wherein at least one gap is formed between the embedding layer and the metal lattice layer.
8. The display panel according to claim 1, wherein a region of the array substrate-side common electrode facing the pixel electrode is etched with two intersecting stripe holes.
9. The display panel according to claim 1, wherein a region of the array substrate side common electrode facing the pixel electrode is etched with two first stripe holes arranged oppositely, and a second stripe hole arranged vertically between the two first stripe holes, the second stripe hole communicating with the two first stripe holes.
10. A display device, comprising:
a housing;
the display panel of claims 1-9, the display panel mounted within the housing.
CN202111504272.1A 2021-12-10 2021-12-10 Display device and display panel thereof Active CN114185458B (en)

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CN114185458B CN114185458B (en) 2023-12-01

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