CN112242347A - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 124
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 58
- 238000005530 etching Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- 230000004048 modification Effects 0.000 claims description 17
- 238000012986 modification Methods 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 15
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000009832 plasma treatment Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000011261 inert gas Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- MGWGWNFMUOTEHG-UHFFFAOYSA-N 4-(3,5-dimethylphenyl)-1,3-thiazol-2-amine Chemical compound CC1=CC(C)=CC(C=2N=C(N)SC=2)=C1 MGWGWNFMUOTEHG-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- JCXJVPUVTGWSNB-UHFFFAOYSA-N nitrogen dioxide Inorganic materials O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WEAMLHXSIBDPGN-UHFFFAOYSA-N (4-hydroxy-3-methylphenyl) thiocyanate Chemical compound CC1=CC(SC#N)=CC=C1O WEAMLHXSIBDPGN-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- AVXURJPOCDRRFD-UHFFFAOYSA-N Hydroxylamine Chemical compound ON AVXURJPOCDRRFD-UHFFFAOYSA-N 0.000 description 1
- 229910017912 NH2OH Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 229910021355 zirconium silicide Inorganic materials 0.000 description 1
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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Abstract
一种半导体结构及其形成方法,方法包括:提供衬底;在所述衬底表面形成停止层;在所述停止层表面形成介电层;在所述介电层内形成第一开口,所述第一开口暴露出所述停止层表面;对所述第一开口底部的停止层进行改性处理,形成改性层;去除所述改性层,形成第二开口,所述第二开口暴露出所述衬底表面。所形成的半导体结构性能得到提高。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体结构及其形成方法。
背景技术
集成电路制造工艺是一种平面制作工艺,其结合光刻、刻蚀、沉积、离子注入等多种工艺,在同一衬底上形成大量各种类型的复杂器件,并将其互相连接以具有完整的电子功能。其中,任何一步工艺出现偏差,都可能会导致电路的性能参数偏离设计值。目前,随着超大规模集成电路的器件特征尺寸不断地等比例缩小,集成度不断地提高,对各步工艺的控制及其工艺结果的精确度提出了更高的要求。
因此,现有的集成电路制造工艺还有待改善。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法,以改善半导体结构的性能。
为解决上述技术问题,本发明技术方案提供一种半导体结构的形成方法,包括:提供衬底;在所述衬底表面形成停止层;在所述停止层表面形成介电层;在所述介电层内形成第一开口,所述第一开口暴露出所述停止层表面;对所述第一开口底部的停止层进行改性处理,形成改性层;去除所述改性层,形成第二开口,所述第二开口暴露出所述衬底表面。
可选的,对所述第一开口暴露出的所述停止层进行改性处理的工艺为等离子体处理工艺。
可选的,所述停止层的材料包括氮化铝、氧化铝或氮化硅;所述改性层的材料包括铝或氧化硅。
可选的,所述等离子处理工艺的气体包括:氢气和氩气的混合气体,所述氢气的体积比大于20%;或者,所述等离子处理工艺的气体为氧气。
可选的,去除所述改性层的工艺包括湿法刻蚀工艺;所述湿法刻蚀工艺采用的溶液包括:NH2OH溶液或者HF溶液。
可选的,所述衬底包括基底和位于基底上的隔离层,所述隔离层内具有互连结构,所述隔离层暴露出部分互连结构表面。
可选的,所述第二开口暴露出所述互连结构表面。
可选的,所述互连结构的材料包括金属,所述金属包括铜、钨、钴和钌其中一种或多种的组合。
可选的,所述介电层包括:位于停止层上的第一介电层和位于第一介电层上的第二介电层;所述第一开口位于所述第二介电层和第一介电层内。
可选的,所述第一介电层的材料包括氧化硅、氮化硅或硅;所述第二介电层的材料包括氧化硅、氮化硅或硅。
可选的,在所述第一介电层和第二介电层内形成第一开口的方法包括:在所述第二介电层表面形成图形化的掩膜层,所述图形化的掩膜层暴露出部分第二介电层表面;以所述图形化的掩膜层为掩膜刻蚀所述第二介电层和第一介电层,直至暴露出所述停止层表面,形成所述第一开口。
可选的,刻蚀所述第二介电层和第一介电层的工艺包括干法刻蚀工艺。
可选的,还包括:在所述第二开口内形成导电插塞。
可选的,所述停止层的形成工艺包括沉积工艺。
可选的,所述介电层的形成工艺包括沉积工艺。
相应的,本发明技术方案还提供一种采用上述任一方法所形成的半导体结构。
与现有技术相比,本发明的技术方案具有以下有益效果:
本发明技术方案的方法中,对所述第一开口底部的停止层进行改性处理形成改性层,所述改性层与所述停止层的材料具有较大的选择刻蚀比,从而在去除所述改性层形成第二开口的过程中,所述刻蚀工艺对所述第二开口侧壁的停止层损伤较小,从而避免了后续在所述第二开口内形成的导电插塞容易短路、漏电的情况,从而提升了半导体结构的性能。
进一步,所述改性层的材料包括铝或氧化硅,所述改性层与所述停止层的刻蚀选择比较大,故在去除改性层形成第二开口的过程中,所述去除工艺对所述第二开口侧壁的停止层损伤较小。
附图说明
图1至图3是一实施例中半导体结构形成过程的剖面结构示意图;
图4至图10是本发明实施例中半导体结构形成过程的剖面结构示意图。
具体实施方式
如背景技术所述,现有的集成电路制造工艺还有待改善。现结合具体的实施例进行分析说明。
图1至图3是一实施例中半导体结构形成过程的剖面结构示意图。
请参考图1,提供衬底,所述衬底包括基底100,位于基底100上的隔离层101,位于隔离层101内的互连结构102;在所述衬底上形成停止层103;在所述停止层103上形成介电层104。
请参考图2,在所述介电层104内形成第一开口105,所述第一开口105暴露出所述停止层103表面。
请参考图3,去除所述第一开口105底部的停止层103,形成第二开口106,所述第二开口106暴露出所述互连结构102的表面。
在所述半导体结构的形成过程中,在形成第一开口105之后,采用湿法刻蚀工艺去除所述第一开口105底部的停止层103,由于湿法刻蚀工艺各向同性的特性,在去除所述第一开口105底部的停止层103形成第二开口106时,不可避免会对所述第二开口106侧壁的停止层103侧向刻蚀,导致相邻互连结构102之间衬底表面的停止层103受到损伤甚至贯穿,则后续在所述第二开口106内形成导电插塞与所述互连结构102电连接后,相邻的导电插塞容易发生短路以及漏电的情况,从而影响所述半导体结构的性能。
为了解决上述问题,本发明技术方案提供一种半导体结构及其形成方法,通过对所述第一开口底部的停止层进行改性处理形成改性层,所述改性层与所述停止层的材料具有较大的选择刻蚀比,从而在去除所述改性层形成第二开口的过程中,所述刻蚀工艺对所述第二开口侧壁的停止层损伤较小,从而避免了后续在所述第二开口内形成的导电插塞容易短路、漏电的情况,从而提升了半导体结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图4至图10是本发明实施例中半导体结构形成过程的剖面结构示意图。
请参考图4,提供衬底。
在本实施例中,所述衬底包括基底200和位于基底200上的隔离层201。
在其它实施例中,所述衬底包括基底和位于基底上的隔离层,所述基底上具有器件结构、导电布线、多层金属层或者多层导电层,所述器件结构、导电布线、多层金属层或者多层导电层位于所述隔离层内。
所述隔离层201内具有互连结构202,所述隔离层201暴露出部分互连结构202表面。在本实施例中,所述互连结构202用于与其他互连结构电连接。所述互连结构包括导电插塞。
在其它实施例中,所述互连结构与所述器件结构、导电布线、多层金属层或者多层导电层电连接。所述器件结构包括晶体管、二极管或PN结。
在本实施例中,所述互连结构202的材料包括金属,所述金属包括铜、钨、钴和钌其中一种或多种的组合。
所述互连结构202的材料包括金属,后续在所述互连结构202表面形成导电插塞,所述互连结构202通过导电插塞与其他器件电连接。
在其它实施例中,所述互连结构的材料包括金属硅化物。所述金属硅化物包括硅化钛、硅化锆、硅化钽或硅化钨。
所述隔离层201的材料包括氧化硅或氮化硅。在本实施例中,所述隔离层201的材料包括氧化硅。
所述基底200的材料包括硅。在其他实施例中,所述基底的材料包括:锗、锗化硅、碳化硅、砷化镓或者镓化铟。
请参考图5,在所述衬底表面形成停止层203。
所述停止层203用于后续在衬底表面形成的介电层内形成开口时的刻蚀停止层,避免所述开口直接暴露出所述互连结构202表面,从而使得所述互连结构202受到损伤。
所述停止层203的形成工艺包括化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
在本实施例中,所述停止层203的形成工艺包括化学气相沉积工艺。采用化学气相沉积工艺可以高效形成结构致密的停止层203。
所述停止层203的材料包括氮化铝、氧化铝或氮化硅;在本实施例中,所述停止层203的材料包括氮化铝。
选用氮化铝作为后续刻蚀所述第一介电层和第二介电层形成第一开口的停止层,所述氮化铝与所述第一介电层具有不同的刻蚀选择比,故可以作为停止层控制所述第一介电层的刻蚀工艺;另一方面,所述氮化铝为不导电材料,从而对第一开口底部的互连结构202起到绝缘作用,避免互连结构202通过停止层203相互导通,影响半导体结构的性能。
在本实施例中,所述停止层203的厚度范围为1nm~5nm。
若所述停止层203的厚度小于1nm,则作为所述刻蚀停止层的停止效果不好;若所述停止层203的厚度大于5nm,则后续在对所述停止层进行改性处理时,所述改性气体的渗入深度有限,无法将所述停止层完全改性。
请参考图6,在所述停止层203表面形成介电层。
所述介电层用于后续在所述第二开口内形成导电插塞提供结构支持,同时也对后续形成的各导电插塞起到绝缘作用,避免各导电插塞之间发生短路,从而影响半导体结构的性能。
在本实施例中,所述介电层包括位于停止层203上的第一介电层204和位于第一介电层204上的第二介电层205。
在所述停止层203上形成第一介电层204和第二介电层205,所述第一介电层204和第二介电层205的材料不同,所述第一介电层204的材料结构较为致密,使得在所述第一介电层204内形成开口的过程中,所述开口的侧壁较为笔直,使得形成开口的图形精度更高,后续在开口内形成的导电插塞与所述互连结构202具有较大的接触面接,导电性更好。
所述第一介电层204的材料包括氧化硅、氮化硅或硅;所述第二介电层205的材料包括氧化硅、氮化硅或硅。
在本实施例中,所述第一介电层204的材料与所述第二介电层205的材料不同。
在本实施例中,所述第一介电层204的材料包括氮化硅;所述第二介电层205的材料包括氧化硅。
形成所述第一介电层204的工艺包括化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
在本实施例中,形成所述第一介电层204的工艺包括化学气相沉积工艺。
形成所述第二介电层205的工艺包括化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
在本实施例中,形成所述第二介电层205的工艺包括化学气相沉积工艺。
在其他实施例中,所述第一介电层的材料与所述第二介电层的材料相同。所述第一介电层的材料与所述第二介电层的形成工艺不同。
所述第一介电层204的材料与所述第二介电层205的材料包括氧化硅、氮化硅或硅。
形成所述第一介电层204的工艺包括原子层沉积工艺;形成所述第二介电层205的工艺包括化学气相沉积工艺或物理气相沉积工艺。
所述原子层沉积工艺相较于所述化学气相沉积工艺,能够形成结构更为致密的氧化硅或氮化硅。
在其他实施例中,当所述停止层的材料包括氮化硅时,所述第一介电层的材料与所述第二介电层的材料相同,所述第一介电层的材料与所述第二介电层的材料包括硅。
所述氮化硅材料的停止层被改性后形成氧化硅,所述氧化硅与氮化硅具有较大的选择刻蚀比,且所述氧化硅与硅具有较大的刻蚀选择比,故在去除所述改性层的过程中,能够对所述停止层和介电层的损伤较小。
请参考图7,在所述介电层内形成第一开口207,所述第一开口207暴露出所述停止层203表面。
在所述第一介电层204和第二介电层205内形成第一开口207的方法包括:在所述第二介电层205表面形成图形化的掩膜层206,所述图形化的掩膜层206暴露出部分第二介电层205表面;以所述图形化的掩膜层206为掩膜刻蚀所述第二介电层205和第一介电层204,直至暴露出所述停止层203表面,形成所述第一开口207。
在本实施例中,刻蚀所述第二介电层205和第一介电层204的工艺包括干法刻蚀工艺;在其他实施例中,刻蚀所述第二介电层205和第一介电层204的工艺包括湿法刻蚀工艺。
在本实施例中,所述图形化的掩膜层206的材料包括光刻胶;在其他实施例中,所述图形化的掩膜层206的材料包括硬掩膜层。
形成所述第一开口207之后,去除所述图形化的掩膜层206。
在本实施例中,去除所述图形化的掩膜层206的工艺包括灰化工艺。
请参考图8,对所述第一开口207底部的停止层203进行改性处理,形成改性层208。所述改性层208与所述停止层203具有较大的刻蚀选择比,后续在去除所述改性层208暴露出所述互连结构202表面时,能够对所述改性层208侧壁的停止层203的损伤较小,避免过刻蚀所述停止层203,使得后续形成的导电插塞短路。
在本实施例中,所述改性层208的材料包括铝;在其他实施例中,所述改性层208的材料包括氧化硅。
在本实施例中,对所述第一开口207暴露出的所述停止层203进行改性处理的工艺为等离子体处理工艺。
在本实施例中,所述停止层203的材料包括氮化铝,所述等离子体处理工艺的气体为氢气和惰性气体的混合气体,所述惰性气体包括氩气或氦气,所述氢气的体积比大于20%。
所述氢气为反应气体,所述氢气能够与所述氮化铝进行化学反应生成金属铝与氨气,所述氨气可随反应气体一起排出,从而使与等离子体接触的所述氮化铝改性成铝;所述铝与氮化铝具有较大的刻蚀选择比,故后续在去除铝形成第二开口时,所述去除铝的工艺对所述第二开口侧壁的停止层203的损伤较小,避免后续在第二开口内形成导电插塞后发生短路、漏电的情况,从而提升了半导体结构的性能。
所述惰性气体容易被电离出电子,从而为所述反应提供电子;同时所述惰性气体可以维持所述反应腔体的气压稳定且不发生化学反应。
在其他实施例中,所述停止层材料为氮化硅时,所述等离子处理的气体为氧气。所述氧气与氮化硅反应生产氧化硅改性层和二氧化氮气体,所述二氧化氮气体可随反应气体一起排出,所述氧化硅改性层与氮化硅停止层有较大的刻蚀选择比。
请参考图9,去除所述改性层208,形成第二开口209,所述第二开口209暴露出所述衬底表面。
在本实施例中,所述第二开口209暴露出所述互连结构202表面,所述第二开口209用于后续在第二开口209内形成导电插塞与所述互连结构202电连接。
在本实施例中,去除所述改性层208的工艺包括湿法刻蚀工艺。
所述湿法刻蚀工艺的参数包括:溶液为NH2OH溶液,溶液温度范围为0℃~40℃。
所述NH2OH溶液在0℃~40℃的温度范围内对所述铝和所述氮化铝的选择刻蚀比较大,能够在去除所述改性层208的过程中,对所述第二开口209侧壁的停止层203损伤较小;同时,所述NH2OH溶液对所述互连结构202具有较高的刻蚀选择比,故能够在去除干净所述改性层208的情况下,对所述互连结构202的损伤较小,从而提升了半导体结构的性能。
若所述NH2OH溶液的温度大于40℃,则所述反应温度较高,所述氮化铝在此温度条件下易发生水解生成氢氧化铝从而与所述NH2OH溶液发生反应,从而在去除所述改性层208的过程中,对所述第二开口209侧壁的停止层203造成损伤,不能达到本发明技术方案的目的。
在另一实施例中,所述停止层的材料包括氮化硅,所述改性层的材料包括氧化硅,所述第一介电层和所述第二介电层的材料包括硅,则所述湿法刻蚀工艺的溶液包括HF溶液。
所述HF溶液对所述氧化硅和氮化硅的选择刻蚀比较大,所述HF溶液对所述氧化硅和硅的刻蚀选择比较大,从而在去除所述改性层的过程中,对所述第二开口侧壁的停止层损伤较小,同时对所述介电层的损伤较小。
请参考图10,形成第二开口209之后,在所述第二开口209内形成导电插塞210。
所述导电插塞210的形成方法包括:在所述第二开口209内、所述第二介电层205表面形成导电插塞材料层(未图示);平坦化所述导电插塞材料层,直至暴露出所述第二介电层205表面,形成所述导电插塞210。
所述导电插塞210的材料包括金属;所述金属包括铜、钨、铝、钛、氮化钛和钽中的一种或多种组合。在本实施例中,所述导电插塞210的材料包括钛或氮化钛。
在本实施例中,形成所述导电插塞210材料层的工艺包括沉积工艺。在其他实施例中,形成所述导电插塞材料层的工艺包括电镀工艺。
在本实施例中,平坦化所述导电插塞210材料层的工艺包括化学机械抛光工艺。
在本实施例中,所述导电插塞210与所述互连结构202电连接。
至此,所形成的所述导电插塞210与所述互连结构202接触面积较大,导电效果较好,同时也减少了短路的情况,提升了半导体结构的性能。
相应的,本发明实施例还提供一种采用上述方法所形成的半导体结构。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (16)
1.一种半导体结构的形成方法,其特征在于,包括:
提供衬底;
在所述衬底表面形成停止层;
在所述停止层表面形成介电层;
在所述介电层内形成第一开口,所述第一开口暴露出所述停止层表面;
对所述第一开口底部的停止层进行改性处理,形成改性层;
去除所述改性层,形成第二开口,所述第二开口暴露出所述衬底表面。
2.如权利要求1所述的半导体结构形成方法,其特征在于,对所述第一开口暴露出的所述停止层进行改性处理的工艺为等离子体处理工艺。
3.如权利要求1所述的半导体结构形成方法,其特征在于,所述停止层的材料包括氮化铝、氧化铝或氮化硅;所述改性层的材料包括铝或氧化硅。
4.如权利要求3所述的半导体结构形成方法,其特征在于,所述等离子处理工艺的气体包括:氢气和氩气的混合气体,所述氢气的体积比大于20%;或者,所述等离子处理工艺的气体为氧气。
5.如权利要求3所述的半导体结构形成方法,其特征在于,去除所述改性层的工艺包括湿法刻蚀工艺;所述湿法刻蚀工艺采用的溶液包括:NH2OH溶液或者HF溶液。
6.如权利要求1所述的半导体结构形成方法,其特征在于,所述衬底包括基底和位于基底上的隔离层,所述隔离层内具有互连结构,所述隔离层暴露出部分互连结构表面。
7.如权利要求6所述的半导体结构形成方法,其特征在于,所述第二开口暴露出所述互连结构表面。
8.如权利要求6所述的半导体结构形成方法,其特征在于,所述互连结构的材料包括金属,所述金属包括铜、钨、钴和钌其中一种或多种的组合。
9.如权利要求1所述的半导体结构形成方法,其特征在于,所述介电层包括:位于停止层上的第一介电层和位于第一介电层上的第二介电层;所述第一开口位于所述第二介电层和第一介电层内。
10.如权利要求9所述的半导体结构形成方法,其特征在于,所述第一介电层的材料包括氧化硅、氮化硅或硅;所述第二介电层的材料包括氧化硅、氮化硅或硅。
11.如权利要求9所述的半导体结构形成方法,其特征在于,在所述第一介电层和第二介电层内形成第一开口的方法包括:在所述第二介电层表面形成图形化的掩膜层,所述图形化的掩膜层暴露出部分第二介电层表面;以所述图形化的掩膜层为掩膜刻蚀所述第二介电层和第一介电层,直至暴露出所述停止层表面,形成所述第一开口。
12.如权利要求11所述的半导体结构形成方法,其特征在于,刻蚀所述第二介电层和第一介电层的工艺包括干法刻蚀工艺。
13.如权利要求1所述的半导体结构形成方法,其特征在于,还包括:在所述第二开口内形成导电插塞。
14.如权利要求1所述的半导体结构形成方法,其特征在于,所述停止层的形成工艺包括沉积工艺。
15.如权利要求1所述的半导体结构形成方法,其特征在于,所述介电层的形成工艺包括沉积工艺。
16.一种如权利要求1至15任一项方法所形成的半导体结构。
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JP2007134567A (ja) * | 2005-11-11 | 2007-05-31 | Sharp Corp | 半導体装置及びその製造方法 |
US7977249B1 (en) * | 2007-03-07 | 2011-07-12 | Novellus Systems, Inc. | Methods for removing silicon nitride and other materials during fabrication of contacts |
US20150140827A1 (en) * | 2013-11-20 | 2015-05-21 | Applied Materials, Inc. | Methods for barrier layer removal |
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