CN112204732A - 一种电路板及移动终端 - Google Patents

一种电路板及移动终端 Download PDF

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Publication number
CN112204732A
CN112204732A CN201880094055.XA CN201880094055A CN112204732A CN 112204732 A CN112204732 A CN 112204732A CN 201880094055 A CN201880094055 A CN 201880094055A CN 112204732 A CN112204732 A CN 112204732A
Authority
CN
China
Prior art keywords
circuit board
component
frame plate
stepped
solder balls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880094055.XA
Other languages
English (en)
Inventor
史洪宾
龙浩晖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN112204732A publication Critical patent/CN112204732A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

一种电路板及移动终端，该电路板包括支撑部件，以及与支撑部件层叠的第一部件；其中，支撑部件具有朝向第一部件的第一台阶结构，第一台阶结构具有第一台阶面及第二台阶面，且第一台阶面通过第一焊球与第一部件连接，第二台阶面通过第二焊球与第一部件连接，第一焊球的高度大于第二焊球的高度。在本申请中，通过在支撑部件上设置台阶面，局部增大了与第一部件之间的间隙，并且在支撑部件与第一部件连接时，两个台阶面上分别设置焊球与第一部件连接，从而可以增大一部分焊球的高度，并通过增高的焊球来降低支撑部件与第一部件之间的焊点的跌落和温度循环应力，提高了整个电路板的机械和环境可靠性，同时也就提高了电路板在使用时的安全性。

Description

PCT国内申请，说明书已公开。

Claims (11)

  1. PCT国内申请，权利要求书已公开。
CN201880094055.XA 2018-05-31 2018-05-31 一种电路板及移动终端 Pending CN112204732A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/089368 WO2019227435A1 (zh) 2018-05-31 2018-05-31 一种电路板及移动终端

Publications (1)

Publication Number Publication Date
CN112204732A true CN112204732A (zh) 2021-01-08

Family

ID=68697749

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880094055.XA Pending CN112204732A (zh) 2018-05-31 2018-05-31 一种电路板及移动终端

Country Status (2)

Country Link
CN (1) CN112204732A (zh)
WO (1) WO2019227435A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023273676A1 (zh) * 2021-06-30 2023-01-05 华为技术有限公司 电路板组件及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214308A (en) * 1990-01-23 1993-05-25 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US20040245624A1 (en) * 2003-06-03 2004-12-09 Swanson Leland S. Using solder balls of multiple sizes to couple one or more semiconductor structures to an electrical device
CN101035415A (zh) * 2006-03-10 2007-09-12 环隆电气股份有限公司 无线通讯用的双基板电子模块的封装方法
US20080224283A1 (en) * 2005-09-20 2008-09-18 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package and fabrication method thereof
US20110140283A1 (en) * 2009-12-16 2011-06-16 Harry Chandra Integrated circuit packaging system with a stackable package and method of manufacture thereof
US20140092572A1 (en) * 2012-09-28 2014-04-03 Md Altaf HOSSAIN Bga structure using ctf balls in high stress regions

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW586199B (en) * 2002-12-30 2004-05-01 Advanced Semiconductor Eng Flip-chip package
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214308A (en) * 1990-01-23 1993-05-25 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US20040245624A1 (en) * 2003-06-03 2004-12-09 Swanson Leland S. Using solder balls of multiple sizes to couple one or more semiconductor structures to an electrical device
US20080224283A1 (en) * 2005-09-20 2008-09-18 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package and fabrication method thereof
CN101035415A (zh) * 2006-03-10 2007-09-12 环隆电气股份有限公司 无线通讯用的双基板电子模块的封装方法
US20110140283A1 (en) * 2009-12-16 2011-06-16 Harry Chandra Integrated circuit packaging system with a stackable package and method of manufacture thereof
US20140092572A1 (en) * 2012-09-28 2014-04-03 Md Altaf HOSSAIN Bga structure using ctf balls in high stress regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023273676A1 (zh) * 2021-06-30 2023-01-05 华为技术有限公司 电路板组件及电子设备

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WO2019227435A1 (zh) 2019-12-05

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Application publication date: 20210108