CN112152486B - 应用于高功率密度充电的超快速瞬态响应交直流转换器 - Google Patents

应用于高功率密度充电的超快速瞬态响应交直流转换器 Download PDF

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CN112152486B
CN112152486B CN202010576902.5A CN202010576902A CN112152486B CN 112152486 B CN112152486 B CN 112152486B CN 202010576902 A CN202010576902 A CN 202010576902A CN 112152486 B CN112152486 B CN 112152486B
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pcb
charger
printed circuit
layer
circuit board
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CN112152486A (zh
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黄培伦
陈佑民
林天麒
郑荣霈
于岳平
牛志强
张晓天
王隆庆
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Cayman Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
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    • H—ELECTRICITY
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    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/02—Details
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Abstract

本发明公开了一种应用于高功率密度充电的超快速瞬态响应交直流转换器，其中，充电器，包括外壳、第一多层印刷电路板(PCB)、第二多层印刷电路板和第三多层印刷电路板。所述的第一印刷电路板包括初级侧电路的至少一部分；所述的第二印刷电路板包括次级侧电路的至少一部分；所述的第三印刷电路板垂直于所述的第一印刷电路板和所述的第二印刷电路板，隔离耦合元件设置在第三印刷电路板上，所述的隔离耦合元件包括多层印刷电路板；所述的第一印刷电路板包括高压(HV)半导体封装，所述的高压(HV)半导体封装包括一个高压金属氧化物半导体场效应晶体管(MOSFET)芯片倒装在芯片基座上，所述的芯片基座的底面从成型封装的底面露出。

Description

应用于高功率密度充电的超快速瞬态响应交直流转换器
技术领域
本发明涉及一种超快速瞬态响应(STR)交流/直流(AC/DC)转换器及其在高功率密度充电中的应用。STR AC/DC转换器具有使用更小的变压器和电容器并提高性能的优点。结合独特的印刷电路板(PCB)设计和部件集成，组装成一个紧凑型功率传递(PD)充电器，为快速充电应用提供超过0.6W/CC的功率密度。
背景技术
图1A是基于脉宽调制(PWM)控制反激AC/DC转换器的传统充电器的简化电路图。变压器TX1将从一次侧电源接收到的能量传输到二次侧，为负载供电。变压器TX1的初级线圈的第一端连接到变压器输入电压VBulk，一般是来自交流壁装电源插座的整流输出电压(整流电压)。变压器初级线圈的第二端连接到主开关Q1，以调节通过变压器初级线圈的电流，以便将能量传输到变压器的次级侧。主控制器位于变压器的一次侧，用于控制主开关的接通和断开。一个反馈回路，其误差放大器位于变压器的次级侧，通过光耦将输出信息反馈给第一侧的控制器。如图1B所示，图1A中电路的工作频率在峰值负载时限制在65kHz至85kHz。脉宽调制控制器的控制带宽(BW)受电流模式控制环路带宽(BW～0.1×fs)约为开关频率的十分之一的限制。由于工作频率低，控制带宽窄，输出电压瞬态响应慢。图1C显示了负载在空载和100％负载之间过渡时，由于工作频率fs的缓慢过渡，输出电压、Vout和瞬态响应的大波动。此外，对于传统的脉宽调制控制器，为了保持与负载状态变化对应的高转换效率，需要在连续导通模式(CCM)和中断导通模式(DCM)的不同操作模式之间切换脉宽调制控制器的操作。为了保持控制器的稳定运行，通常需要恒流补偿回路和恒压补偿回路。因此，传统的基于脉宽调制控制的反激式交直流转换器的充电器不可避免地需要额外的元件。
图1D和图1E分别显示了图1A传统充电器中常用的传统垂直MOSFET晶体管的横截面图和俯视图。该晶体管的漏极D位于晶体管芯片的底面上，连接到引线框架芯片基座上，引线框架芯片基座底部表面暴露于封装中。源极和栅极位于晶体管芯片的顶面上。源极和栅极连接到源极引脚S和栅极引脚G。图1F显示了图1A的传统充电器的PCB布局10。PCB布局10配置为接收图1D和图1E的传统MOSFET器件。传统MOSFET器件具有小面积源极引脚连接到PCB上的小铜垫11，大面积漏极引脚14连接到PCB上的大铜垫12。MOSFET芯片的漏极通过漏极引脚14和铜垫区12之间的大接触区与变压器TX1连接。MOSFET芯片的源极通过电阻R2接地。由于热耗散和电磁干扰(EMI)降噪之间不可避免的折衷，PCB布局10的性能没有得到优化。MOSFET器件Q1会发热，需要一个大的铜垫区域12(例如，长度大于10mm，宽度大于5mm)进行冷却。然而，大面积漏极引脚14具有高电压和高dv/dt值。它将EMI噪声与系统耦合。这对于低压应用来说可能不是问题。然而，对于500V或更高电压应用，由于快速变化和高漏极电压，EMI噪声很高。它需要一个小的铜垫区域12来降低电磁干扰噪声。这与需要使用更大的铜垫区域12进行冷却的要求相反。一个大的铜垫区域12的结果是产生大的电磁干扰噪声。为了满足规范要求，经常需要采用附加的大体积散热器和金属屏蔽来提高散热性能和射频干扰屏蔽。此外，对于高压应用，大面积的高压漏极引脚需要较大的安全空间，因此增加了器件面积，使得在保持高电压安全空间的同时，最大限度地减小器件尺寸成为一项挑战。
便携式设备充电器的理想功能包括：提供安全充电而不损坏待充电设备的高性能、快速充电以节省时间和紧凑尺寸以节省空间以方便移动。这种理想的特性将迫使充电器使用较少的元件数量和较小尺寸的元件，如较小的变压器和较小的电容器，以处理更高的功率密度而不增加太多的成本。功率密度的增加会引起散热和电磁干扰问题。使用较小的部件或较少的部件数可能会影响充电器的性能。因此，目前市场上最好的充电器功率密度小于0.5W/CC。
发明内容
本发明提供了一种超过0.5W/CC的解决方案，其方法是：采用新颖的系统电路控制，将主开关和控制集成电路(IC)共同封装在单一芯片基座上，并使用四层印刷电路板(PCB)。因此，减少了电磁干扰，提高了热性能，实现了快速开启。
为了达到上述目的，本发明通过以下技术方案实现：
一个设置在多层印刷电路板上的交流/直流转换器，所述交流/直流转换器包括：
一个变压器，包括初级线圈和次级线圈，初级线圈的第一端子接收整流电压；
一个功率半导体封装，包括主开关，该主开关具有连接到源极引线的源极电极和连接到漏极引线的漏极电极；
其中，漏极引线连接到印刷电路板上的漏极接触焊盘上；
其中，所述漏极接触焊盘与所述变压器初级线圈的第二端子电连接；
其中，所述源极引线连接到所述印刷电路板上的源接触焊盘；并且
其中，连接多层印刷电路板上的源接触焊盘的源引线面积大于连接多层印刷电路板上的漏极接触焊盘的漏极引线面积。
可选的，所述多层印刷电路板包括顶层和底层之间的一个或多个中间层。
可选的，所述多层印刷电路板的中间层包括连接到源极接触焊盘的导电区域。
可选的，所述功率半导体封装设置在顶层，所述变压器设置在底层。
可选的，所述功率半导体封装还包括驱动IC，用于提供控制主开关的驱动信号。
可选的，所述功率半导体封装还包括用于接收整流电压以产生控制主开关的启动信号的耗尽型场效应晶体管。
可选的，还包括驱动器IC，以提供控制主开关的驱动信号。
可选的，还包括：
二次侧控制器，其中二次侧控制器包括：
一个反馈回路，其包括一个比较器,比较器的反向端子接收与输出电压成比例的反馈电压，并与非反向端子上的参考电压相比较。
可选的，所述二次侧控制器还包括一个导通时间发生器，其接收来自所述比较器的比较结果以生成一个导通时间控制信号。
可选的，还包括同步MOSFET晶体管，所述同步MOSFET晶体管具有连接到所述次级线圈的第二端子的漏极和连接到地的源极。
可选的，还包括连接在二次侧控制器和驱动器之间的隔离耦合元件。
可选的，所述驱动器产生驱动信号以打开和关闭主开关晶体管，以在满负荷时以高于最大85kHz的开关频率调节通过变压器初级线圈的电流。
可选的，自然峰值负载工作频率被限制在最大150kHz。
可选的，输出电压包括纹波噪声，所述纹波噪声包括低频交流纹波和开关频率的高频开关纹波；并且，在所述整流电压的波峰附近的开关纹波频率低于整流电压的波谷附近的开关纹波频率。
可选的，输出电压不包含次谐波频率纹波噪声。
可选的，所述二次侧控制器是一个固定导通时间控制器；其中，在满负荷条件下，当整流电压降低时，所述二次侧控制器增加导通时间以保持负载输出直到达到最大的导通时间。
可选的，最大导通时间为占空比的80％。
可选的，当达到最大导通时间时，当整流电压持续降低时，控制器增加开关频率。
可选的，还包括带内置微控制器单元的功率传递控制器，以与负载通信。
可选的，所述功率传递控制器为USB C型控制器。
本发明与现有技术相比具有以下优点：
本发明的系统电路控制采用二次侧固定导通时间(COT)控制，使得主控制器中带有比较器的反馈回路位于二次侧(而不是在现有技术中的一次侧使用误差放大器)。与传统控制方案相比，本发明的控制响应更快。自然峰值负荷运行频率最大为150kHz(与传统最大值的65k-85k Hz相比)。更高的开关频率150kHz，不仅提供了快速响应瞬态调节的好处，还可以在保持相同的输出功率条件下，使用更小的电容器和更小的变压器。此外，本发明的控制方案不需要任何额外的补偿回路部件。因此，本发明能够将系统封装到较小的空间中，而不会降低热性能和电性能。
本发明的变压器尺寸减小，因为线圈匝数从85kHz最大频率的58匝减少到150kHz最大频率的45匝。13圈的线圈匝数裕度可用于选择较小尺寸的磁芯体，或用于选择较大直径的导线以减小尺寸或铜损耗。
由于COT全范围开关频率反馈控制方案、最大占空比高达80％、负载条件高达150kHz的自动频率扫描以及不使用电流模式控制因而没有子谐波的问题，本发明的电容器尺寸减小。
本发明公开了一种交流/直流充电器，包括外壳、第一印刷电路板、第二印刷电路板、第三印刷电路板、第一插脚和第二插脚。第一印刷电路板包括初级侧电路。第二印刷电路板包括次级侧电路。第三印刷电路板垂直于第一印刷电路板和第二印刷电路板。本发明的第一印刷电路板、第二印刷电路板和第三印刷电路板是多层印刷电路板，优选四层印刷电路板。除接触区域外，它们还提供额外的散热区域。
分离的初级侧印刷电路板(带有一个主控制器)和次级侧印刷电路板(带有一个次级控制器)提供了在三维支撑夹具的协助下优化元件布置的优势，以将系统包装在最小空间内。在一个例子中，隔离耦合元件被布置在第三个印刷电路板上。隔离耦合元件包括多层PCB无芯变压器，优选四层PCB无芯变压器。PCB无芯变压器作为一个独立的表面安装部件或嵌入母板内提供了灵活性。
第一印刷电路板和第二印刷电路板各包括半导体封装。半导体封装的芯片基座的底面暴露于成型封装中。芯片基座的外露表面直接连接到印刷电路板的导电区域。本发明的半导体封装利用MOSFET倒装芯片封装技术，将MOSFET晶体管和控制IC共同封装在单个芯片基座上。它提供了一个大面积的源电极，从封装的底面暴露出来，以提高热耗散，降低变压器一次侧和二次侧的电磁干扰。
附图说明
图1A是现有技术充电器的简化电路图；
图1B显示现有技术充电器的开关频率负载依赖性；
图1C是现有技术充电器的输出瞬态响应图；
图1D和图1E分别显示了现有技术充电器中使用的传统垂直MOSFET晶体管的横截面图和俯视图；
图1F显示了现有技术充电器的印刷电路板布局；
图2A是本发明示例中充电器的简化电路图；
图2B显示本发明的示例中充电器的开关频率负载依赖性；
图2C是本发明示例中充电器的输出瞬态响应图；
图2D显示了降低充电器整流电压的控制响应；
图2E显示了本发明示例中充电器的输出纹波；
图3A是本发明示例中充电器的透视图；
图3B是本发明示例中充电器的电路；
图4A、图4B和图4C分别是本发明示例中充电器第一印刷电路板的内层、外层和中间层的布局；
图5A、图5B和图5C分别是本发明示例中充电器第二印刷电路板的内层、外层和中间层的布局；
图6A、图6B和图6C分别为本发明示例中高压(HV)半导体封装的俯视图，横截面图和底面视图；
图7A和图7B分别是本发明示例中半导体封装的是俯视图和横截面图；
图8是本发明示例中另一半导体封装的俯视图；
图9A、9B和9C分别是本发明的示例中PCB无芯变压器的上层、下层和底层的俯视图。
具体实施方式
以下结合附图，通过详细说明一个较佳的具体实施例，对本发明做进一步阐述。
图2A是本发明示例中基于反激AC/DC转换器的二次侧固定导通时间控制(COT)的充电器的简化电路图。控制器102位于变压器101的二次侧(次级侧)。控制器102在次级侧包括反馈回路，比较器191的反向端接收反馈电压，该反馈电压与输出电压成比例，并与比较器191的非反向端上的参考电压相比较。比较结果由导通时间发生器192接收，该发生器处理其接收的信息，以生成通过隔离耦合元件103传输到变压器101初级侧驱动器104的导通时间控制信号。驱动器根据接收到的开启和关闭主开关105的导通时间控制信号生成驱动信号，以调节通过变压器101的初级线圈的电流。主开关105(MOSFET或其它绝缘栅极晶体管)可在远高于传统脉宽调制控制方案最大85kHz的工作频率下驱动。如图2B所示，图2A中电路的自然峰值负载工作频率被限制在最大150kHz。通过使用COT全范围开关频率反馈控制方案实现超快速瞬态响应(STR)，结果如图2C所示，输出电压(图2A的Vout和图2C中的Vo)非常稳定，在负载转换过程中波动很小。
在本发明的示例中，次级侧COT控制方案提供的更高操作频率提供了在基于该控制方案制造充电器时减小变压器尺寸的优势。例如，假设图2A中的电路在100％负载下以150kHz的开关频率运行，峰值电流ipk为1.0安培，相比之下，图1A中的电路在85kHz的开关频率运行，100％负载将不得不将其峰值电流ipk增加到1.3安培，以便根据公式(1)提供相同的输出功率：
其中Po为输出功率，Lm为变压器电感，fs为工作频率。如果最大频率85kHz下的满载转比设计为58圈，则根据公式(2)中的关系，150kHz下的满载转比设计可减少为45圈。
L×ipk＝Np×Bsat×Ae (2)
其中Np是初级线圈匝数，Bsat是磁芯饱和磁通密度，Ae是磁芯横截面积。因此，有13圈的线圈匝数裕度可以选择较小尺寸的磁芯或使用较大直径的导线以减小尺寸或铜损耗时。
在本发明的示例中，控制方案的超快速瞬态响应(STR)特性使负载条件高达150kHz的自动频率扫描成为可能。这为基于该控制方案的充电器的制造提供了减小储能电容器(输入电容器)尺寸的优势。在本发明的示例中，如图2D所示，在满负荷条件下，当整流电压VBulk降低时，控制方案将增加固定导通时间Ton，以保持负载直到达到最大的固定导通时间Ton。在本发明的示例中，如果整流电压VBulk继续降低，控制方案将增加开关频率fs，以保持负载。与传统PMW控制方案能提供60％最大占空比相比，次级侧COT控制方案将最大占空比提高到80％。增大的最大占空比可以在低电压下提供更大的功率，或者可以在不影响控制性能的情况下使用较小的电容器。在本发明的示例中，由于控制方案不基于电流模式控制，因此它没有次谐波问题。低频元件需要一个较大的电容器来过滤掉。
输出电压VOUT具有一个纹波噪声，该纹波噪声包括一个低频交流纹波，该低频交流纹波源自两倍输入交流源频率的整流电压，加上由于主开关的开关操作而在开关频率fs处产生的高频开关纹波。在本发明的示例中，如图2E所示，整流电压VBulk波峰周围的开关纹波频率低于整流电压VBulk波谷周围的开关纹波频率。在一个例子中，“峰周围”和“谷周围”分别指来自波峰或波谷的小于10％的占空比。在另一个例子中，“波峰周围”和“波谷周围”分别指来自波峰或波谷的小于20％的占空比。这是因为控制方案在交流纹波谷提供更高的开关频率，在交流纹波波峰提供更低的开关频率。这与传统的控制方案相反，后者的开关频率固定，不管在整流电压峰值和谷值。本发明中，由低频交流纹波的波峰到波谷，开关频率升高。由低频交流纹波的波谷到波峰，开关频率降低。这有助于避免电压摆动，降低交流纹波和开关纹波噪声。根据本发明的这一特点，输出电容器的尺寸可以更小。
在本发明的示例中，控制方案允许使用较小的储能电容器和输出电容器。在输出功率为10W的示例中，系统使用16.8μF的储能电容器和720μF的输出电容器。与基于传统控制方案的10W iPAD充电器(使用24μF的储能电容器和1200μF的输出电容器)相比，本发明的控制方案使用更小的储能电容器仅为现有技术的70％，较小的输出电容器仅为现有技术的60％。此外，本发明的控制方案不需要补偿回路的任何元件。本发明的所有这些特征有助于根据新的控制方案减小充电器的尺寸。
图3A是本发明示例中充电器100的透视图。图3B是本发明示例中充电器100的AC/DC反激转换器电路200。充电器100包括外壳110、第一印刷电路板(PCB)120、第二印刷电路板140、第一插脚152和第二插脚154。外壳110为立方体形状或矩形棱柱形状。可选圆角适用于外壳110。第一印刷电路板临近外壳110的第一侧面111。第二印刷电路板140临近外壳110的第二侧面112。第二侧面112与第一侧面111相对。第一插脚152和第二插脚154穿过外壳110的底面。外壳110的底面垂直于第一和第二侧面111和112。在一个示例中，第一插塞脚152和第二插塞脚154彼此沿平行于第一和第二侧面111和112的方向布置。在另一个示例中，第一插脚152和第二插脚154彼此沿垂直于第一和第二侧面111和112的方向布置。插座连接器，例如USB C型连接器或最小化型标准化连接器，通过外壳110顶面上与底面相对的开口180暴露。在图3A中，外壳110和第一,第二印刷电路板画成透明的。
图3B是一个更详细的电路图，其采用与图2A相同的控制方案。如图3B所示，AC/DC反激转换器电路200包括变压器201，其具有连接到接收从AC输入整流的整流电压VBulk的一次线圈的第一端子。由带滤波电路的桥式整流器202(包括储能电容器203)进行滤波。初级线圈的第二端子连接到初级侧接收器221的漏极端子。一次侧接收器221还包括接收在二次侧产生的控制信号的Rx终端，该控制信号作为栅极控制信号来调节通过一次线圈的一次电流。一次侧接收器221还可以包括一个高压终端HV，以在接收到二次侧产生的控制信号之前，在提供交流输入的开始时接收到整流电压以产生启动信号以控制一次线圈的一次电流。在变压器201的二次侧，提供与图2A中的控制器102以相同控制方案操作的超快速瞬态响应(STR)控制器241，以在反馈终端FB处接收输出反馈信号。在处理反馈信号后，次级侧STR控制器241产生恒定的导通时间控制信号。隔离耦合元件250连接在二次侧STR控制器241的传输终端Tx和一次侧接收器221的Rx终端之间，将固定导通时间控制信号从二次侧传输到反激转换器的一次侧。
交直流反激转换器电路200的二次侧还包括一个标准的高度集成的功率传递(PD)控制器271，通过多针输出互连插座281与负载通信。高度集成的PD控制器271可配备内置微控制器单元(MCU)和内置多次编程(MPT)功能。在一个例子中，高度集成的PD控制器271是一个通用系列总线(USB)C型控制器，支持2.0/3.0标准的供电。
在图3A中，第一印刷电路板120包括内层121、外层122和可选的一个或多个中间层123。在本发明的示例中，第一印刷电路板120包括图3B的一次侧电路220的至少一部分。在一个示例中，安装在第一印刷电路板120上的初级侧电路220的部件包括变压器201和储能电容器203布置在图4A所示的内层121上，以及布置在图4B所示外层122上的初级侧接收器221。在另一个示例中，安装在第一印刷电路板120上的初级侧电路220的部件还包括设置在外层122上的桥式整流器202。
如图3A所示，第二PCB 140包括内层141，外层142，以及其间可选的一个或多个中间层143。第二PCB 140包括图3B的次级侧电路240的至少一部分。在一个示例中，安装在第二PCB 140上的次级侧电路240的部件包括设置在如图5A所示的内层141上的输出电容器213，以及设置在如图5B所示的外层142上的次级侧STR控制器241和高度集成的PD控制器271。在另一示例中，安装在第二PCB 140上的次级侧电路240的部件还包括设置在内层141上的多针输出互连插座281。如图3A所示，第一PCB 120的内层121面向第二PCB 140的内层141，使得变压器201，储能电容器203，输出电容器213和其他大体积元件被限制在第一PCB120和第二PCB 140之间的空间中。低轮廓表面安装部件，包括初级侧接收器221，次级侧STR控制器241和高度集成的PD控制器271，位于分别面向外壳110第一和第二侧表面111和112的外层122和142上。多针输出互连插座281优选地安装在第二PCB 140的面向外壳110的顶表面上的开口180的边缘上。
为了避免现有技术装置中出现的散热问题和EMI问题，本发明第一PCB120的外层122设置有大面积源极接触焊盘223C和小面积漏极接触焊盘225C，如图4B所示。在一个示例中，大面积源极接触焊盘223C的面积是小面积漏极接触焊盘225C的面积的十倍或更多。在另一示例中，大面积源极接触焊盘223C的面积是小面积漏极接触焊盘225C的面积的二十倍或更多。大面积源极接触焊盘223C具有基本上与图6C所示的初级侧接收器221从半导体封装底面露出的芯片基座的底表面319一致的形状。如图4B和6C所示，在源极接触焊盘223C和用作半导体封装的源极引脚的暴露的芯片基座之间提供大的源极连接区域。小面积漏极接触焊盘225C具有基本上与从图6C所示的初级侧接收器221的半导体封装的底面露出的漏极引脚的底表面一致的形状。如图4B和6C所示，在漏极接触焊盘225C和半导体封装的暴露的漏极引脚之间提供小的漏极连接区域。在一个示例中，源连接区域是漏极连接区域的10倍以上。大面积源极接触焊盘提供主开关快速散热的优点，小面积漏极接触焊盘提供降低射频辐射EMI的好处。如图4B所示，大面积源极接触焊盘223C扩展到第一PCB 120的外层122上的大导电区域223，以用作散热器。为了进一步改善系统的热性能，在图4A中内层121以及图4C中的一个或多个可选的中间层123上设置较大的导电区域223'，通过导电通孔227连接到第一PCB 120的外层122上的大面积源极接触焊盘223C和扩展导电区域223。如图4C所示，一个或多个可选中间层123上的导电区域223'可以基本上扩张到整个中间层的PCB区域，除了导电孔的位置和它们的互连之外。这有助于通过整个PCB扩散和平均电流开关元件产生的热量，从而大大提高了热性能。在一个示例中，通过导电通孔227连接到源极接触焊盘223C的第一PCB 120的所有层中的组合导电区域223'是源极接触焊盘223C的面积的五倍以上。在又一示例中，通过导电通孔227连接到源极接触焊盘223C的第一PCB 120的所有层中的组合导电区域223'是源极接触焊盘223C的面积的十倍以上。出于同样的原因，如图5B所示，第二PCB 140的外层142设置有大面积源极接触焊盘243C和小面积漏极接触焊盘245C。如图7A和7B所示，二次侧半导体封装的暴露的芯片基座用作次级侧半导体封装的源极引脚，提供了与图5B源极接触焊盘243C之间大的源极连接区域。如图7A和7B所示，次级侧半导体封装的暴露的漏极引脚提供了与图5B漏极接触焊盘245C之间的小漏极连接区域。在一个示例中，源连接区域是漏极连接区域的10倍以上。大面积源极接触焊盘243C扩展到第二PCB 140的外层142上的大导电区域243，以用作散热器。较大的导电区域243'设置在内层141上以及图5C中的一个或多个可选的中间层143上。通过导电通孔247连接到第二PCB 140的外层142上的大面积源极接触焊盘243C和扩展导电区域243。如图5C所示，一个或多个可选中间层143上的导电区域243'可以基本上扩张到整个中间层的PCB区域，除了导电孔的位置和它们的互连之外。这有助于通过整个PCB扩散和平均电流开关元件产生的热量，从而大大提高了热性能。在一个示例中，通过导电通孔247连接到源极接触焊盘243C的第二PCB 140的所有层中的组合导电区域243'是源极接触焊盘243C的面积的五倍以上。在又一示例中，通过导电通孔247连接到源极接触焊盘243C的第二PCB 140的所有层中的组合导电区域243'是源极接触焊盘243C的面积的十倍以上。
图6A是本发明的示例中的HV半导体封装300的俯视图，图6B是沿AA'的横截面图，图6C是底部视图。在一个示例中，HV指的是500伏或更高的电压。HV半导体封装300包括引线框架320，集成电路(IC)340(可以是接收器IC或驱动器IC，或通常统称控制器IC)，耗尽型场效应晶体管(DFET)350[比如耗尽型MOSFET或耗尽型结型场效应晶体管(JFET))，HV金属-绝缘体-半导体场效应晶体管(MOSFET)360和模塑封装390。HV MOSFET 360具有源电极和栅电极设置在顶表面上，漏电极设置在底表面上。在一个示例中，HV半导体封装300是图3A示出的充电器100的电路图3B中的初级侧接收器221。在本发明的示例中，HV半导体封装300在封装本身，或安装在电路板上无需使用铜屏蔽和隔离聚酯薄膜。
引线框架320包括芯片基座322和与芯片基座分离的栅级接触岛。在一个例子中，引线框架320仅包含一个芯片基座322。引线框架320不包括另一个芯片基座。芯片基座322包括非蚀刻上表面部分326和蚀刻上表面部分328。IC 340通过第一非导电材料336连接到芯片基座322的非蚀刻上表面部分326。DFET 350通过第二非导电材料356连接到芯片基座322的非蚀刻上表面部分326。高压MOSFET 360通过导电材料(例如，多个焊球362)连接到芯片基座322的蚀刻上表面部分328。HV MOSFET 360前表面的大部分由预成型封装372包围。
成型封装390包围IC 340、DFET 350、HV MOSFET 360和引线框架320的大部分。IC340和DFET 350在正面放置。高压场效应晶体管360是在翻转芯片放置。高压MOSFET 360的源电极361直接连接到多个焊球362。多个焊球362直接连接到芯片基座322的蚀刻上表面部分328。
芯片基座322的蚀刻上表面部分328包括凹槽阵列329。凹槽阵列329中每个凹槽的深度为芯片基座322厚度的45％到55％。
在本发明的示例中，高压引脚386和连接到芯片基座322的相邻低压引脚388之间的水平距离389不得小于与高压半导体封装300的额定电压相对应的水平爬电距离。如图6A所示，高压引脚386和漏极引脚335布置在靠近一个拐角的两侧，在该拐角处芯片基座322被切除以保持水平爬电距离。为了保持可用的最大芯片基座底面面积，最好将切除面积减到最小。在本发明的示例中，芯片基座具有倒L形切除区399，以保持与高压导线386和漏极导线335至少1.1mm的水平爬电距离。高压MOSFET 360包括多个焊球362。多个焊球362的大部分被预成型封装372包围。垂直爬电距离由多个焊球362的高度保持，该高度将高压MOSFET360与芯片基座322的蚀刻上表面部分328分开。
在另一个示例中，图6C中底部暴露源极面积是漏极335的底部暴露面积的10倍以上。在另一个示例中，图6C中底部暴露源极面积是漏极335的底部暴露面积的20倍以上。在本发明的的示例中，图6C芯片基座322的底面319暴露于成型封装390中。在一个示例中，芯片基座322的外露底面319的表面积至少为高压半导体封装300底面的60％。在又一个例子中，芯片基座322的暴露底面319的表面积至少为高压半导体封装300底面的80％。因为IC340、DFET 350和HV MOSFET 360安装在同一个芯片基座322上，目的是减少部件计数，并且由于HV MOSFET 360处于翻转的芯片位置，所以HV半导体封装300可以具有大功率接地(电连接到酸性高压MOSFET 360的CE电极361、芯片基座322的外露底面319和低压引脚388)。芯片基座322的外露底面319连接到第一个PCB 120的大源接触焊盘223C，以便于散热，以满足77℃的最大皮肤接触温度要求(用户的手接触充电器100的外壳110)。实际上，高压半导体封装300可仅包括安装在芯片基座322上的高压MOSFET 360翻转芯片，并且IC 340、DFET350提供在一个或多个单独的半导体封装中。或者高压半导体封装300可包括安装在芯片基座322上的高压MOSFET 360翻转芯片，与IC340和DFET 350中的一个共同包装。
在本发明的示例中，HV MOSFET 360与IC 340隔离并且与HV半导体封装300内的DFET 350隔离。引脚347(控制器栅极驱动输出)和引脚367(MOSFET栅极)在HV半导体封装300内电隔离。HV MOSFET 360可以通过HV半导体封装300外部的电路电连接到IC 340。因此，本发明提供了来自外部的其他附加控制的灵活性。或者，控制器栅极驱动输出可以在内部连接到MOSFET栅极，使得在HV半导体封装300上无需设置栅极端子。
图7A是本发明的示例中的俯视图。图7B是在沿着半导体封装400的CC'的横截面图。半导体封装400包括引线框架420，控制器440，MOSFET460和模制封装490。在一个示例中，半导体封装400是图3A中的充电器100中如图3B所示出的的次级侧STR控制器241。
引线框架420包括芯片基座422。在一个示例中，引线框架420仅包括单个芯片基座422.引线框架420不包括另一个芯片基座。芯片基座422包括未蚀刻的顶表面部分426和蚀刻的顶表面部分428。控制器440通过非导电材料436附接到芯片基座422的未蚀刻的顶表面部分426。MOSFET 460通过导电材料462附接到芯片基座422的蚀刻的顶表面部分428。
模制封装490包围控制器440，MOSFET 460和引线框架420的大部分。控制器440朝上放置。MOSFET 460设置于翻转芯片中。MOSFET 460的源电极461直接连接到导电材料462。导电材料462直接连接到芯片基座422的蚀刻的顶表面部分428。
芯片基座422的蚀刻顶表面部分428包括凹槽阵列429。凹槽阵列429中的每一个的凹槽深度是芯片基座422的厚度的45％至55％。
图8是本发明的示例中的半导体封装500的俯视图。半导体封装500包括引线框架520，PD控制器540，第一MOSFET 550，第二MOSFET 560和模制封装590(以透明示出)。在一个示例中，半导体封装500是图3A中的充电器100中如图3B所示出的次级侧中高度集成的PD控制器271。
引线框架520包括第一芯片基座522，第二芯片基座524和第三芯片基座526。PD控制器540附接到第一芯片基座522。第一MOSFET 550附接到第二芯片基座524。第二MOSFET560连接到第三芯片基座526。第一芯片基座522，第二芯片基座524和第三芯片基座526彼此分开。
在一个示例中，在图3A的充电器100中使用的隔离耦合元件250是无芯脉冲变压器。如图9A和9B所示，隔离耦合元件250由多层PCB上的导电迹线形成。在本发明的示例中，上层1300包括多个匝的初级线圈1360和次级线圈1370的第一部分1380。初级线圈1360设置在上层1300的外部，包围次级线圈1370的第一部分1380。次级线圈1370的第一部分1380设置在上层1300的内部。下层1400包括次级线圈1370的第二部分1480。上层1300上的次级线圈1370的第一部分1380具有中间接点1382位于上层1300的中央部分，连接到位于下层1400的中心部分的第二部分1480的中间接点1481。次级线圈1370的第一部分1380的第二端1384位于上层1300连接到下层1400上的次级线圈1370的第二端1484。在本发明的示例中，可以提供覆盖上层1300的可选顶层(未示出)，也可以提供可选的底层1200以覆盖下层1400以保护隔离耦合元件250的线圈导电迹线。底层1200上的第一焊盘1232可以通过第一组一个或多个过孔连接到初级线圈1360的第一端1362。底层1200上的第二焊盘1234可以通过第二组一个或多个通孔和下层1400上的导电迹线1494连接到初级线圈1360的第二端1364。底层1200上的第三焊盘1236可以通过第三组一个或多个通孔连接到下层1400上的次级线圈1370的第一端1482。底层1200上的第四焊盘1238可以通过下层1400上的第四组一个或多个通孔和导电迹线1498连接到次级线圈1370的第二端1484。或者，接触焊盘可以选择形成在下层1400上。
在一个示例中，隔离耦合元件250在初级线圈和次级线圈之间具有3:10的匝数比。在另一示例中，隔离耦合元件250在100kHz下提供50nH的互感。在又一个示例中，隔离耦合元件250提供高达5.5kVrms的电流隔离。在一个示例中，隔离耦合元件250形成在四层PCB上。在另一示例中，隔离耦合元件250形成为尺寸为9.5mm×5.5mm×1.8mm或更小的独立部件。隔离耦合元件250可以设置在第一PCB 120上或第二PCB 140上。
在本发明的示例中，图3A的充电器100还包括设置在第一PCB 120和第二PCB 140之间的空间中的可选的第三PCB 160。第三PCB 160垂直于第一PCB 120和第二PCB 140。在一个示例中，多针输出互连插座281安装在第三PCB 160的面向外壳110的顶表面上的开口180的边缘上。在另一个示例中，第三PCB 160包括设置在其上的隔离耦合元件250。在本发明的示例中，隔离耦合元件250是安装在第三PCB上或嵌入在第三PCB中的独立元件。
在本发明的示例中，充电器100具有大于0.5W/CC的功率密度。在一个示例中，以30mm×33mm×29mm的紧凑尺寸提供18W PD充电器。在另一个示例中，提供30W PD充电器，其紧凑尺寸为39mm×35mm×39mm。在又一个示例中，提供了45W PD充电器，其紧凑尺寸为48mm×48mm×28mm。由本发明的PD充电器提供的功率密度远高于目前市场上可用的移动设备的PD充电器的最大功率密度。
本领域普通技术人员可以认识到，本申请公开的各实施方案是可以修改的。例如，凹槽阵列329的多个行和多个列可以变化。例如，凹槽阵列329中的每一个的尺寸可以变化。本领域普通技术人员可以想到其他修改，并且所有这些修改都被认为落入由权利要求限定的本发明的范围内。

Claims (20)

1.一个充电器，其特征在于，包括：
一个外壳；
第一PCB，包括：
一个变压器，一个储能电容器和一个半导体封装，其中变压器的初级线圈的第一端子接收整流电压，并且半导体封装包括一个主开关晶体管，其中主开关晶体管的漏极引线连接到变压器初级线圈第二端子；
第二PCB与第一PCB分开，第二PCB包括：
输出电容器和二次侧控制器，其中二次侧控制器反馈输入端接收表示输出电压的反馈电压，并产生控制信号；
其中，隔离耦合元件传输来自第二PCB的控制信号，以控制第一PCB上的主开关晶体管的开关操作；
其中从半导体封装的底表面暴露的主开关晶体管的源极引线连接到第一PCB上的源极接触焊盘；其中，源极接触焊盘和从半导体封装的底表面露出的源极引线的连接区域大于漏极接触焊盘和主开关晶体管的漏极引线的连接区域。
2.如权利要求1所述的充电器，其特征在于，其中所述变压器和所述储能电容器设置在所述第一PCB的内层上，并且所述半导体封装设置在与所述第一PCB的内层相对的第一PCB外层上；其中，输出电容器设置在第二PCB的内层上，次级侧控制器设置在与所述第二PCB的内层相对的第二PCB的外层上；并且其中第一PCB的内层面向第二PCB的内层。
3.如权利要求2所述的充电器，其特征在于，其中所述隔离耦合元件设置在所述第一PCB上，用于将所述控制信号从所述第二PCB传输到所述第一PCB。
4.如权利要求2所述的充电器，其特征在于，其中所述隔离耦合元件设置在所述第二PCB上，用于将所述控制信号从所述第二PCB传输到所述第一PCB。
5.如权利要求2所述的充电器，其特征在于，其中所述第二PCB还包括PD控制器，所述控制器具有MCU以与负载通信，所述PD控制器设置在所述第二PCB的外部层上。
6.如权利要求5所述的充电器，其特征在于，其中所述第二PCB还包括设置在所述第二PCB的内层上的多针输出互连插座。
7.如权利要求6所述的充电器，其特征在于，其中所述二次侧控制器是COT控制器。
8.如权利要求7所述的充电器，其特征在于，其在充电操作中提供的功率密度大于0.6W/cc。
9.如权利要求5所述的充电器，其特征在于，还包括第三PCB，其中第三PCB垂直于第一PCB和第二PCB。
10.如权利要求9所述的充电器，其特征在于，还包括设置在第三PCB边缘上的多针输出互连插座。
11.如权利要求9所述的充电器，其特征在于，其中第三PCB包括多层PCB，隔离耦合元件是一个嵌入形成在第三PCB中的无芯印刷电路板变压器。
12.如权利要求9所述的充电器，其特征在于，其中隔离耦合元件是一个安装在第三PCB上的独立无芯印刷电路板变压器。
13.如权利要求1所述的充电器，其特征在于，所述源极接触焊盘与暴露于所述半导体封装底面的源引线的连接面积至少比所述漏极接触焊盘与所述主开关晶体管的漏引线的连接面积大10倍。
14.如权利要求1所述的充电器，其特征在于，其中源极接触焊盘还连接延伸到第一PCB上的其它导电区域。
15.如权利要求1所述的充电器，其特征在于，其中所述第一PCB包括第一层和最后一层之间的一个或多个中间层；并且，在所述一个或多个中间层和所述最后一层上形成一个或多个导电区域与所述源极接触焊盘电连接。
16.如权利要求1所述的充电器，其特征在于，其中形成于第一PCB的中间层上的导电区域基本上延伸第一PCB的整个中间层区域，除了导电孔的位置和它们之间的互连区域以外。
17.如权利要求1所述的充电器，其特征在于，其中所述二次侧控制器还包括同步开关晶体管，所述同步开关晶体管具有连接到二次线圈的第二端子的漏极引线和连接到地的源极引线；其中第二PCB源极接触焊盘和从二次侧控制器的底面暴露的同步开关晶体管源极引线的连接区域大于第二印刷电路板漏极接触焊盘和同步场效应晶体管的漏极引线的连接区域。
18.如权利要求17所述的充电器，其特征在于，其中源极接触焊盘还连接延伸到第二PCB上的其它导电区域。
19.如权利要求18所述的充电器，其特征在于，其中所述第二PCB包含在第一层和最后一层之间的一个或多个中间层；并且，在所述一个或多个中间层和所述最后一层上形成一个或多个导电区域与所述源极接触焊盘电连接。
20.如权利要求18所述的充电器，其特征在于，其中形成在第二PCB的中间层上的导电区域基本上延伸第二PCB的整个中间层区域，除了导电孔的位置和它们之间的互连区域以外。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278264B1 (en) * 2000-02-04 2001-08-21 Volterra Semiconductor Corporation Flip-chip switching regulator
CN1739197A (zh) * 2003-10-22 2006-02-22 大动力有限公司 在基板栅格阵列封装中应用的dc－dc转换器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020105009A1 (en) 2000-07-13 2002-08-08 Eden Richard C. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
US7154174B2 (en) * 2003-02-27 2006-12-26 Power-One, Inc. Power supply packaging system
US8169185B2 (en) * 2006-01-31 2012-05-01 Mojo Mobility, Inc. System and method for inductive charging of portable devices
US7851856B2 (en) * 2008-12-29 2010-12-14 Alpha & Omega Semiconductor, Ltd True CSP power MOSFET based on bottom-source LDMOS
JP5902010B2 (ja) 2012-03-19 2016-04-13 トランスフォーム・ジャパン株式会社 化合物半導体装置及びその製造方法
US8766430B2 (en) * 2012-06-14 2014-07-01 Infineon Technologies Ag Semiconductor modules and methods of formation thereof
JP2014138111A (ja) * 2013-01-17 2014-07-28 Fujitsu Ltd 半導体装置及びその製造方法、電源装置、高周波増幅器
TWI538376B (zh) * 2014-06-19 2016-06-11 沈志隆 具超高昇降壓比之創新電能轉換裝置
JP6237554B2 (ja) * 2014-09-24 2017-11-29 アイシン・エィ・ダブリュ株式会社 電力変換装置の制御基板
US9960664B2 (en) 2014-12-07 2018-05-01 Alpha And Omega Semiconductor Incorporated Voltage converter
US9824949B2 (en) * 2015-03-11 2017-11-21 Gan Systems Inc. Packaging solutions for devices and systems comprising lateral GaN power transistors
DE202015105092U1 (de) * 2015-09-28 2015-10-29 Tbs Avionics Co Ltd Elektronisches Bauteil
CN110165442B (zh) * 2018-02-12 2020-11-03 泰达电子股份有限公司 金属块焊接柱组合及其应用的电源模块

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278264B1 (en) * 2000-02-04 2001-08-21 Volterra Semiconductor Corporation Flip-chip switching regulator
CN1739197A (zh) * 2003-10-22 2006-02-22 大动力有限公司 在基板栅格阵列封装中应用的dc－dc转换器

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