CN112151615A - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

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CN112151615A
CN112151615A CN202010582091.XA CN202010582091A CN112151615A CN 112151615 A CN112151615 A CN 112151615A CN 202010582091 A CN202010582091 A CN 202010582091A CN 112151615 A CN112151615 A CN 112151615A
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semiconductor layer
semiconductor device
silicon
layer
lower semiconductor
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卢昶佑
裵东一
裵金钟
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明涉及半导体器件和制造半导体器件的方法。该半导体器件包括：在衬底上的掩埋绝缘层；在掩埋绝缘层上的下半导体层，下半导体层包括第一材料；在下半导体层上的沟道图案，沟道图案与下半导体层间隔开并且包括与第一材料不同的第二材料；以及围绕沟道图案的至少一部分的栅电极。

Description

半导体器件和制造半导体器件的方法
技术领域
实施方式涉及半导体器件和制造半导体器件的方法。
背景技术
作为用于增大半导体器件的密度的按比例缩放技术，可以考虑其中鳍型硅体或纳米线形硅体形成在衬底上并且栅极形成在硅体的表面上的多栅晶体管。
多栅晶体管可以使用三维(3D)沟道，并且可以促进多栅晶体管的按比例缩放。可以在不增加多栅晶体管的栅极长度的情况下提高电流控制能力。另外，可以有效地抑制其中沟道区域的电位受漏极电压影响的短沟道效应(SCE)。
发明内容
实施方式可以通过提供一种半导体器件来实现，该半导体器件包括：在衬底上的掩埋绝缘层；在掩埋绝缘层上的下半导体层，下半导体层包括第一材料；在下半导体层上的沟道图案，沟道图案与下半导体层间隔开并且包括与第一材料不同的第二材料；以及围绕沟道图案的至少一部分的栅电极。
实施方式可以通过提供一种半导体器件来实现，该半导体器件包括：在衬底上的下半导体层，下半导体层包括第一材料；在下半导体层上的堆叠结构，堆叠结构包括导电图案和在导电图案上的上半导体层，上半导体层包括与第一材料不同的第二材料；以及在下半导体层上的源极/漏极区域，源极/漏极区域连接到上半导体层。
实施方式可以通过提供一种半导体器件来实现，该半导体器件包括：硅衬底；在硅衬底上的掩埋绝缘层，掩埋绝缘层包括氧化物；在掩埋绝缘层上的下半导体层，下半导体层包括凹陷；与下半导体层间隔开的第一硅沟道图案；在第一硅沟道图案上的第二硅沟道图案；在下半导体层上的栅电极，栅电极围绕第一硅沟道图案和第二硅沟道图案的至少一部分；以及源极/漏极区域，连接到第一硅沟道图案和第二硅沟道图案并且填充凹陷的至少一部分，其中下半导体层包括与第一硅沟道图案和第二硅沟道图案的材料不同的材料。
附图说明
通过参照附图详细描述示例性实施方式，特征对本领域技术人员将明显，附图中：
图1示出了根据一些实施方式的半导体器件的示意性剖视图。
图2至图9示出了根据一些实施方式的制造图1的半导体器件的方法中的阶段的示意性剖视图。
图10示出了根据一些实施方式的半导体器件的示意性剖视图。
图11示出了根据一些实施方式的半导体器件的示意性剖视图。
图12和图13示出了根据一些实施方式的制造图11的半导体器件的方法中的阶段的示意性剖视图。
图14示出了根据一些实施方式的半导体器件的示意性剖视图。
具体实施方式
图1示出了根据一些实施方式的半导体器件的示意性剖视图。
参照图1，根据一些实施方式的半导体器件可以包括：衬底100；在衬底100上的掩埋绝缘层110；在掩埋绝缘层110上的下半导体层200；以及在下半导体层200上的导电图案400、第一沟道图案320_1、第二沟道图案320_2、第三沟道图案320_3、栅极间隔物108、盖图案350和多个接触800。导电图案400可以包括栅电极330和栅极绝缘层220。在一实现方式中，如图1所示，可以包括(例如在衬底100的厚度方向上堆叠)多个沟道图案320_1、320_2和320_3中的三个以及多个导电图案400中的三个。在一实现方式中，第一沟道图案320_1、第二沟道图案320_2和第三沟道图案320_3可以被统称为多个沟道图案320_1、320_2和320_3。
衬底100可以是例如硅衬底，或者可以包括其他材料，诸如硅锗、铟锑化物、铅碲化合物、铟砷化物、铟磷化物、镓砷化物或镓锑化物。当在此使用时，术语“或”不是排他性术语，例如，“A或B”将包括A、B或A和B。在一实现方式中，衬底100可以具有形成在基础衬底上的外延层。
在一实现方式中，掩埋绝缘层110可以包括例如硅氧化物、硅氮氧化物、硅氮化物或其组合。为了简化描述，掩埋绝缘层110由硅氧化物制成的情况将作为示例被描述。
例如，衬底100和在衬底100上的掩埋绝缘层110可以是绝缘体上硅(SOI)。在一实现方式中，掩埋绝缘层110可以是SOI衬底100的掩埋氧化物(BOX)层或在SOI衬底100上的掩埋氧化物(BOX)层。
下半导体层200可以在掩埋绝缘层110上。下半导体层200可以由例如硅锗(SiGe)形成或包括例如硅锗(SiGe)。在根据一些实施方式的制造半导体器件的工艺中，可以增加硅锗的厚度，以帮助降低当形成源极/漏极凹陷时发生未蚀刻现象的可能性或防止当形成源极/漏极凹陷时发生未蚀刻现象。硅锗可以与在半导体制造工艺期间形成的牺牲层的材料相同，并且当去除牺牲层时，也可以部分地去除构成下半导体层200的硅锗。例如，根据制造半导体器件的方法，在制造之后保留在半导体器件中的下半导体层200的厚度可以是薄的，从而抑制根据一些实施方式的半导体器件的泄漏电流，并且还减小泄漏电容。
导电图案400可以在下半导体层200上。导电图案400可以包括栅电极330。在一实现方式中，栅电极330可以包括例如TiN、WN、TaN、Ru、TiC、TaC、Ti、Ag、Al、TiAl、TiAlN、TiAlC、TaCN、TaSiN、Mn、Zr、W或Al。在一实现方式中，栅电极330可以由例如Si、SiGe等而非金属形成，或包括例如Si、SiGe等而非金属。在一实现方式中，栅电极330可以例如通过替换工艺形成。
导电图案400还可以包括围绕栅电极330的栅极绝缘层220。在一实现方式中，栅极绝缘层220可以具有例如围绕除了最上面的栅电极330的上表面以外(例如，除了在衬底100远侧的栅电极330的背对衬底100的表面以外)的栅电极的每个表面的形状。栅极绝缘层220可以包括具有比硅氧化物层的介电常数高的介电常数的高电介质材料。在一实现方式中，高电介质材料可以包括例如铪氧化物、铪硅氧化物、镧氧化物、镧铝氧化物、锆氧化物、锆硅氧化物、钽氧化物、钛氧化物、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、钇氧化物、铝氧化物、铅钪钽氧化物或铅锌铌酸盐。
包括上半导体层(例如沟道图案)的堆叠结构500可以在下半导体层200上。在包括上半导体层的堆叠结构500中，多个沟道图案320_1、320_2和320_3以及被栅极绝缘层220围绕的栅电极330可以交替地堆叠。
在一实现方式中，多个沟道图案320_1、320_2和320_3可以包括例如作为元素半导体材料的硅(Si)或锗(Ge)。在一实现方式中，多个沟道图案320_1、320_2和320_3可以包括化合物半导体，例如IV-IV族化合物半导体或III-V族化合物半导体。
例如，当多个沟道图案320_1、320_2和320_3包括IV-IV族化合物半导体时，多个沟道图案320_1、320_2和320_3可以包括包含例如碳(C)、硅(Si)、锗(Ge)和锡(Sn)中的至少两种元素的二元化合物或三元化合物，或包括掺有IV族元素的上述化合物。例如，当多个沟道图案320_1、320_2和320_3包括III-V族化合物半导体时，多个沟道图案320_1、320_2和320_3可以包括通过将铝(Al)、镓(Ga)和铟(In)中的至少一种作为III族元素与磷(P)、砷(As)和锑(Sb)中的一种作为V族元素结合而形成的二元化合物、三元化合物或四元化合物。
盖图案350可以在栅电极330和栅极绝缘层220的上表面上。盖图案350可以包括绝缘材料。
在一实现方式中，可以省略盖图案。
栅极间隔物108可以在栅极绝缘层220和盖图案350的两个侧表面上。例如，栅极绝缘层220、栅电极330和盖图案350可以填充由栅极间隔物108的内侧壁形成的沟槽。
在一实现方式中，栅极间隔物108可以包括例如硅氮化物(SiN)、硅氮氧化物(SiON)、硅氧化物(SiO2)、硅氧碳氮化物(SiOCN)或其组合。
源极/漏极区域700可以连接到下半导体层200以及包括导电图案400和上半导体层的堆叠结构500。在一实现方式中，源极/漏极区域700可以具有小于在第二方向(Y方向)上的最大宽度的在第一方向(X方向)上的最大宽度。源极/漏极区域700的侧壁可以具有弯曲形状，并且当多个沟道图案320_1、320_2和320_3是PMOS硅沟道图案时，可以通过向多个沟道图案320_1、320_2和320_3施加应力来提高沟道迁移率。
硅化物层900可以在源极/漏极区域700上，并且多个接触800可以在硅化物层900上。
根据一些实施方式的半导体器件的下半导体层200可以具有(在第二方向Y上的)第一厚度Dl，该第一厚度Dl可以小于下面将描述的第二厚度D2和第三厚度D3。例如，可以最小化半导体器件(例如下半导体层200)与源极/漏极相接的区域，从而减小截止(OFF)状态下的泄漏电流或泄漏电容。
在一实现方式中，当制造根据一些实施方式的半导体器件时，下半导体层200可以形成为具有第二厚度D2，该第二厚度D2可以相对较厚(例如，与第一厚度D1相比)。例如，当形成用于形成源极/漏极区域700的凹陷时，可以防止源极/漏极区域700的(在-Y方向上的)最下表面穿过下半导体层200并到达掩埋绝缘层110，并且还可以防止其中源极/漏极区域700形成为未到达下半导体层200的蚀刻现象。
在一实现方式中，当在Y方向上测量时，下半导体层200的厚度D1可以小于沟道图案320_1、320_2和320_3的厚度。
图2至图9示出了根据一些实施方式的制造图1的半导体器件的方法中的阶段的示意性剖视图。在下面的描述中，可以省略多余的描述。
参照图2，下半导体层200可以在衬底100上的掩埋绝缘层110上形成。(其中牺牲层210和第一沟道图案320_1依次堆叠的)第一初始堆叠结构300_1可以在下半导体层200上形成。(其中牺牲层210和第二沟道图案320_2依次堆叠的)第二初始堆叠结构300_2可以在第一初始堆叠结构300_1上形成。(其中牺牲层210和第三沟道图案320_3依次堆叠的)第三初始堆叠结构300_3可以在第二初始堆叠结构300_2上形成。在一实现方式中，初始堆叠结构300_1、300_2和300_3中的每个还可以包括牺牲层210和沟道图案。
牺牲层210中的每个可以包括相同的材料。牺牲层210和多个沟道图案320_1、320_2和320_3可以包括不同的材料。在一实现方式中，每个牺牲层210可以在Y方向上具有第三厚度D3，Y方向是衬底的厚度方向。在一实现方式中，每个牺牲层210可以具有不同的厚度。下面将描述每个牺牲层210具有相同的第三厚度D3的情况。
在一实现方式中，每个牺牲层210可以包括硅锗。另外，多个沟道图案320_1、320_2和320_3可以包括相对于牺牲层210具有蚀刻选择性的材料。
在一实现方式中，多个沟道图案320_1、320_2和320_3可以包括可用作晶体管的沟道区域的材料。例如，在PMOS的情况下，多个沟道图案320_1、320_2和320_3可以包括具有高空穴迁移率的材料，在NMOS的情况下，多个沟道图案320_1、320_2和320_3可以包括具有高电子迁移率的材料。在下文中，描述的是多个沟道图案320_1、320_2和320_3包括硅。
当多个沟道图案320_1、320_2和320_3中的每个包括硅时，它们可以被描述为多个硅沟道图案。
在掩埋绝缘层110上的下半导体层200可以在Y方向上具有第二厚度D2，Y方向是衬底100的厚度方向。第二厚度D2可以大于图1的第一厚度D1(例如，在最终制备好的器件中下半导体层200在Y方向上的厚度)。在一实现方式中，第二厚度D2可以大于第三厚度D3。在一实现方式中，第二厚度D2可以等于第三厚度D3。
在一实现方式中，掩埋绝缘层110可以包括例如硅氧化物(SiO2)、硅氮化物(SiN)、硅氮氧化物(SiON)或其组合。
下半导体层200可以以与牺牲层210相同的方式包括硅锗。例如，在根据一些实施方式的制造半导体器件的工艺中，可以调节下半导体层200的第二厚度D2，以帮助防止当形成源极/漏极凹陷时发生未蚀刻现象。
在一实现方式中，下半导体层200可以以与牺牲层210相同的方式包括硅锗，并且当如下所述地去除牺牲层210时，也可以部分地去除下半导体层200，使得根据一些实施方式的半导体器件的下半导体层200可以形成为具有小于最初第二厚度D2的第一厚度D1。
例如，根据一些实施方式的半导体器件的下半导体层200的第一厚度D1可以小于在根据一些实施方式的制造半导体器件的工艺期间的第二厚度D2(例如中间厚度)，从而减小截止状态下泄漏电流或泄漏电容的影响。
下半导体层200的硅锗中的锗的第一比例或浓度可以小于牺牲层210的硅锗中的锗的第二比例或浓度。在去除牺牲层210的工艺中，去除速率可以取决于硅锗中的锗的比例而变化。例如，硅锗中的锗的比例越小，去除速率越快。例如，如果下半导体层200中的锗的比例小于牺牲层210中的锗的比例，则在去除牺牲层210的工艺中，下半导体层200可以比牺牲层210被更快地去除，这将在下面被描述。
例如，通过降低下半导体层200中的锗的比例，可以进一步增加下半导体层200的第二厚度D2。例如，可以抑制在根据一些实施方式的制造半导体器件的工艺期间发生的未蚀刻现象，并且还可以在去除牺牲层210期间更快地去除下半导体层200。例如，可以减小根据一些实施方式的半导体器件的下半导体层200的第一厚度D1，从而抑制根据一些实施方式的半导体器件的截止状态下的泄漏电流或泄漏电容。
通过使用在第三初始堆叠结构300_3上的掩模图案，可以形成牺牲栅极104和在牺牲栅极104上的掩模图案106。牺牲栅极104可以包括例如多晶硅或非晶硅。
然后，参照图3，栅极间隔物108可以共形地形成，以覆盖第三初始堆叠结构300_3的上表面、牺牲栅极104的侧表面以及掩模图案106的上表面和侧表面。
在一实现方式中，栅极间隔物108可以包括例如硅氮化物(SiN)、硅氮氧化物(SiON)、硅氧化物(SiO2)、硅氧碳氮化物(SiOCN)或其组合。
然后，参照图4，可以蚀刻栅极间隔物108，以形成暴露下半导体层200的至少一部分的源极/漏极凹陷R1。
在根据一些实施方式的制造半导体器件的方法中，可以选择下半导体层200的第二厚度D2，使得当形成源极/漏极凹陷R1时不发生未蚀刻现象。
例如，具有足够厚的第二厚度D2的下半导体层200可以帮助防止源极/漏极凹陷R1的最下表面在-Y方向上穿过下半导体层200并且到达掩埋绝缘层110。还可以防止其中下半导体层200完全没被蚀刻的未蚀刻现象。
源极/漏极凹陷R1的侧表面可以具有弯曲形状，该弯曲形状在多个沟道图案320_1、320_2和320_3是P型硅图案时可以增大应力，从而进一步提高沟道中电荷的迁移率。
在根据一些实施方式的制造半导体器件的方法中，源极/漏极凹陷R1的侧表面的形状可以具有除了弯曲形状之外的形状。在一实现方式中，源极/漏极凹陷R1的最下表面可以在下半导体层200内的合适位置处。
随后，参照图5，源极/漏极区域700可以通过外延工艺形成在源极/漏极凹陷R1中。源极/漏极区域700的(例如在衬底100远侧的)最上表面可以在Y方向上比第三初始堆叠结构300_3的第三沟道图案320_3的最上表面更高(例如，在Y方向上离衬底更远)。
随后，参照图6，层间绝缘层225可以被形成，以覆盖源极/漏极区域700、栅极间隔物108和掩模图案106。图6示出了在形成层间绝缘层225之后通过化学机械抛光(CMP)工艺使层间绝缘层225、栅极间隔物108和掩模图案106的上表面平坦化后的状态。
层间绝缘层225可以包括例如硅氧化物、硅氮化物、硅氮氧化物或具有比硅氧化物低的介电常数的低介电常数材料。在一实现方式中，低介电常数材料可以包括例如可流动的氧化物(FOX)、东燃硅氮烷(Tonen Silazane)(TOSZ)、无掺杂的硅酸盐玻璃(USG)、硼硅酸盐玻璃(BSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、等离子体增强原硅酸四乙酯(PETEOS)、氟化物硅酸盐玻璃(FSG)、掺碳的硅氧化物(CDO)、干凝胶、气凝胶、非晶氟化碳、有机硅酸盐玻璃(OSG)、聚对二甲苯、双苯并环丁烯(BCB)、SiLK、聚酰亚胺、多孔聚合材料或其组合。
随后，参照图7，可以去除牺牲层210。作为参考，在图7中，为了在根据一些实施方式的制造半导体器件的方法中的描述的方便，保持下半导体层200的第二厚度D2。
在根据一些实施方式的制造半导体器件的方法中，下半导体层200中的锗的比例可以小于牺牲层210中的锗的比例，并且当去除牺牲层210时，可以更快地去除下半导体层200。例如，下半导体层200的厚度可以从(中间的)第二厚度D2减小到图8的(最终的)第一厚度D1。
根据一些实施方式，可以根据半导体器件来调节或选择下半导体层200的厚度和锗的比例。例如，为了在根据一些实施方式的制造半导体器件的工艺期间形成具有厚的厚度的下半导体层200并且在根据该制造方法形成的根据一些实施方式的半导体器件中最终形成具有非常薄的第一厚度D1的下半导体层200，可以通过降低下半导体层200中的锗的比例使得在根据一些实施方式的制造半导体器件的方法的最初步骤中形成的下半导体层200的第二厚度D2变得更厚来制造根据一些实施方式的半导体器件。
随后，参照图8，在已经去除了牺牲层的位置处，栅极绝缘层220可以沿着其中已经去除了牺牲层的空间的侧壁形成。然后，通过在栅极绝缘层220中填充导电材料，可以形成栅电极330。
在依照根据一些实施方式的制造半导体器件的方法的半导体器件中，下半导体层200可以在去除牺牲层期间以高速率部分地去除，因而可以使第一厚度D1小于第二厚度D2。
随后，参照图9，在去除牺牲栅极104和掩模图案106之后，另一栅极绝缘层220可以沿着形成在栅极间隔物108中的沟槽的侧壁形成。然后，另一栅电极330可以通过在栅极绝缘层220中填充导电材料而形成。盖图案350可以形成在栅电极330的上表面和栅极绝缘层220的表面上。
再次参照图1，在图9的工艺之后，通过去除层间绝缘层225，硅化物层900可以形成在源极/漏极区域700上，并且多个接触800可以形成在硅化物层900上。例如，多个接触800可以将电信号传输到源极/漏极区域700。
图10示出了根据一些实施方式的半导体器件的示意性剖视图。在下面的描述中，可以省略多余的描述。
参照图10，下半导体层200可以包括第一子半导体层201和第二子半导体层202。第一子半导体层201可以具有第一_第一厚度D1_1，第二子半导体层202可以具有第一_第二厚度D1_2。在一实现方式中，第一_第一厚度D1_1和第一_第二厚度D1_2可以是不同的厚度。
在根据一些实施方式的半导体器件中，下半导体层200的第一子半导体层201可以包括硅，并且下半导体层200的第二子半导体层202可以包括硅锗。
例如，通过分别调节第一子半导体层201的第一_第一厚度Dl_1和第二子半导体层202的第一_第二厚度D1_2，可以调节下半导体层200的第一厚度。例如，通过调节第二子半导体层202中包括的锗的比例，可以调节当去除牺牲层时去除下半导体层200的第二子半导体层202的速率。
除了图2的下半导体层200包括第一子半导体层201和第二子半导体层202以外，制造根据一些实施方式的图10的半导体器件的方法是类似的，其重复的描述被省略。
图11示出了根据一些实施方式的半导体器件的示意性剖视图。
与根据一些实施方式的图1的半导体器件不同，图11的半导体器件还可以包括在栅极绝缘层220与源极/漏极区域700之间的内间隔物308。例如，内间隔物308可以在围绕源极/漏极区域700之间的栅电极330的栅极绝缘层220的侧表面上。
内间隔物308可以包括例如低介电常数材料、硅氮化物(SiN)、硅氮氧化物(SiON)、硅氧化物(SiO2)、硅氧碳氮化物(SiOCN)或其组合。低介电常数材料可以是具有比硅氧化物低的介电常数的材料。
图12和图13示出了根据一些实施方式的制造图11的半导体器件的方法中的阶段的示意性剖视图。
根据一些实施方式的制造图11的半导体器件的方法的一些中间步骤与图2至图4的步骤相同，将描述在图4的步骤之后的步骤。
参照图12，牺牲层210的被源极/漏极凹陷R1暴露的部分可以被蚀刻。例如，牺牲层210可以通过选择性蚀刻工艺被蚀刻。
通过牺牲层210的蚀刻工艺，内间隔物凹陷SR可以被形成，使得牺牲层210的侧壁比多个沟道图案320_1、320_2和320_3中的每个的由源极/漏极凹陷R1暴露的侧壁(例如在X方向上)更加凹入。
随后，参照图13，内间隔物308可以沿着由源极/漏极凹陷R1暴露的侧壁形成。然后，可以去除(除了形成在多个沟道图案320_1、320_2和320_3之间的内间隔物308以外的)剩余部分。
后续步骤与图5至图9的步骤相同，并且在图9的步骤之后形成图11的半导体器件的工艺也是类似的，其描述被省略。
图14示出了根据一些实施方式的半导体器件的示意性剖视图。
参照图14，与图1的半导体器件不同，下半导体层200可以包括第一子半导体层201和第二子半导体层202，并且该半导体器件可以包括内间隔物308。下半导体层200包括第一子半导体层201和第二子半导体层202的特征类似于图10的半导体器件的特征。包括内间隔物308的特征类似于图11的半导体器件的特征，其描述被省略。
作为总结和回顾，半导体器件变得更小且在性能方面变得更高。例如，包括在半导体器件中的晶体管的小的结构差异可能对半导体器件的性能具有大的影响。为了满足性能要求，可以使用绝缘体上硅(SOI)衬底。
为了在SOI衬底上形成晶体管结构，硅(Si)层可以形成在形成SOI衬底的掩埋绝缘层上。如果掩埋绝缘层上的硅层的厚度太薄，则当在制造半导体器件的工艺中形成源极/漏极凹陷时，由于缺少余量而可能发生未蚀刻现象。如果掩埋绝缘层上的硅层的厚度太厚，则半导体器件的泄漏电流可能增大。
一个或更多个实施方式可以包括在掩埋绝缘层上形成硅锗(SiGe)层而非硅层，以通过在制造半导体器件的工艺期间形成厚的硅锗层来增加余量，并且通过在制造半导体器件之后保持硅锗层的薄的厚度来减小半导体器件的泄漏电流。
一个或更多个实施方式可以提供具有提高的产品可靠性的半导体器件。
一个或更多个实施方式可以提供用于制造具有提高的产品可靠性的半导体器件的方法。
这里已经公开了示例实施方式，并且尽管采用了特定术语，但是它们仅在一般性和描述性的意义上被使用和解释，而不是出于限制的目的。在一些情形下，如在提交本申请时对本领域普通技术人员将明显的，结合特定实施方式描述的特征、特性和/或元件可以单独使用，或与结合其它实施方式描述的特征、特性和/或元件组合使用，除非另有明确指示。因此，本领域技术人员将理解，在不背离本发明的如所附权利要求中阐明的精神和范围的情况下，可以进行在形式和细节上的各种改变。
2019年6月26日在韩国知识产权局提交的名称为“半导体器件和制造半导体器件的方法”的韩国专利申请第10-2019-0076005号通过引用全文合并于此。

Claims (20)

1.一种半导体器件，包括：
在衬底上的掩埋绝缘层；
在所述掩埋绝缘层上的下半导体层，所述下半导体层包括第一材料；
在所述下半导体层上的沟道图案，所述沟道图案与所述下半导体层间隔开并且包括与所述第一材料不同的第二材料；以及
围绕所述沟道图案的至少一部分的栅电极。
2.如权利要求1所述的半导体器件，其中：
所述第一材料包括硅锗(SiGe)，以及
当在所述衬底的厚度方向上测量时，所述下半导体层的厚度小于所述沟道图案的厚度。
3.如权利要求2所述的半导体器件，其中所述下半导体层包括第一子半导体层和在所述第一子半导体层上的第二子半导体层。
4.如权利要求3所述的半导体器件，其中：
所述第一子半导体层包括硅，以及
所述第二子半导体层包括硅锗。
5.如权利要求1所述的半导体器件，还包括在所述下半导体层上的源极/漏极区域，所述源极/漏极区域连接到所述沟道图案。
6.如权利要求5所述的半导体器件，其中，所述第一材料包括硅锗。
7.如权利要求6所述的半导体器件，其中：
所述下半导体层包括源极/漏极凹陷，以及
所述源极/漏极区域的一部分填充所述源极/漏极凹陷。
8.如权利要求7所述的半导体器件，其中，所述源极/漏极区域的侧表面具有弯曲形状。
9.如权利要求1所述的半导体器件，还包括在所述栅电极的侧壁上的内间隔物。
10.一种半导体器件，包括：
在衬底上的下半导体层，所述下半导体层包括第一材料；
在所述下半导体层上的堆叠结构，所述堆叠结构包括导电图案和在所述导电图案上的上半导体层，所述上半导体层包括与所述第一材料不同的第二材料；以及
在所述下半导体层上的源极/漏极区域，所述源极/漏极区域连接到所述上半导体层。
11.如权利要求10所述的半导体器件，其中所述导电图案包括围绕所述上半导体层的至少一部分的栅电极。
12.如权利要求10所述的半导体器件，还包括在所述衬底上的掩埋绝缘层，其中：
所述第一材料包括硅锗，以及
所述第二材料包括硅。
13.如权利要求10所述的半导体器件，其中所述下半导体层包括第一子半导体层和在所述第一子半导体层上的第二子半导体层。
14.如权利要求13所述的半导体器件，其中：
所述第一子半导体层包括硅，以及
所述第二子半导体层包括硅锗。
15.如权利要求14所述的半导体器件，其中所述源极/漏极区域的侧表面具有弯曲形状。
16.如权利要求10所述的半导体器件，还包括在所述堆叠结构的侧壁上的内间隔物。
17.一种半导体器件，包括：
硅衬底；
在所述硅衬底上的掩埋绝缘层，所述掩埋绝缘层包括氧化物；
在所述掩埋绝缘层上的下半导体层，所述下半导体层包括凹陷；
与所述下半导体层间隔开的第一硅沟道图案；
在所述第一硅沟道图案上的第二硅沟道图案；
在所述下半导体层上的栅电极，所述栅电极围绕所述第一硅沟道图案和所述第二硅沟道图案的至少一部分；以及
源极/漏极区域，连接到所述第一硅沟道图案和所述第二硅沟道图案并且填充所述凹陷的至少一部分，
其中所述下半导体层包括与所述第一硅沟道图案和所述第二硅沟道图案的材料不同的材料。
18.如权利要求17所述的半导体器件，其中：
所述下半导体层包括硅锗，以及
当在所述衬底的厚度方向上测量时，所述下半导体层的厚度小于所述第一硅沟道图案和所述第二硅沟道图案的厚度。
19.如权利要求17所述的半导体器件，其中：
所述下半导体层包括第一子半导体层和在所述第一子半导体层上的第二子半导体层，
所述第一子半导体层包括硅，以及
所述第二子半导体层包括硅锗。
20.如权利要求19所述的半导体器件，还包括在所述栅电极上的内间隔物。
CN202010582091.XA 2019-06-26 2020-06-23 半导体器件和制造半导体器件的方法 Pending CN112151615A (zh)

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