TW202133271A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202133271A
TW202133271A TW110100773A TW110100773A TW202133271A TW 202133271 A TW202133271 A TW 202133271A TW 110100773 A TW110100773 A TW 110100773A TW 110100773 A TW110100773 A TW 110100773A TW 202133271 A TW202133271 A TW 202133271A
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gate
semiconductor
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area
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TW110100773A
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楊智銓
林士豪
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台灣積體電路製造股份有限公司
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Abstract

此處揭露包括形成在磊晶源極/汲極區與半導體基底之間的隔離層之奈米結構場效電晶體及其形成方法。在一實施例，一種半導體裝置包括：半導體基底；閘極堆疊物，在半導體基底的上方，閘極堆疊物包括閘極電極與閘極介電質；第一磊晶源極/汲極區，相鄰於閘極堆疊物；以及高介電常數介電質，在半導體基底與第一磊晶源極/汲極區之間延伸，高介電常數介電質接觸第一磊晶源極/汲極區，閘極介電質與高介電常數介電質包括相同的材料。

Description

半導體裝置
本發明實施例是關於半導體製程技術，特別是關於半導體裝置及其形成方法。
半導體裝置是應用於各種電子應用中，例如，個人電腦、行動電話、數位相機及其他電子設備。半導體裝置通常是藉由在半導體基底的上方依序沉積複數個絕緣層或介電層、複數個導電層與複數個半導體材料層，並使用微影技術對各種材料層進行圖形化，以在其上形成複數個電路構件與元件而製造。
半導體產業藉由不斷縮小最小特徵尺寸，使更多的構件能夠集積到給定的面積中，而不斷提高各種電子構件(舉例而言：電晶體、二極體、電阻器、電容器等)的集積密度。然而，隨著最小特徵尺寸的減小，又出現了一些應該解決的問題。
一實施例是關於一種半導體裝置，包括：一半導體基底；一閘極堆疊物，在上述半導體基底的上方，上述閘極堆疊物包括一閘極電極與一閘極介電質；一第一磊晶源極/汲極區，相鄰於上述閘極堆疊物；以及一高介電常數介電質，在上述半導體基底與上述第一磊晶源極/汲極區之間延伸，上述高介電常數介電質接觸上述第一磊晶源極/汲極區，其中上述閘極介電質與上述高介電常數介電質包括相同的材料。
另一實施例是關於一種半導體裝置的形成方法，包括：在一半導體基底的上方沉積一多層堆疊物，上述多層堆疊物包括多層交替排列的一第一半導體材料與一第二半導體材料；在上述多層堆疊物形成一磊晶源極/汲極區，上述磊晶源極/汲極區延伸而至少部分穿過上述多層堆疊物；移除上述多層堆疊物的一第一層與一第二層，以分別形成一第一凹部與一第二凹部；在上述第一凹部與上述第二凹部沉積一閘極介電層，上述閘極介電層填充上述第一凹部以形成一第一隔離層，上述第一隔離層在上述磊晶源極/汲極區與上述半導體基底之間延伸；以及在上述第二凹部沉積一閘極電極材料。
又另一實施例是關於一種半導體裝置的形成方法，包括：在一半導體基底的上方沉積一多層堆疊物，上述多層堆疊物包括在上述半導體基底的上方的一第一犧牲層、在上述第一犧牲層的上方的一第二犧牲層、在上述第二犧牲層的上方的一第一通道層及在上述第一通道層的上方的一第二通道層；形成一第一源極/汲極區，其延伸穿過上述第二通道層、上述第一通道層及上述第二犧牲層而至上述第一犧牲層的一頂表面；使用一第一蝕刻製程，從上述半導體裝置的一第一區蝕刻上述第一通道層與上述第一犧牲層；以及在藉由蝕刻上述第一通道層與上述第一犧牲層而形成的複數個凹部沉積一第一介電層，上述第一介電層填充藉由蝕刻上述第一犧牲層而形成的上述複數個凹部。
以下的揭露內容提供許多不同的實施例或範例以實現本發明實施例的不同構件。以下的揭露內容敘述各個構件及其排列方式的特定實施例或範例，以簡化本發明實施例的說明。當然，這些特定的範例並非用以限定。例如，若是本發明實施例敘述了一第一構件形成於一第二構件之上或上方，即表示其可能包括上述第一構件與上述第二構件是直接接觸的實施例，亦可能包括了有附加構件形成於上述第一構件與上述第二構件之間，而使上述第一構件與第二構件可能未直接接觸的實施例。此外，本發明實施例可能會在各種實施例重複使用相同的元件符號。這樣的重複是為了敘述上的簡化與明確，而非意指所討論的不同實施例及/或結構之間的關係。
此外，其與空間相關用詞。例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，係為了便於描述圖示中一個元件或構件與另一個(些)元件或構件之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包括使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
各種實施例提供了具有低漏電流與改進效能的半導體裝置及其形成方法。上述半導體裝置可以是奈米結構(舉例而言：奈米片、奈米線、全繞式閘極或類似結構)場效電晶體(nanostructure  field-effect transistors；NSFETs)。在用於形成奈米結構場效電晶體中的通道區的半導體層下方的 N型金屬—氧化物—半導體(NMOS)區與P型金屬—氧化物—半導體(PMOS)區中，可以提供複數個薄半導體層。上述薄半導體層可以用例如高介電常數(高k值)介電材料等的介電材料來代替。上述介電材料可以在上述奈米結構場效電晶體的塊體區域(bulk regions)與上述奈米結構場效電晶體的各個源極/汲極區、通道區和閘極之間延伸。上述介電材料減少了從上述源極/汲極區到上述塊體區域的漏電流，避免已完成的半導體裝置中的閂鎖效應的問題，並改善裝置效能。
第1圖顯示根據一些實施例的奈米結構場效電晶體的三維視圖的一範例。上述奈米結構場效電晶體包括在一基底50(舉例而言：半導體基底)的上方的複數個奈米結構55。在基底50設置複數個隔離區(淺溝槽隔離區68)，奈米結構55設置在高於相鄰的隔離區域68之處且設置在相鄰的上述隔離區(淺溝槽隔離區68)之間。儘管將描述/圖示敘述/圖示為與基底50分離，但在本文所使用的用語「基底」可單獨指半導體基底或指半導體基底與上述隔離區的組合。此外，基底50可包括單一材料或複數種材料。
複數個閘極介電層96是沿著基底50的側壁且在基底50的頂表面的上方並且沿著奈米結構55的頂表面、側壁與底表面。複數個閘極電極98在閘極介電層96的上方。複數個磊晶源極/汲極區90設置於奈米結構55、閘極介電層96與閘極電極98相對於閘極電極98的一縱軸的兩側。第1圖進一步繪示在後續的圖式中使用的參考剖面。參考剖面A-A'是沿著閘極電極98的一縱軸，並且在垂直於例如一奈米結構場效電晶體的磊晶源極/汲極區90之間的電流流動方向的方向。參考剖面B-B'垂直於參考剖面A-A'，並且沿著上述奈米結構場效電晶體的一第一導電區中的一奈米結構55的縱軸，並且在例如上述奈米結構場效電晶體的磊晶源極/汲極區90之間的電流流動方向。參考剖面C-C'平行於參考剖面B-B'，並且在上述奈米結構場效電晶體的一第二導電區中延伸而穿過一奈米結構55。參考剖面D-D'平行於參考剖面A-A'，並且延伸而穿過上述奈米結構場效電晶體的磊晶源極/汲極區90。後續圖式為了清楚起見，參考了這些參考剖面。
本文討論的一些實施例是在使用一閘極後製(gate-last)製程形成的奈米結構場效電晶體的背景下討論的。在其他實施例中，可以使用一閘極先製(gate-first)製程。此外，一些實施例考慮了在例如平面場效電晶體(planar FET)等的平面裝置中使用的面向，或在鰭式場效電晶體(fin field-effect transistors；FinFET) 中使用的面向。
第2至18C圖是根據一些實施例的製造奈米結構場效電晶體的中間階段的剖面圖。第2至5、6A、12A、13A、14A、15A、16A、17A與18A圖顯示第1圖所顯示的參考剖面A-A'。第6B與7圖顯示第1圖所顯示的參考剖面B-B'或C-C'。第8A、9A、10A、11A、12B、13B、14B、15B、16B、17B與18B圖顯示第1圖所顯示的參考剖面B-B'。第8B、9B、10B、11B、12C、13C、14C、15C、16C、17C與18C圖顯示第1圖所顯示的參考剖面C-C'。第16D圖顯示第1圖所顯示的參考剖面B-B'與C-C。第11C與11D圖顯示沿著第1圖所顯示的參考剖面D-D'。
在第2圖提供一基底50。基底50可以是一半導體基底，例如一塊體半導體、一絕緣體上覆半導體(semiconductor-on-insulator；SOI)基底或類似的基底，其可以是已摻雜(舉例而言：使用p型或n型摻雜物)或未摻雜。基底50可以是一晶圓，例如矽晶圓。一般而言，一絕緣體上覆半導體基底是形成在一絕緣體層上的一半導體材料層。上述絕緣體層可以是例如一埋入式氧化物(buried oxide；BOX)層、氧化矽層或類似物。將上述絕緣體層提供在一基底上，通常是矽基底或玻璃基底。亦可使用其他基底，例如多層或漸變基底。在一些實施例中，基底50的半導體材料可包括：矽；鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含矽鍺(silicon-germanium)、磷化砷化鎵(gallium arsenide phosphide)、砷化鋁銦(aluminum indium arsenide)、砷化鋁鎵(aluminum gallium arsenide)、砷化鎵銦(gallium indium arsenide)及/或磷化砷化鎵銦(gallium indium arsenide phosphide)；或上述之組合。
基底50具有複數個區域50A與複數個區域50B。區域50A可以是用於形成具有第一導電類型的裝置(舉例而言：n型裝置，例如 N型金屬—氧化物—半導體電晶體或n型奈米結構場效電晶體或p型裝置，例如p型金屬—氧化物—半導體電晶體或p型奈米結構場效電晶體)。區域50B可以是用於形成具有與第一導電類型相反的第二導電類型的裝置。例如，在第一導電類型為p型的實施例中，第二導電類型可以是n型；而在第一導電類型為n型的實施例中，第二導電類型可以是p型。區域50A可以與區域50B(未單獨顯示)物理分離，並且可以在區域50A與區域50B之間設置任何數量的裝置部件(舉例而言：其他主動裝置、摻雜區、隔離結構等)。儘管顯示兩個區域50A與一個區域50B，但可以提供任意數量的區域50A與區域50B。
基底50可以用p型或n型不純物作輕度摻雜。可在基底50的上部進行抗擊穿(anti-punch-through；APT)佈植，以形成抗擊穿區51。在抗擊穿佈植的過程中，可以在區域50A與區域50B佈植摻雜物。上述摻雜物可以具有與將要在各個區域50A與區域50B形成的源極/汲極區的導電類型相反的導電類型。抗擊穿區51可以在後續形成的奈米結構場效電晶體中的源極/汲極區之下延伸，上述奈米結構場效電晶體將在後續的製程形成。抗擊穿區51可用於減少從上述源極/汲極區到基底50的漏電流。在一些實施例中，在抗擊穿區51的摻雜濃度可以為約1×1013 個原子/cm3 至約1×1014 個原子/cm3 。為了簡潔與易懂，抗擊穿區51在後續的圖式中未顯示。
在第2圖中，還在基底50的上方形成多層堆疊物64。多層堆疊物64包括交替排列的不同半導體材料的複數個第一半導體層52與複數個第二半導體層54。上第一半導體層52可以以一第一半導體材料來形成，其可以包含例如矽鍺(SiGe)；III-V族化合物半導體材料，例如砷化鎵(GaAs)、氮化銦(InN)、磷化銦(InP)、磷化鎵(GaP)、氮化鎵(GaN)；或類似材料。第二半導體層54可以以一第二半導體材料來形成，其可以包括例如矽(Si)、矽碳(SiC)或類似的材料。在其他實施例中，第一半導體層52可以以上述第二半導體材料形成，而第二半導體層54可以以上述第一半導體材料形成。為了說明的目的，多層堆疊物64包括三個第一半導體層(舉例而言：第一半導體層52A-52C)與三個第二半導體層 (舉例而言：第二半導體層54A-54C)。在其他實施例中，多層堆疊物64可以包括任意數量的第一半導體層52與第二半導體層54。多層堆疊物64的每個層可以使用例如化學氣相沉積(chemical vapor deposition；CVD)、原子層沉積(atomic layer deposition；ALD)、氣相磊晶(vapor phase epitaxy；VPE)、分子束磊晶(molecular beam epitaxy；MBE)或類似的製程進行磊晶成長。
第一半導體層52A與第二半導體層54A可以是犧牲層，而第一半導體層52B與52C以及第二半導體層54B與54C可以是通道層。如第2圖所示，上述通道層(舉例而言：第一半導體層52B與52C以及第二半導體層54B與54C)的厚度可以大於上述犧牲層(舉例而言：第一半導體層52A與第二半導體層54A)的厚度。例如，上述犧牲層可以具有約4 nm至約6 nm的厚度，例如約5 nm；上述通道層可以具有約8 nm至約10 nm的厚度，例如約9 nm。上述通道層的厚度相對於上述犧牲層的厚度的比值可以為約1.5至約2.5，例如約2。將通道層與犧牲層的厚度最小化並使用上述厚度，可以為n型裝置與p型裝置形成更短的通道，而提高裝置效能。
如以下面將更詳細地討論，包括具有既定厚度的上述通道層與上述犧牲層，進一步得以讓一高介電常數介電質(如以下就第16A-16D圖討論的閘極介電層96)填充藉由移除上述犧牲層而留下的間隙，並得以讓上述高介電常數介電質與一閘極電極(如以下就第16A-16D圖討論的閘極電極98)均填充藉由移除上述通道層而留下的間隙。上述高介電常數介電質用於將後續形成的源極/汲極區(例如以下就第11A-11D圖討論的磊晶源極/汲極區90)隔離於上述通道層與基底50，而減少漏電流，防止閂鎖效應，提高效能，並減少已完成的半導體裝置的缺陷。
在第3圖中，在多層堆疊物64與基底50形成複數個奈米結構55。奈米結構55可以是半導體條(semiconductor strips)。在一些實施例中，可以藉由在多層堆疊物64與基底50中蝕刻出複數個溝槽，而在多層堆疊物64與基底50形成奈米結構55。上述蝕刻可以是任何可接受的蝕刻製程，例如反應性離子蝕刻(reactive ion etch；RIE)、中性束蝕刻(neutral beam etch；NBE)、類似製程或上述之組合。上述蝕刻可以是非等向性。
可以藉由任何合適的方法對奈米結構55進行圖形化。例如，可以使用一種或多種微影製程對奈米結構55進行圖形化，包括雙重圖形化(double-patterning)或多重圖形化(multi-patterning)製程。一般而言，雙重圖形化或多重圖形化製程結合了微影製程與自對準製程，得以產生具有比使用單一的直接微影製程可以獲得的例如間距更小的圖形。例如，在一實施例中，在基底上形成一犧牲層並使用一微影製程進行圖形化。使用一自對準製程在已圖形化的上述犧牲層旁邊形成複數個間隔物。然後移除上述犧牲層，然後可使用留下來的上述間隔物來將奈米結構55圖形化。
如第3圖所示，區域50A中的奈米結構55的寬度可大於區域50B中的奈米結構55的寬度。例如，區域50A中的奈米結構55可以具有約8 nm至約50 nm的寬度，例如約36 nm；區域50B中的奈米結構55可以具有約8 nm至約50 nm的寬度，例如約10 nm。區域50A中的奈米結構55的寬度相對於區域50B中的奈米結構55的寬度之比值可以是約3至約6，例如約3.6。在區域50A中包括較寬的奈米結構55，而在區域50B中包括較窄的奈米結構55，這得以在區域50B中形成較小的半導體裝置，而在區域50A中包括強電晶體(strong transistors)，這提供了具有改進的效能與小尺寸的裝置。在另外的實施例中，區域50B中的奈米結構55的寬度可以大於或等於區域50A中的奈米結構55的寬度。
在第4圖中，形成與奈米結構55相鄰的複數個淺溝槽隔離(shallow trench isolation；STI)區68。淺溝槽隔離區68可以藉由在基底50與奈米結構55的上方且在奈米結構55之間沉積一絕緣材料來形成。上述絕緣材料可以是例如氧化矽等的氧化物、氮化物、類似材料或上述之組合，並且可以藉由高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition；HDP-CVD)、流動式化學氣相沉積(flowable chemical vapor deposition；FCVD)、類似製程或上述之組合而形成。可以使用由任何可接受的製程形成的其他絕緣材料。在圖示的實施例中，上述絕緣材料是由流動式化學氣相沉積製程形成的氧化矽。一旦形成上述絕緣材料，可以施行一退火製程。在一實施例中，上述絕緣材料的形成使得多餘的絕緣材料覆蓋奈米結構55。儘管圖式中顯示上述絕緣材料為單層，但一些實施例可以使用多層的絕緣材料。例如，在一些實施例中，首先可以沿著基底50與奈米結構55的一表面形成一襯墊(liner，未單獨顯示)。其後，可在上述襯墊的上方形成一填充材料，例如上文討論的那些材料。
然後，對上述絕緣材料施以一移除製程，以移除奈米結構55的上方的多餘的絕緣材料。在一些實施例中，可以利用一平坦化製程，例如化學機械研磨(chemical mechanical polish；CMP)、一回蝕製程、上述之組合或類似製程。上述平坦化製程暴露奈米結構55，使得奈米結構55與絕緣材料的頂表面在上述平坦化製程完成後為齊平。
然後，將上述絕緣材料凹陷以形成淺溝槽隔離區68。將上述絕緣材料凹陷，使得區域50A與區域50B中的奈米結構55的上部從相鄰的淺溝槽隔離區68之間突出。此外，淺溝槽隔離區68的頂表面可以具有如圖所示的平坦表面、凸面、凹面(例如為淺碟凹陷(dishing))或上述之組合。淺溝槽隔離區68的上述頂表面可以藉由適當的蝕刻形成平坦、凸面與/或凹面。將淺溝槽隔離區68凹陷，可以使用可接受的蝕刻製程，例如對上述絕緣材料的材料具有選擇性的蝕刻製程(舉例而言：以比奈米結構55的材料更快的速率蝕刻上述絕緣材料的材料)來凹陷。例如，可以使用氧化物移除，其使用例如氫氟酸稀釋溶液(dilute hydrofluoric；dHF)。
就第2圖至第4圖敘述的上述製程僅是可以如何形成奈米結構55的一例。在一些實施例中，奈米結構55可以藉由一磊晶成長製程來形成。例如，可以在基底50的一頂表面的上方形成一介電層，且可以穿透介電層而蝕刻出複數個溝槽以暴露下層的基底50。複數個磊晶結構可以在上述溝槽中磊晶成長，且可以將上述介電層凹陷，使得上述磊晶結構從上述介電層突出以形成奈米結構55。上述磊晶結構可以包括前文討論的交替排列的半導體材料，例如上述第一半導體材料與上述第二半導體材料。在上述磊晶結構是磊晶成長的一些實施例中，磊晶成長的材料可以在成長過程中同步(in situ)摻雜，而可以不在其之前或之後進行佈植，儘管同步摻雜與佈植摻雜可以一起使用。
在第4圖中，還可以在奈米結構55及/或基底50形成適當的井（未單獨顯示）。在一些實施例中，可分別在區域50A與區域50B中形成具有與區域50A與區域50B相反的導電類型的井。P井或N井可以形成在區域50A與區域50B的任何一個中。如下文即將就第16A-16D圖進一步的詳細討論，複數個介電層(如下文就第16A-16D圖討論的閘極介電層96)可以在源極/汲極區(如下文就第11A-11D圖討論的磊晶源極/汲極區90)與基底50之間形成，以將上述源極/汲極區與基底50隔離。上述井可用於防止從上述源極/汲極區向基底50的漏電流。在源極/汲極區與基底50之間提供介電層，得以將上述井省略。
在具有不同井類型的實施例中，可以使用一光阻劑或其他遮罩（未單獨顯示）來達成用於區域50A與區域50B的不同的佈植步驟。例如，可以在區域50A的奈米結構55與淺溝槽隔離區68的上方形成一光阻劑。將上述光阻劑圖形化以暴露基底50的區域50B。上述光阻劑可以藉由使用一旋轉塗佈技術來形成，並且可以使用可接受的微影技術來進行圖形化。一旦將上述光阻劑圖形化，就在區域50B進行n型不純物的佈植或p型不純物的佈植，上述光阻劑可以作為遮罩，以實質上防止將n型不純物或p型不純物植入區域50A。n型不純物可以是磷、砷、銻或類似物，p型不純物可以是硼、氟化硼、銦或類似物。上述區域內的不純物佈植濃度可以等於或小於1×1014 個原子/cm3 ，例如從約1×1013 個原子/cm3 到約1×1014 個原子/cm3 。在上述佈植之後，移除上述光阻劑，例如藉由一可接受的灰化製程。
在區域50B的佈植之後，在區域50B的奈米結構55與淺溝槽隔離區68的上方形成一光阻劑。將上述光阻劑圖形化以暴露基底50的區域50A。上述光阻劑可以藉由使用一旋轉塗佈技術來形成，且可以使用可接受的微影技術來進行圖形化。一旦將上述光阻劑圖形化，可以在區域50A中進行與在區域50B中執行的佈植類型相反的n型不純物佈植類型或p型不純物佈植類型，且上述光阻劑可以作為遮罩，以實質上防止將n型不純物或p型不純物佈植到區域50B中。n型不純物可以是磷、砷、銻或類似物，p型不純物可以是硼、氟化硼、銦或類似物。上述區域內的不純物佈植濃度可以等於或小於1×1014 個原子/cm3 ，例如從約1×1013 個原子/cm3 到約1×1014 個原子/cm3 。在上述佈植之後，移除上述光阻劑，例如藉由一可接受的灰化製程。
在區域50A與區域50B的佈植之後，可進行退火以修復佈植損傷並活化已佈植的p型及/或n型不純物。在一些實施例中，磊晶奈米結構的成長材料可以在成長過程中進行同步摻雜，這可以將佈植省略，儘管同步摻雜與佈植摻雜可以一起使用。
在第5圖中，在奈米結構55上形成一虛設(dummy)介電層70。虛設介電層70可以是例如氧化矽、氮化矽、上述之組合或類似物，並且可以根據可接受的技術來進行沉積或加熱成長。在虛設介電層70的上方形成一虛設閘極層72，並且在虛設閘極層72的上方形成一遮罩層74。虛設閘極層72可以沉積在虛設介電層70的上方，然後將其平坦化，例如藉由化學機械研磨。遮罩層74可以沉積在虛設閘極層72的上方。虛設閘極層72可以是一導體或非導體材料，並且可以選自由非晶矽、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物與金屬所組成之群。虛設閘極層72可以藉由物理氣相沉積(physical vapor deposition；PVD)、化學氣相沉積、濺擊沉積(sputter deposition)或本技術領域已知與已使用的用於沉積所選擇的材料的其他技術來沉積。虛設閘極層72可以由其他材料製得，這些材料對於上述隔離區的蝕刻具有高蝕刻選擇性。遮罩層74可包括例如氮化矽、氮氧化矽或類似材料。在本例中，橫跨區域50A與區域50B而形成一單一的虛設閘極層72與一單一的遮罩層74。需要注意的是，所示的虛設介電層70僅覆蓋鰭狀物66，其僅用於說明目的。在一些實施例中，可以沉積虛設介電層70而使虛設介電層70覆蓋淺溝槽隔離區68，在虛設閘極層72與淺溝槽隔離區68之間延伸。
第6A至18C圖顯示在製造實施例的裝置中的各種附加步驟。第6B圖、第7圖、第11C圖與第11D圖顯示區域50A或區域50B中的部件。具體而言，在第6B圖與第7圖顯示的結構可以適用於區域50A與區域50B二者。在第8A圖、第9A圖、第10A圖、第11A圖、第12B圖、第13B圖、第14B圖、第15B圖、第16B圖、第17B圖與第18B圖顯示的結構說明了區域50A中的部件。在第8B圖、第9B圖、第10B圖、第11B圖、第12C圖、第13C圖、第14C圖、第15C圖、第16C圖、第17C圖與第18C圖顯示的結構說明了區域50B中的部件。第6A圖、第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第16D圖、第17A圖與第18A圖所示的結構說明了區域50A與區域50B中的部件。區域50A與區域50B的結構中的任何差異在每個圖式的對應的發明說明中敘述。
在第6A與6B圖中，可以使用可接受的微影與蝕刻技術對遮罩層74(請見第5圖)進行圖形化，以形成遮罩78。然後，可以將遮罩78的圖形轉移到虛設閘極層72。在一些實施例中(未單獨顯示)，亦可以藉由可接受的蝕刻技術，將遮罩78的圖形轉移到虛設介電層70以形成複數個虛設閘極76。虛設閘極76覆蓋奈米結構55的各自的通道區。可將遮罩78的圖形用於將每個虛設閘極76與相鄰的虛設閘極76物理性分離。虛設閘極76所具有的長度方向還可以實質上垂直於各奈米結構55的長度方向。
在第7圖中，在虛設閘極76、遮罩78及/或奈米結構55的暴露表面上，形成複數個閘極密封間隔物80。一加熱氧化或一沉積後接一非等向性蝕刻可形成閘極密封間隔物80。閘極密封間隔物80可以以氧化矽、氮化矽、氮氧化矽或類似物形成。
在形成閘極密封間隔物80之後，可以進行用於輕摻雜源極/汲極（lightly doped source/drain；LDD）區域（未單獨說明）的佈植。在具有不同裝置類型的實施例中，類似前文於第4圖中討論的佈植，可以在區域50A的上方形成一遮罩，例如光阻劑，同時暴露區域50B，並可以將適當類型的不純物(舉例而言：具有與區域50B相同的導電類型的不純物)佈植到區域50B中暴露的奈米結構55中。然後，可以移除上述遮罩。隨後，可以在區域50B的上方形成一遮罩，例如光阻劑，同時暴露區域50A，並可以將適當類型的不純物(舉例而言：具有與區域50A相同的導電類型的不純物)佈植到區域50A中暴露的奈米結構55中。然後，可以移除上述遮罩。n型不純物可以是先前討論的n型不純物中的任何一種，而p型不純物可以是先前討論的p型不純物中的任何一種。上述輕摻雜源極/汲極區可以具有約1×1015 個原子/cm3 至約1×1019 個原子/cm3 的不純物濃度。可使用退火，以修復佈植物損傷並活化已佈植的不純物。
還是在第7圖中，沿著虛設閘極76與遮罩78的側壁在閘極密封間隔物80上形成複數個閘極間隔物82。閘極間隔物82可以藉由共形(conformally)沉積一絕緣材料並隨後非等向性蝕刻上述絕緣材料而形成。閘極間隔物82的絕緣材料可以是氧化矽、氮化矽、氮氧化矽、氮碳化矽、上述之組合或類似的材料。
需要注意的是，前文的揭露一般敘述了形成間隔物與輕摻雜源極/汲極區的製程。可以使用其他製程與順序。例如，可以利用較少的或額外的間隔物、可以利用不同的步驟順序(舉例而言：在形成閘極密封間隔物82之前，可以不對閘極密封間隔物80進行蝕刻，產生「L型」的閘極密封間隔物)、可以形成與移除間隔物及/或類似情況。此外，可以使用不同的結構與步驟來形成n型與p型裝置。例如，用於n型裝置的輕摻雜源極/汲極區域可以在形成閘極密封間隔物80之前形成，而用於p型裝置的輕摻雜源極/汲極區域可以在形成閘極密封間隔物80之後形成。
在第8A與8B圖中，在區域50A與區域50B中的奈米結構55形成複數個凹部84。如第8A圖所示，在區域50A的凹部84延伸穿過第一半導體層52B與52C以及第二半導體層54A-54C，暴露出第一半導體層52A。在區域50A，第一半導體層52A在凹部84的下方、第一半導體層52B與52C的下方以及第二半導體層54A-C的下方連續延伸。如第8B圖所示，在區域50B的凹部84延伸穿過第一半導體層52B與52C以及第二半導體層54B與54C，暴露出第二半導體層54A。在區域50B，第二半導體層54A在凹部84的下方、第一半導體層52B與52C的下方以及第二半導體層54B與54C的下方連續延伸。
凹部84可以藉由使用非等向性蝕刻製程，例如反應性離子蝕刻、中性束蝕刻或類似製程蝕刻奈米結構55而形成。在用於形成凹部84的蝕刻製程期間，閘極間隔物82、閘極密封間隔物80與遮罩78掩蓋部分的奈米結構55。可以使用一單一的蝕刻製程來蝕刻第一半導體層52B與52C以及第二半導體層54A-54C中的每一個。在其他實施例中，可以使用多個蝕刻製程來蝕刻多層堆疊物64的各層。可以使用定時蝕刻製程(timed etch processes)在對區域50A中的第二半導體層54A進行蝕刻之後與在對區域50B中的第一半導體層52B進行蝕刻之後，停止對凹部84的蝕刻。可以將區域50A中的凹部84蝕刻到約40 nm至約50 nm的深度，例如約45 nm，而可以將區域50B中的凹部84蝕刻到約30 nm至約40 nm的深度，例如約35 nm。上述蝕刻可以使用由例如三氟甲烷(CHF3 )、四氟甲烷(CF4 )、溴化氫(HBr)等製程氣體形成的電漿來進行。
在凹部84分別在區域50A與區域50B中具有不同深度的實施例中，可以在形成凹部84的蝕刻製程的期間使用光阻劑或其他遮罩(未單獨顯示)。在蝕刻區域50B的同時，可以在區域50A的上方形成一遮罩，例如光阻劑。然後，可以移除上述遮罩。後續，可以在蝕刻區域50A的同時，在區域50B的上方形成一遮罩，例如光阻劑。然後，可以移除上述遮罩。
在第9A與9B圖中，對由凹部84暴露的多層堆疊物64的層部分側壁進行蝕刻，以形成複數個側壁凹部86。可以使用等向性蝕刻製程，例如濕式蝕刻或類似製程，對上述側壁進行蝕刻。如第9A圖所示，可以在區域50A蝕刻第一半導體層52B與52C的側壁。如第9B圖所示，可以在區域50B蝕刻第二半導體層54B與54C的側壁。藉由使用光阻劑或其他遮罩(未單獨顯示)，可以在區域50A與區域50B中蝕刻不同的層。在對區域50B進行蝕刻的同時，可以在區域50A的上方形成一遮罩，例如光阻劑。然後，可以移除上述遮罩。後續，可以對蝕刻區域50A進行蝕刻的同時，在區域50B的上方形成一遮罩，例如光阻劑。然後，可以移除上述遮罩。
用於蝕刻第一半導體層52B與52C的蝕刻劑可以對第二半導體層54A-54C的材料具有選擇性，而用於蝕刻第二半導體層54B與54C的蝕刻劑可以對第一半導體層52A-52C的材料具有選擇性。在第一半導體層52A-52C包括第一半導體材料(舉例而言：SiGe或類似物)以及第二半導體層54A-54C包括第二半導體材料(舉例而言：Si、SiC或類似物)的一實施例中，可以使用氫氧化四甲基銨(tetramethylammonium hydroxide；TMAH)、氫氧化銨(NH4 OH)或類似物來蝕刻區域50A中的多層堆疊物64的每個側壁，並且可以使用稀釋的氫氧化銨—過氧化氫混合物(ammonium hydroxide-hydrogen peroxide mixture；APM)、硫酸—過氧化氫混合物(sulfuric acid-hydrogen peroxide mixture；SPM)或類似物來蝕刻區域50B中的多層堆疊物64的每個側壁。
在另外的實施例中，可以使用一乾蝕刻製程來蝕刻上述層。氟化氫、另一種氟基氣體(fluorine-based gas)或類似物可用於蝕刻區域50A中的多層堆疊物64的側壁，而氫(H2 )電漿、三氟甲烷(CHF3 )/氧(O2 )/氫(H2 )電漿、上述之組合或類似物可用於蝕刻區域50B中的多層堆疊物64的側壁。儘管在第9A與9B圖顯示第一半導體層52B與52C以及第二半導體層54B與54C具有與側壁凹部86相鄰的直線狀的側壁，但上述側壁可以是具有凹面、具有凸面或類似形狀。此外，第一半導體層52B與52C以及第二半導體層54B與54C中的每一個的側壁可以延伸到相鄰的通道層及/或犧牲層的側壁以外之處、從相鄰的通道層及/或犧牲層的側壁凹陷或與相鄰的通道層及/或犧牲層的側壁有共同端點(co-terminus)。
在第10A圖與10B中，在側壁凹部86形成內間隔物88。內間隔物88可藉由在第9A圖與9B所示的結構的上方沉積一內間隔物層來形成。上述內間隔層可以藉由例如化學氣相沉積、原子層沉積或類似製程等的一共形沉積製程來沉積。上述內間隔層可以包括例如氮化矽或氮氧化矽等的一材料，儘管可以利用任何合適的材料，如k值小於約3.5的低k(低介電常數)材料。
然後，可以對上述內間隔層進行蝕刻以形成內間隔層88。上述內間隔層可藉由一非等向性蝕刻製程，例如反應性離子蝕刻、中性束蝕刻或類似製程來進行蝕刻。可將內間隔層88用於防止後續蝕刻製程對後續形成的源極/汲極區(例如下文就第11A與11B圖討論的磊晶源極/汲極區90)造成的損傷。儘管將內間隔物88顯示為具有直線狀的側壁，但內間隔物88的側壁可以是具有凹面、具有凸面或類似形狀。此外，與凹部84相鄰的內間隔物88的側壁可以延伸到與位於內間隔物88相鄰且在內間隔物88的上方或下方的通道層及/或犧牲層的側壁以外之處、從與位於內間隔物88相鄰且在內間隔物88的上方或下方的通道層及/或犧牲層的側壁凹陷或和與位於內間隔物88相鄰且在內間隔物88的上方或下方的通道層及/或犧牲層的側壁有共同端點。
在第11A-11D圖中，在區域50A與區域50B的凹部84中形成磊晶源極/汲極區90，以在多層堆疊物64的上述通道層(舉例而言：第一半導體層52B與52C以及第二半導體層54B與54C)中施加應力，藉此改善效能。將磊晶源極/汲極區90形成在凹部84，使得每個虛設閘極76分別位於相鄰的磊晶源極/汲極區90對之間。在區域50A，第一半導體層52A在磊晶源極/汲極區90的下方以及磊晶源極/汲極區90與基底50之間連續延伸。在區域50B，第二半導體層54A在磊晶源極/汲極區90下方以及磊晶源極/汲極區90與基底50之間連續延伸。在一些實施例中，閘極間隔物82用於將磊晶源極/汲極區90與虛設閘極76隔開適當的橫向距離，以使磊晶源極/汲極區90不會與所獲得的奈米結構場效電晶體的後續形成的閘極短路。內間隔物88亦可用於將磊晶源極/汲極區90與虛設閘極76隔開，並避免在磊晶源極/汲極區90與所獲得的奈米結構場效電晶體的隨後形成的閘極之間發生短路。
在區域50A的磊晶源極/汲極區90可以藉由遮蔽區域50B來形成。然後，將磊晶源極/汲極區90磊晶成長在凹部84。磊晶源極/汲極區90可以包括任何可接受的材料。例如，若第二半導體層54B與54C是以上述第二半導體材料(舉例而言：Si、SiC或類似物)形成，則在區域50A的磊晶源極/汲極區90可以包括在第二半導體層54B與54C中施加拉伸應變的材料，例如矽、碳化矽、摻磷的碳化矽、磷化矽或類似物。磊晶源極/汲極區90可以具有從多層堆疊物64的各自表面凸起的表面，並且可以具有刻面(facets)。
在區域50B的磊晶源極/汲極區90可以藉由遮蔽區域50A而形成。然後，將磊晶源極/汲極區90磊晶成長在凹部84。磊晶源極/汲極區90可以包括任何可接受的材料。例如，若第一半導體層52B與52C是以上述第一半導體材料(舉例而言：SiGe或類似物)形成，則在區域50B的磊晶源極/汲極區90可以包括在第一半導體層52B與52C中施加壓縮應變的材料，例如矽鍺、摻硼的矽鍺、鍺、鍺錫(germanium tin)或類似物。在磊晶源極/汲極區90、第一半導體層52B與52C包括矽鍺的實施例中，磊晶源極/汲極區90的鍺濃度可以大於第一半導體層52B與52C的鍺濃度。磊晶源極/汲極區90還可以具有從多層堆疊物64的各自表面凸起的表面，並且可以具有刻面。
作為使用上述磊晶製程來形成區域50A與區域50B中的磊晶源極/汲極區90的結果，磊晶源極/汲極區90的上表面具有刻面，這些刻面向外側擴展至超出奈米結構55的側壁。在一些實施例中，如第11C圖所示，這些刻面導致同一奈米結構場效電晶體的相鄰磊晶源極/汲極區90合併。在其他實施例中，如第11D圖所示，在完成上述磊晶製程之後，相鄰的磊晶源極/汲極區90保持分離。在第11C與11D圖所示的實施例中，形成閘極間隔物82與閘極密封間隔物80，覆蓋延伸在高於淺溝槽隔離區68之處的奈米結構55的側壁的一部分，藉此阻止磊晶成長。在一些其他實施例中，可調整用於形成閘極間隔物82與閘極密封間隔物80的間隔物蝕刻，以移除間隔物材料，得以使磊晶成長的區域延伸到淺溝槽隔離區68的表面。
可以以摻雜物對磊晶源極/汲極區90及/或多層堆疊物64進行佈植以形成複數個源極/汲極區，類似於先前討論的用於形成輕摻雜源極/汲極區的製程，隨後進行退火。上述源極/汲極區可具有約1×1019 個原子/cm3 至約1×1021 個原子/cm3 的不純物濃度。上述源極/汲極區的n型及/或p型不純物可以是前文已討論的任何不純物。在一些實施例中，磊晶源極/汲極區90可以在成長的期間進行同步摻雜。
儘管以上描述已經討論了對繪示於第8A-11D圖的每個步驟使用單獨的遮罩，但可以對區域50A使用針對區域50A的單一的光阻劑或其他遮罩並對與區域50B使用針對區域50B的單一的光阻劑或其他遮罩，來執行不同的製程。例如，可以在區域50A的上方形成一遮罩，例如一光阻劑，同時對區域50B施行繪示於第8B圖、第9B圖、第10B圖與第11B圖的製程。然後，可以移除上述遮罩。後續，可以在區域50B的上方形成一遮罩，例如一光阻劑，同時對區域50A施行繪示於第8A圖、第9A圖、第10A圖與第11A圖的製程。然後，可以移除上述遮罩。
在第12A圖-12C中，在繪示於第11A圖、第11B圖與第6A圖的結構的上方沉積第一層間介電質(interlayer dielectric；ILD)92(第7-11B圖的製程未改變繪示於第6A圖的剖面)。第一層間介電質92可以以一介電材料形成，並且可以藉由任何合適的方法沉積，例如化學氣相沉積、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition；PECVD)或流動式化學氣相沉積。上述介電材料可以包括磷矽酸鹽玻璃(phospho-silicate glass；PSG)、硼矽酸鹽玻璃(boro-silicate glass；BSG)、摻硼的磷矽酸鹽玻璃(boron-doped phospho-silicate glass；BPSG)、未摻雜的矽酸鹽玻璃(undoped silicate glass；USG)或類似材料。可以使用藉由任何可接受的製程形成的其他絕緣材料。在一些實施例中，在第一層間介電質92與磊晶源極/汲極區90、遮罩78以及閘極間隔物82之間設置一接觸蝕刻停止層(contact etch stop layer；CESL)91。接觸蝕刻停止層91可以包括一介電材料，例如，氮化矽、氧化矽化氮氧化矽或類似材料，其具有的蝕刻速率與上覆的第一層間介電質92的材料的蝕刻速率不同。
在第13A-13C圖中，可以施行一平坦化製程，例如化學機械研磨，以使第一層間介電質92的頂表面與虛設閘極76或遮罩78的頂表面齊平。上述平坦化製程還可以移除虛設閘極76上的遮罩78，以及移除閘極密封間隔物80與閘極間隔物82之沿著遮罩78的側壁的部分。在上述平坦化製程之後，虛設閘極76、閘極密封間隔物80、閘極間隔物82與第一層間介電質92的頂表面齊平。因此，經由第一層間介電質92而暴露出虛設閘極76的頂表面。在一些實施例中，可以留下遮罩78，在這樣的情況下，上述平坦化製程使第一層間介電質92的頂表面與遮罩78、閘極密封間隔物80及閘極間隔物82的頂表面齊平。
在第14A-14C圖中，在一或多個蝕刻步驟中移除虛設閘極76與遮罩78（如果存在），而形成複數個凹部94。凹部94中的虛設介電層70的部分亦可以被移除。在一些實施例中，僅移除虛設閘極76，而虛設介電層70仍然存在並被凹部94暴露。在一些實施例中，將虛設介電層70從一晶粒(die)的一第一區域(舉例而言：一核心邏輯區域)中的凹部94移除，並保留在上述晶粒的一第二區域(舉例而言：一輸入/輸出區域)中的凹部94。在一些實施例中，藉由一非等向性的乾蝕刻製程來移除虛設閘極76。例如，上述蝕刻製程可以包括使用反應氣體的一乾蝕刻製程，上述反應氣體選擇性地蝕刻虛設閘極76而不蝕刻第一層間介電質92、閘極密封間隔物80或閘極間隔物82。每個凹部94暴露及/或覆蓋多層堆疊物64。部分的多層堆疊物64是設置於磊晶源極/汲極區90的相鄰對之間。在移除的過程中，當對虛設閘極76進行蝕刻時，虛設介電層70可用來作為蝕刻停止層。然後，可以在移除虛設閘極76之後選擇性地(optionally)移除虛設介電層70。
在第15A-15C圖中，將第一半導體層52A-52C從區域50A移除，將第二半導體層54A-54C從區域50B移除，而使凹部94延伸。可以藉由光阻劑或其他遮罩(未單獨顯示)，將多層堆疊物64的特定層從區域50A與區域50B移除。可以在區域50A的上方形成一遮罩，例如一光阻劑，同時從區域50B移除第二半導體層54A-54C。然後，可以移除上述遮罩。後續，可以在區域50B的上方形成一遮罩，例如一光阻劑，同時從區域50A移除第一半導體層52A-52C。然後，可以移除上述遮罩。
可以藉由例如濕蝕刻或類似製程等的等向性蝕刻製程，將多層堆疊物64的層移除。用於移除第一半導體層52A-52C的蝕刻劑可以選擇性地移除第二半導體層54A-54C的材料，而用於蝕刻第二半導體層54A-54C的蝕刻劑可以選擇性地移除第一半導體層52A-52C的材料。在第一半導體層52A-52C包括上述第一半導體材料(舉例而言：SiGe或類似物)且第二半導體層54A-54C包括上述第二半導體材料(舉例而言：Si、SiC或類似物)的一實施例中，可以使用氫氧化四甲基銨(tetramethylammonium hydroxide；TMAH)、氫氧化銨(NH4 OH)或類似物來移除區域50A中的多層堆疊物64的層，且可使用稀釋的氫氧化銨—過氧化氫混合物(ammonium hydroxide-hydrogen peroxide mixture；APM)、硫酸—過氧化氫混合物(sulfuric acid-hydrogen peroxide mixture；SPM)或類似物來移除區域50B中的多層堆疊物64的層。可以使用電漿，例如由氫氣(H2 )或類似物形成的電漿來移除第一半導體層52A-52C。可以使用包括氫氟酸(HF)與過氧化氫(H2 O2 )的溶液、包括氫氟酸、硝酸(HNO3 )與水(H2 O)的溶液或類似物來移除第二半導體層54A-54C。
在第16A-16D圖中，形成複數個閘極介電層96與複數個閘極電極98而用於替換閘極。將閘極介電層96共形地沉積在凹部94，例如沉積在第一半導體層52A的頂表面上與側壁上以及第一半導體層52B與52C及第二半導體層54A-54C的頂表面上、側壁上與底表面上。亦可以在基底50的頂表面上、第一層間介電質92上、接觸蝕刻停止層91上與淺溝槽隔離區68上，且在閘極密封間隔物80的頂表面上、側壁上與底表面上，並在閘極間隔物82的頂表面上及底上面上以及在內間隔物88的側壁上，沉積閘極介電層96。根據一些實施例，閘極介電層96包括氧化矽、氮化矽或上述的多層結構。在一些實施例中，閘極介電層96包括一高介電常數介電材料，而在這些實施例中，閘極介電層96的k值可以大於約7.0，並且可以包括金屬氧化物或鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛及其組合的矽酸鹽。閘極介電層96的形成方法可以包括分子束沉積(molecular-beam deposition；MBD)、原子層沉積、電漿輔助化學氣相沉積等。
閘極介電層96可具有約2 nm至約3 nm的厚度，例如約2.5 nm。閘極介電層96的厚度可以大於第一半導體層52A的厚度的一半，也可以大於第二半導體層54A的厚度的一半。具體而言，沉積在藉由移除第一半導體層52B與52C所形成的凹部中的閘極介電層96的部分以及區域50A中的虛設閘極76的厚度，可以大於第一半導體層52A的厚度的一半；而沉積在藉由移除第二半導體層54B與54C所形成的凹部中的閘極介電層96的部分以及區域50B中的虛設閘極76的厚度，可以大於第二半導體層54A的厚度的一半。因為閘極介電層96的厚度大於第一半導體層52A與第二半導體層54A的厚度的一半，所以閘極介電層96填充藉由從區域50B移除第一半導體層52A而留下的凹部94的部分以及填充藉由從區域50A移除第二半導體層54A而留下的凹部94的部分。如第16B-16D圖所示，閘極介電層96可以在磊晶源極/汲極區90的下方延伸，也就是在區域50A與區域50B中的基底50與磊晶源極/汲極區90之間延伸。磊晶源極/汲極區90藉由閘極介電層96而與基底50絕緣。因此，在基底50與每個磊晶源極/汲極區90之間形成閘極介電層96，可以防止從磊晶源極/汲極區90到基底50的漏電流，防止閂鎖效應並提高效能。閘極介電層96之在基底50與第二半導體層54A/區域50A中的磊晶源極/汲極區90之間延伸的部分以及閘極介電層96之在基底50與第一半導體層52B/區域50B中的磊晶源極/汲極區90之間延伸的部分，可稱為隔離層。
將閘極電極98分別沉積在閘極介電層96上，並填充凹部94的剩餘部分。閘極電極98可以包括一含金屬材料，例如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、上述之組合或上述的多層結構。例如，儘管在第14B圖中顯示一單層的閘極電極98，但閘極電極98可以包括任意數量的襯墊層、任意數量的功函數調整層與一填充材料。在閘極電極98由多於一層形成的複數層中，取決於構成閘極電極的層的厚度與凹部94的間距(spacing)，可以將構成閘極電極98的部分或全部的層形成在凹部94之在第二半導體層54A與第二半導體層54B之間延伸的部分、在第二半導體層54B與第二半導體層54C之間延伸的部分以及在第一半導體層52B與第一半導體層52C之間延伸的部分。閘極電極98可以藉由原子層沉積、化學氣相沉積、物理氣相沉積、類似方法或上述之組合來形成。在一些實施例中，閘極電極98可以藉由原子層沉積後接物理氣相沉積來形成。
在凹部94的填充之後，可以施行例如化學機械研磨等的一平坦化製程，以移除閘極介電層96的多餘部分與閘極電極98的材料的多餘部分，這些多餘部分是在第一層間介電質92的頂表面的上方。閘極電極98的材料的留下來的部分與閘極介電層96的留下來的部分因此而形成所形成的奈米結構場效電晶體的替換閘極。可將閘極電極98與閘極介電層96一起稱為「閘極堆疊物」。上述閘極與上述閘極堆疊物可以圍繞第一半導體層52B與52C以及第二半導體層54B與54C中的每一個。
區域50A與區域50B中的閘極介電層96的形成可以同時發生，使得每個區域中的閘極介電層96是以相同的材料形成，並且閘極電極98的形成可以同時發生，使得每個區域中的閘極電極98是以相同的材料形成。在一些實施例中，可以藉由不同的製程來形成每個區域中的閘極介電層96，使得複數個閘極介電層96可以是不同的材料，及/或可以藉由不同的製程來形成每個區域中的閘極電極98，使得複數個閘極電極98可以是不同的材料。當使用不同的製程時，可以使用各種遮蔽步驟來遮蔽與暴露適當的區域。
在第16D圖中，將一區域50A繪示在一區域50B的旁邊，以繪示區域50A與區域50B之間的比較。區域50A可以與區域50B物理地分開(如由分界線53所示)。由於在區域50A與區域50B中的通道區使用不同的半導體層，上述閘極堆疊物可能具有不同的高度，磊晶源極/汲極區90可能延伸到不同的深度，且可以在區域50A與區域50B將上述通道區(舉例而言：區域50B中的第一半導體層52B與52C以及區域50A中的第二半導體層54B與54C)的頂表面設置於不同高度。例如，如第16D圖所示，區域50B中的閘極堆疊物的高度H2 可以大於區域50A中的閘極堆疊物的高度H1 。區域50B中的閘極堆疊物與區域50A中的閘極堆疊物之間的高度差可以為約8 nm至約10 nm，例如約9 nm。區域50A中的通道區的頂表面可以設在高於區域50B中的通道區之處。例如，區域50A中的第二半導體層54C的一頂表面可以設在高於區域50B中的第一半導體層52C的一頂表面之處，高出的距離D1 為約8 nm至約10 nm，例如約9 nm。區域50B中的磊晶源極/汲極區90的底表面可以設在高於區域50A中的磊晶源極/汲極區90的底表面之處。例如，區域50B中的磊晶源極/汲極區90的底表面可以設在高於區域50A中的磊晶源極/汲極區90的底面之處，高出的距離D2 為約4 nm至約6 nm，例如約5 nm。
在第17A-17C圖中，將一第二層間介電質100沉積在第一層間介電質92的上方。在一些實施例中，第二層間介電質100是藉由一流動式化學氣相沉積方法所形成的一可流動薄膜。在一些實施例中，第二層間介電質100是以例如矽酸鹽玻璃、硼矽酸鹽玻璃、摻硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃或類似材料等的一介電材料所形成，並且可以藉由任何合適的方法，例如化學氣相沉積、電漿輔助化學氣相沉積或類似的方法所沉積。根據一些實施例，在形成第二層間介電質100之前，上述閘極堆疊物(包括閘極介電層96與相應的上覆的閘極電極98)是凹陷的，而在閘極堆疊的正上方與在閘極密封間隔物80的相對的部分之間形成一凹部。將包括一層或多層介電材料(例如氮化矽、氮氧化矽或類似材料)的一閘極遮罩102填充在上述凹部，後接一平坦化製程以移除延伸在第一層間介電質92的上方之上述介電材料的多餘部分。後續形成的複數個閘極接觸件(例如下文就第18A圖-18C討論的閘極接觸件104)穿透閘極遮罩102以接觸凹陷的閘極電極98的頂表面。
在第18A-18C圖中，形成複數個閘極接觸件104與複數個源極/汲極接觸件106。將用於源極/汲極接觸件106的複數個開口形成為穿透第二層間介電質100與第一層間介電質92，並將用於閘極接觸件104的複數個開口形成為穿透第二層間介電質100與閘極遮罩102。這些開口可以使用可接受的微影與蝕刻技術來形成。在上述開口形成一襯墊以及一導體材料，上述襯墊例如一擴散阻障層、一黏附層或類似物。上述襯墊可以包括鈦、氮化鈦、鉭、氮化鉭或類似物。上述導體材料可以是銅、銅合金、銀、金、鎢、鈷、鋁、鎳或類似材料。可以施行一平坦化製程，例如化學機械研磨，以從第二層間介電質100的一表面移除多餘的材料。留下來的襯墊與導體材料在上述開口形成源極/汲極接觸件106與閘極接觸件104。可以施行一退火製程，以在源極/汲極接觸件106與每個磊晶源極/汲極區90之間的界面處形成矽化物。源極/汲極接觸件106與磊晶源極/汲極區90是物理性且電性耦合，閘極接觸件104與閘極電極98是物理性且電性耦合。源極/汲極接觸件106與閘極接觸件104可以在不同的製程中形成，或者可以在相同的製程中形成。儘管圖示為形成在相同的剖面，但應當理解的是，源極/汲極接觸件106與閘極接觸件104中的每一個可以形成在不同的剖面，這可以避免接觸件的短路。
如上所述，使用閘極介電層96替換第一半導體層52A與第二半導體層54A的情況是將磊晶源極/汲極區90與基底50絕緣。這避免從磊晶源極/汲極區90到基底50的漏電流，而避免閂鎖效應並提升效能。
根據一實施例，一種半導體裝置包括：一半導體基底；一閘極堆疊物，在上述半導體基底的上方，上述閘極堆疊物包括一閘極電極與一閘極介電質；一第一磊晶源極/汲極區，相鄰於上述閘極堆疊物；以及一高介電常數(high-k)介電質，在上述半導體基底與上述第一磊晶源極/汲極區之間延伸，上述高介電常數介電質接觸上述第一磊晶源極/汲極區，其中上述閘極介電質與上述高介電常數介電質包括相同的材料。在一實施例中，上述半導體裝置更包括：一第二磊晶源極/汲極區，相鄰於該閘極堆疊物且在上述第一磊晶源極/汲極區的對向，其中上述高介電常數介電質的延伸，是連續地從上述第一磊晶源極/汲極區的下方、上述閘極堆疊物之下而至上述第二磊晶源極/汲極區的下方。在一實施例中，上述半導體裝置更包括：一第一半導體層，在上述高介電常數介電質與上述閘極堆疊物之間；以及複數個通道區，在上述第一半導體層的上方與上述高介電常數介電質的上方，其中上述複數個通道區包括如上述第一半導體層的相同材料，其中上述閘極堆疊物在上述第一半導體層與上述複數個通道區之間延伸，且在上述複數個通道區中的通道區之間延伸。在一實施例中，上述第一半導體層與上述複數個通道區包括矽，且其中上述第一磊晶源極/汲極區包括磷化矽。在一實施例中，上述半導體裝置更包括：一第一半導體層，在上述半導體基底與上述高介電常數介電質之間，上述第一半導體層包括一材料，其不同於上述半導體基底的材料。在一實施例中，上述半導體裝置更包括：複數個通道區，在上述第一半導體層的上方與上述高介電常數介電質的上方，其中上述複數個通道區包括如上述第一半導體層的相同材料，其中上述閘極堆疊物在上述複數個通道區中的通道區之間延伸。在一實施例中，上述第一半導體層與上述複數個通道區包括矽鍺(silicon germanium)，且其中上述第一磊晶源極/汲極區包括矽鍺。在一實施例中，上述高介電常數介電質的厚度為2 nm至3 nm。
根據另一實施例，一種半導體裝置的形成方法包括：在一半導體基底的上方沉積一多層堆疊物，上述多層堆疊物包括多層交替排列的一第一半導體材料與一第二半導體材料；在上述多層堆疊物形成一磊晶源極/汲極區，上述磊晶源極/汲極區延伸而至少部分穿過上述多層堆疊物；移除上述多層堆疊物的一第一層與一第二層，以分別形成一第一凹部與一第二凹部；在上述第一凹部與上述第二凹部沉積一閘極介電層，上述閘極介電層填充上述第一凹部以形成一第一隔離層，上述第一隔離層在上述磊晶源極/汲極區與上述半導體基底之間延伸；以及在上述第二凹部沉積一閘極電極材料。在一實施例中，形成上述磊晶源極/汲極區包括：蝕刻上述多層堆疊物以形成一第一開口，上述第一開口暴露上述第一層的一頂表面的一第一開口；以及磊晶成長上述磊晶源極/汲極區，而使上述磊晶源極/汲極區填充上述第一開口。在一實施例中，將上述第一層沉積為4 nm至6 nm的厚度，將上述第二層沉積為8 nm至10 nm的厚度。在一實施例中，沉積上述多層堆疊物包括：在上述第二層與上述第一層的上方沉積一第三層，其中沉積上述閘極介電層包括在上述多層堆疊物的上述第三層的四個表面上沉積上述閘極介電層。在一實施例中，移除上述多層堆疊物的上述第一層與上述第二層包括一選擇性的蝕刻製程，其蝕刻上述第一層與上述第二層的速率快於上述選擇性的蝕刻製程蝕刻上述第三層的速率。
根據又另一實施例，一種半導體裝置的形成方法包括：在一半導體基底的上方沉積一多層堆疊物，上述多層堆疊物包括在上述半導體基底的上方的一第一犧牲層、在上述第一犧牲層的上方的一第二犧牲層、在上述第二犧牲層的上方的一第一通道層及在上述第一通道層的上方的一第二通道層；形成一第一源極/汲極區，其延伸穿過上述第二通道層、上述第一通道層及上述第二犧牲層而至上述第一犧牲層的一頂表面；使用一第一蝕刻製程，從上述半導體裝置的一第一區蝕刻上述第一通道層與上述第一犧牲層；以及在藉由蝕刻上述第一通道層與上述第一犧牲層而形成的複數個凹部沉積一第一介電層，上述第一介電層填充藉由蝕刻上述第一犧牲層而形成的上述複數個凹部。在一實施例中，上述方法更包括：形成一第二源極/汲極區，其延伸穿過上述第二通道層及上述第一通道層而至上述第二犧牲層的一頂表面；使用一第二蝕刻製程，從上述半導體裝置的一第二區蝕刻上述第二通道層與上述第二犧牲層；以及在藉由蝕刻上述第二通道層與上述第二犧牲層而形成的複數個凹部沉積一第二介電層，上述第二介電層填充藉由蝕刻上述第二犧牲層而形成的上述複數個凹部。在一實施例中，上述第一區為一N型金屬—氧化物—半導體(NMOS)區，上述第二區為一P型金屬—氧化物—半導體(PMOS)區，上述第一犧牲層與上述第一通道層包括矽鍺(silicon germanium)，上述第二犧牲層與上述第二通道層包括矽。在一實施例中，上述方法更包括：蝕刻上述第二通道層在上述第一區的一側壁以形成一第一凹部，其中形成上述第一源極/汲極區包括蝕刻上述第二通道層、上述第一通道層及上述第二犧牲層以形成一第二凹部，其中經由上述第二凹部而蝕刻上述第二通道層的上述側壁；以及蝕刻上述第一通道層在上述第二區的一側壁以形成一第三凹部，其中形成上述第二源極/汲極區包括蝕刻上述第二通道層及上述第一通道層以形成一第四凹部，其中經由上述第四凹部而蝕刻上述第一通道層的上述側壁。在一實施例中，上述方法更包括：在上述第一凹部、上述第二凹部、上述第三凹部及上述第四凹部共形地(conformally)沉積一內間隔物層，上述內間隔物層填充上述第一凹部與上述第三凹部；以及蝕刻上述內間隔物層以移除上述內間隔物層在上述第一凹部之外及上述第三凹部之外的部分。在一實施例中，將上述第一介電層形成在藉由蝕刻上述第一通道層而形成的上述凹部至其厚度大於上述第一犧牲層的一半厚度，且將上述第二介電層形成在藉由蝕刻上述第二通道層而形成的上述凹部至其厚度大於上述第二犧牲層的一半厚度。
前述內文概述了許多實施例的特徵，使所屬技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。所屬技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。所屬技術領域中具有通常知識者也應了解這些均等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
50:基底 50A,50B:區域 51:抗擊穿區 52A,52B,52C:第一半導體層 53:分界線 54A,54B,54C:第二半導體層 55:奈米結構 68:淺溝槽隔離區 70:虛設介電層 72:虛設閘極層 74:遮罩層 76:虛設閘極 78:遮罩 80:閘極密封間隔物 82:閘極間隔物 84:凹部 86:側壁凹部 88:內間隔物 90:磊晶源極/汲極區 91:接觸蝕刻停止層 92:第一層間介電質 94:凹部 96:閘極介電層 98:閘極電極 100:第二層間介電質 102:閘極遮罩 104:閘極接觸物 106:源極/汲極接觸件 A-A’,B-B’,C-C’,D-D’:參考剖面 D1 ,D2 :距離 H1 ,H2 :高度
根據以下的詳細說明並配合所附圖式而最有效地瞭解本發明實施例的面向。應注意的是，根據本產業的標準作業，圖式並未必按照比例繪製各種部件。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1圖是根據一些實施例之一奈米結構場效電晶體(nanostructure field-effect transistor；NSFET)的一例之三維視圖； 第2圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第3圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第4圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第5圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第6A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第6B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第7圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第8A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第8B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第9A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第9B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第10A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第10B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第11A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第11B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第11C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第11D圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第12A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第12B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第12C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第13A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第13B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第13C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第14A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第14B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第14C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第15A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第15B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第15C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第16A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第16B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第16C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第16D圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第17A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第17B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第17C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第18A圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第18B圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖； 第18C圖是根據一些實施例之製造奈米結構場效電晶體的中間階段之剖面圖。
50:基底
50A,50B:區域
52A,52B,52C:第一半導體層
53:分界線
54A,54B,54C:第二半導體層
80:閘極密封間隔物
82:閘極間隔物
88:內間隔物
90:磊晶源極/汲極區
91:接觸蝕刻停止層
92:第一層間介電質
96:閘極介電層
98:閘極電極
D1 ,D2 :距離
H1 ,H2 :高度

Claims (1)

  1. 一種半導體裝置，包括： 一半導體基底； 一閘極堆疊物，在該半導體基底的上方，該閘極堆疊物包括一閘極電極與一閘極介電質； 一第一磊晶源極/汲極區，相鄰於該閘極堆疊物；以及 一高介電常數介電質，在該半導體基底與該第一磊晶源極/汲極區之間延伸，該高介電常數介電質接觸該第一磊晶源極/汲極區，其中該閘極介電質與該高介電常數介電質包括相同的材料。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI837838B (zh) * 2021-10-12 2024-04-01 台灣積體電路製造股份有限公司 半導體裝置及其形成方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11664420B2 (en) 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR20210124731A (ko) * 2020-04-07 2021-10-15 삼성전자주식회사 게이트 스페이서를 갖는 반도체 소자들

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9006829B2 (en) 2012-08-24 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Aligned gate-all-around structure
US9209247B2 (en) 2013-05-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned wrapped-around structure
US9136332B2 (en) 2013-12-10 2015-09-15 Taiwan Semiconductor Manufacturing Company Limited Method for forming a nanowire field effect transistor device having a replacement gate
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9412817B2 (en) 2014-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
US9536738B2 (en) 2015-02-13 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) devices and methods of manufacturing the same
US9613871B2 (en) * 2015-07-16 2017-04-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US9502265B1 (en) 2015-11-04 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) transistors and methods of forming the same
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
KR102409962B1 (ko) * 2015-12-16 2022-06-16 삼성전자주식회사 반도체 장치
KR102476143B1 (ko) * 2016-02-26 2022-12-12 삼성전자주식회사 반도체 장치
US10032867B1 (en) * 2017-03-07 2018-07-24 International Business Machines Corporation Forming bottom isolation layer for nanosheet technology
US10090410B1 (en) * 2017-03-17 2018-10-02 International Business Machines Corporation Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate
US10008583B1 (en) * 2017-05-08 2018-06-26 Samsung Electronics Co., Ltd. Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same
KR102277610B1 (ko) * 2017-06-29 2021-07-14 삼성전자주식회사 반도체 장치의 제조 방법
US10468311B2 (en) * 2017-10-06 2019-11-05 International Business Machines Corporation Nanosheet substrate isolated source/drain epitaxy by nitrogen implantation
US20190221639A1 (en) * 2018-01-12 2019-07-18 United Microelectronics Corp. Nanosheet device and method for fabricating the same
US11062959B2 (en) * 2018-03-19 2021-07-13 International Business Machines Corporation Inner spacer and junction formation for integrating extended-gate and standard-gate nanosheet transistors
US10818792B2 (en) * 2018-08-21 2020-10-27 Globalfoundries Inc. Nanosheet field-effect transistors formed with sacrificial spacers
KR102537527B1 (ko) * 2018-09-10 2023-05-26 삼성전자 주식회사 집적회로 소자
KR102509307B1 (ko) * 2018-09-19 2023-03-10 삼성전자주식회사 반도체 장치
US11189694B2 (en) * 2018-10-29 2021-11-30 Mediatek Inc. Semiconductor devices and methods of forming the same
US11830933B2 (en) * 2019-01-04 2023-11-28 Intel Corporation Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach
US10916627B2 (en) * 2019-03-22 2021-02-09 International Business Machines Corporation Nanosheet transistor with fully isolated source and drain regions and spacer pinch off
US10998234B2 (en) * 2019-05-14 2021-05-04 International Business Machines Corporation Nanosheet bottom isolation and source or drain epitaxial growth
US11145765B2 (en) * 2019-09-26 2021-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around structure with self substrate isolation and methods of forming the same
US11404587B2 (en) * 2019-10-30 2022-08-02 Mediatek Inc. Semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI837838B (zh) * 2021-10-12 2024-04-01 台灣積體電路製造股份有限公司 半導體裝置及其形成方法

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