CN112136209A - 集成转接件的第一元件、互联结构及其制备方法 - Google Patents

集成转接件的第一元件、互联结构及其制备方法 Download PDF

Info

Publication number
CN112136209A
CN112136209A CN201980000583.9A CN201980000583A CN112136209A CN 112136209 A CN112136209 A CN 112136209A CN 201980000583 A CN201980000583 A CN 201980000583A CN 112136209 A CN112136209 A CN 112136209A
Authority
CN
China
Prior art keywords
conductive
electrical interface
component
piece
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201980000583.9A
Other languages
English (en)
Inventor
王红超
沈健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
Original Assignee
Shenzhen Goodix Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Publication of CN112136209A publication Critical patent/CN112136209A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

本申请部分实施例提供了一种集成转接件的第一元件、互联结构及其制备方法。第一元件201的表面具有第一电气接口204，转接件包括绝缘本体202和第一导电件209，绝缘本体直接在第一元件的表面上制作形成，转接件的第一表面与第一元件的表面贴合且转接件的第一表面和第二表面之间贯穿有第一通孔208；第一通孔内形成有第一导电件209，且第一导电件的第一端与第一电气接口连接；第一导电件的第二端用于供第二电气接口205压焊连接。本实施例可以在实现第一元件和第二元件电气互联的同时，简化互联结构的制备工艺。

Description

PCT国内申请，说明书已公开。

Claims (23)

  1. PCT国内申请，权利要求书已公开。
CN201980000583.9A 2019-04-24 2019-04-24 集成转接件的第一元件、互联结构及其制备方法 Pending CN112136209A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/084081 WO2020215248A1 (zh) 2019-04-24 2019-04-24 集成转接件的第一元件、互联结构及其制备方法

Publications (1)

Publication Number Publication Date
CN112136209A true CN112136209A (zh) 2020-12-25

Family

ID=72940678

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980000583.9A Pending CN112136209A (zh) 2019-04-24 2019-04-24 集成转接件的第一元件、互联结构及其制备方法

Country Status (2)

Country Link
CN (1) CN112136209A (zh)
WO (1) WO2020215248A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023193505A1 (zh) * 2022-04-08 2023-10-12 华为技术有限公司 互联组件和通信模块

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140815A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-d devices using encapsulant for structural support
US20110044015A1 (en) * 2009-08-20 2011-02-24 Fujitsu Limited Multichip module and method for manufacturing the same
CN103579052A (zh) * 2012-08-01 2014-02-12 马维尔以色列(M.I.S.L.)有限公司 集成电路插入器及其制造方法
CN103887290A (zh) * 2012-12-21 2014-06-25 阿尔特拉公司 具有接合中介层的集成电路器件
US20150115405A1 (en) * 2013-10-31 2015-04-30 Qualcomm Incorporated Wireless interconnects in an interposer
CN105161432A (zh) * 2015-09-17 2015-12-16 中芯长电半导体（江阴）有限公司 一种芯片封装方法
CN106206409A (zh) * 2015-05-08 2016-12-07 华邦电子股份有限公司 堆叠电子装置及其制造方法
CN107846790A (zh) * 2016-09-19 2018-03-27 苏州纳格光电科技有限公司 多层柔性电路板的制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8411459B2 (en) * 2010-06-10 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd Interposer-on-glass package structures
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140815A1 (en) * 2008-12-10 2010-06-10 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-d devices using encapsulant for structural support
US20110044015A1 (en) * 2009-08-20 2011-02-24 Fujitsu Limited Multichip module and method for manufacturing the same
CN103579052A (zh) * 2012-08-01 2014-02-12 马维尔以色列(M.I.S.L.)有限公司 集成电路插入器及其制造方法
CN103887290A (zh) * 2012-12-21 2014-06-25 阿尔特拉公司 具有接合中介层的集成电路器件
US20150115405A1 (en) * 2013-10-31 2015-04-30 Qualcomm Incorporated Wireless interconnects in an interposer
CN106206409A (zh) * 2015-05-08 2016-12-07 华邦电子股份有限公司 堆叠电子装置及其制造方法
CN105161432A (zh) * 2015-09-17 2015-12-16 中芯长电半导体（江阴）有限公司 一种芯片封装方法
CN107846790A (zh) * 2016-09-19 2018-03-27 苏州纳格光电科技有限公司 多层柔性电路板的制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023193505A1 (zh) * 2022-04-08 2023-10-12 华为技术有限公司 互联组件和通信模块

Also Published As

Publication number Publication date
WO2020215248A1 (zh) 2020-10-29

Similar Documents

Publication Publication Date Title
US6469260B2 (en) Wiring boards, semiconductor devices and their production processes
US10460958B2 (en) Method of manufacturing embedded packaging with preformed vias
US7185426B1 (en) Method of manufacturing a semiconductor package
US8399992B2 (en) Package-on-package type semiconductor package
US6506633B1 (en) Method of fabricating a multi-chip module package
CN116169110A (zh) 一种芯片及封装方法
EP2234158A1 (en) A three-dimensional electronics package
CN108598061B (zh) 一种陶瓷转接板结构及其制造方法
JP2009506572A (ja) 相互接続構造を含むマイクロフィーチャ組立品およびそのような相互接続構造を形成するための方法
CN104505382A (zh) 一种圆片级扇出PoP封装结构及其制造方法
CN110335859B (zh) 一种基于tsv的多芯片的封装结构及其制备方法
JP2016505222A (ja) ワイヤボンドビアを有するマイクロ電子パッケージ、その製造方法、およびそのための補強層
KR20100133303A (ko) 반도체 장치 및 그 제조 방법
US20090008766A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US20090111213A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US20040124516A1 (en) Circuit device, circuit module, and method for manufacturing circuit device
US7745260B2 (en) Method of forming semiconductor package
CN112136209A (zh) 集成转接件的第一元件、互联结构及其制备方法
KR100843705B1 (ko) 금속 범프를 갖는 반도체 칩 패키지 및 그 제조방법
CN110299328B (zh) 一种堆叠封装器件及其封装方法
CN113990763A (zh) 一种基于电铸技术的芯片封装结构及其封装方法
CN115706017A (zh) 一种封装机构及其制备方法
US10290612B1 (en) Systems and methods for flash stacking
CN106129022A (zh) 双向集成芯片重布线埋入式pop封装结构及其制作方法
CN102097329B (zh) 封装基板的嵌入式导通结构及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination