CN112117241A - 半导体封装方法及其结构 - Google Patents

半导体封装方法及其结构 Download PDF

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CN112117241A
CN112117241A CN201910535814.8A CN201910535814A CN112117241A CN 112117241 A CN112117241 A CN 112117241A CN 201910535814 A CN201910535814 A CN 201910535814A CN 112117241 A CN112117241 A CN 112117241A
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李文显
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Suzhou Zhenkun Technology Co ltd
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Abstract

本发明公开了一种半导体封装方法及其结构。所述半导体封装结构包括导线架，具有多个引脚，引脚具有承放导线，其相邻对称设置的承放导线之间形成一间隔区，承放导线底部形成内凹部；芯片，放置于承放导线上且遮蔽间隔区；引线，电性连接芯片与引脚；封胶体，包覆芯片、承放导线、引线且让引脚部份露出。本发明是于芯片与承放导线接触区域设有黏胶体，黏胶体固化后会分布于间隔区及内凹部内，藉此提升承放导线的支撑力，防止承放导线在打线作业时下陷变形。

Description

半导体封装方法及其结构
技术领域
本发明属于一种半导体封装方法及其结构的技术领域，尤其涉及一种当芯片黏放于导线架且能提升结构强度的设计。
背景技术
在半导体封装结构中，导线架因具有低材料成本与高可靠度而被长期使用。导线架依承载芯片的部位不同，导线架又可区分为使用芯片座的传统导线架、芯片上引线(lead-on-chip，LOC)之导线架与引脚上芯片(chip-on-lead,COL)的导线架。其中，芯片上引线(LOC)与引脚上芯片(COL)的差异在于：芯片上引线是使导线架的引脚贴附至芯片的主动面，引脚上芯片是使芯片的背面贴附至导线架的引脚。
如图1所示，为引脚上芯片(COL)封装结构的示意图。导线架1具有多个引脚11，引脚11具有承放导线111。芯片12是利用芯片黏贴薄膜(Die Aattach Film,DAF)13固定于承放导线111上。在打线作业的加压过程中，容易下压承放导线111造成变形，使得芯片12无法黏着于承放导线111上，导致承载力变差，在后续封胶作业中容易受到模流影响而使芯片12偏移。
发明内容
为解决上述问题，本发明的主要目的是提供一种半导体芯片封装方法及其结构，主要于芯片黏着于导线架时，让部份黏胶体下陷，且在固化后形成倒钩状结构体，藉此提升导线架的支撑强度，防止承放导线下陷变形。
为实现前述目的，本发明采用了如下技术方案：
本发明为一种半导体封装结构，包括：导线架，具有多个引脚，引脚具有承放导线，相邻两个承放导线之间形成间隔区，承放导线于相接间隔区的底部形成内凹部；芯片，放置于承放导线上且遮蔽间隔区；引线，电性连接芯片与引脚；封胶体，包覆芯片、承放导线、引线且让引脚部份露出，芯片与承放导线接触区域设有黏胶体，且黏胶体分布于间隔区及内凹部内。
再者，本发明为一种半导体封装方法，步骤包括：涂布黏胶体于晶圆；贴附胶膜于黏胶体上；切割晶圆形成多个芯片，芯片黏附着黏胶体；自胶膜上取下黏附着黏胶体的芯片；将芯片以黏胶体放置于导线架的对称设置的承放导线上，黏胶体填满承放导线之间的间隔区内，且分布于承放导线底部的内凹部内；执行打线作业，使引线两端分别电性连接芯片及引脚；由封胶体塑封芯片、承放导线、引线且让引脚部份露出。
作为较佳优选实施方案之一，所述导线架以半蚀刻方式于承放导线底部形成内凹区。
作为较佳优选实施方案之一，所述间隔区的纵向尺寸是由上而下渐增。
作为较佳优选实施方案之一，所述承放导线对应于间隔区的所在位置是形成斜面。
作为较佳优选实施方案之一，所述承放导线对应于间隔区的所在位置是形成弧面。
作为较佳优选实施方案之一，所述承放导线与黏胶体相接触的区域为粗糙面。
作为较佳优选实施方案之一，所述粗糙面位于承放导线的顶面、侧面及底面。
作为较佳优选实施方案之一，在芯片放置于对称设置的承放导线上会同步加热，使得黏胶体软化填满间隔区并流至内凹部内。
作为较佳优选实施方案之一，在芯片以黏胶体放置于对称的承放导线上，利用黏晶头将芯片及黏胶体下压，使部份黏胶体填入间隔区并流至内凹部内。
与现有技术相比，本发明具有下列具体的功效：
1.本发明的芯片与承放导线之间具有黏胶体，且黏胶体分布间隔区及内凹部内，当黏胶体固化即形成钩状结构体，可增加承放导线的强度，改善打线制程的支撑强度，防止承放导线下陷变形。
2.因承放导线不会有下陷变形的情形，使芯片紧紧黏贴在承放导线上，后续封胶作业中就不容易受到模流而使芯片偏移。
3.不需花费许多成本，即可改善打线接合(Wire bonding)的良率，且持别适用于1mm*1mm小尺寸的封装组件。
附图说明
图1是现用技术中引脚上芯片(COL)的封装结构示意图。
图2为本发明半导体封装结构第一实施例的剖面示意图。
图3为本发明半导体封装结构第二实施例的剖面示意图。
图4为本发明半导体封装结构第三实施例的剖面示意图。
图5为本发明半导体封装结构第四实施例的剖面示意图。
图6为本发明半导体封装结构，第一实施例的芯片在引脚上(COL)的封装方法流程图。
图7A～图7H为本发明半导体封装结构，第一实施例的芯片在引脚上(COL)的封装方法运作示意图。
附图标记说明：1-导线架，11-引脚，111-承放导线，12-芯片，13-芯片黏贴薄膜，2-导线架，21-引脚，211-承放导线，212-内凹区，213-斜面，214-弧面，215-粗糙面，22-间隔区，3-芯片，4-黏胶体，5-引线，6-封胶体，7-切割装置，8-黏晶头。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟悉此技术领域的人士可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。本发明也可借由其它不同的具体实例例加以施行或应用，本发明说明书中的各项细节也可基于不同观点与应用在不悖离本发明的精神下进行各种修饰与变更。
如图2所示，为本发明半导体封装结构第一实施例的剖面示意图。本实施例包括：导线架2，具有多个引脚21。引脚21一端具有承放导线211。相邻对称之承放导线211形成间隔区22，承放导线211相接于间隔区22的底部形成内凹部212。芯片3，放置于承放导线211上且遮蔽间隔区22，芯片3与承放导线211接触区域设有黏胶体4，且黏胶体4也分布于间隔区22及内凹部212内。引线5，两端电性连接芯片3与引脚21。封胶体6，包覆芯片3、承放导线211、引线5且让引脚21部份露出。
本发明的设计是当芯片3以黏胶体4黏着于承放导线211时，加热施压会使黏胶体4软化进一步填满间隔区22并延伸至内凹部212内。如此当黏胶体4固化后，就会如同倒钩状紧紧固定于承放导线211，且让芯片3紧紧黏固于承放导线211上。在后续打线接合作业中，位于内凹部212内固化的黏胶体4，提供适当的支撑力，能有效防止承放导线211下陷，降低不良品的产生，提高生产质量。另外芯片3紧紧地黏贴于承放导线211上，在后续封胶作业中也不容易受到模流影响而使芯片3偏移。
在上述实施例中，间隔区22由上而下的纵向尺寸皆相同，但并不以此为限。本发明为了增加黏胶体4的流动或固化后的强度另设有下列种不同的实施例。如图3所示，为本发明半导体封装结构第二实施例的剖面示意图。在本实施例中该间隔区22的纵向尺寸是由上而下渐增。在本实施例中在承放导线211对应于间隔区22的所在位置形成斜面213，此目的是为使黏胶体4更容易地沿着斜面213流至间隔区22及内凹区212内。
如图4所示，为本发明半导体封装结构第三实施例的剖面示意图。在本实施例中该间隔区22的纵向尺寸仍为由上而下渐增。但在本实施例中在承放导线211对应于间隔区22的所在位置形成弧面214。弧面214也有助黏胶体4流至间隔区22及内凹区212内。
如图5所示。为本发明半导体封装结构第四实施例的剖面示意图。在本实施例中是在承放导线211的顶面、侧面及底面皆形成粗糙面215。粗糙面215分布于承放导线211与黏胶体4相接触的区域，此可增加黏胶体4与连接承放导线211的接触面积，改善黏胶体4设置于承放导线211的黏接强度。
接着如图6所示，为本发明半导体封装方法的流程图。请配合参阅图7A～图7H。本发明封装方法的步骤包括：
步骤301，涂布黏胶体4于晶圆30；如图7A所示，于晶圆30的底部涂布一层黏胶体4。
步骤302，贴附胶膜6于黏胶体4上；如图7B所示，于黏胶体4底部黏贴一层胶膜6。
步骤303，切割晶圆30形成多个芯片3，芯片3黏附着黏胶体4；如图7C所示，使用切割装置7切割晶圆30以形成多个芯片3，每个芯片3皆单独黏附着黏胶体4。
步骤304，自胶膜6上取下黏附着黏胶体4的芯片3；如图7D所示，使用黏晶头8吸取单颗芯片3，黏胶体4也会自胶膜6处剥离。
步骤305，将芯片3由黏胶体4放置于导线架2的对称设置的承放导线211上，黏胶体4填满承放导线211之间的间隔区22内，且分布于承放导线211底部的内凹部212内。如图7E所示，所使用导线架2具有多个引脚21，引脚21具有承放导线211。导线架2可利用半蚀刻方式于承放导线211底部形成内凹部212。对称设置的承放导线211之间形成有贯穿的间隔区22。请进一步参阅图7F所示，使用黏晶头8将芯片3放置承放导线211的过程中，也会同步加热，使得黏胶体4软化，分布在芯片3与承放导线211之间，再者，黏晶头8亦会提供芯片3一下压力，使黏胶体4填满间隔区22内及内凹部212内。待黏胶体4固化后就会如同倒钩状紧紧结合于承放导线211处。
步骤306，执行打线作业，使引线5两端分别电性连接芯片3及引脚21；如图7G所示，引线5两端连接于芯片3与引脚21上。
步骤307，由封胶体6塑封芯片3、承放导线211、引线5且让引脚21部份露出。如图7H所示，利用封胶体6包覆着芯片3、承放导线211、引线5、引脚21。其中引脚21会部份露出，作为电性连接端子。
综合以上所述，本发明芯片在引脚上(COL)的封装方法及结构，是在芯片3由黏胶体4黏着于承放导线211，进一步让黏胶体4分布于间隔区22及内凹部212内。当黏胶体4固化后，就会如同倒钩状紧紧固定于承放导线211，藉此提升导线架2的支撑强度，防止承放导线211下陷变形，以最低的成本发挥最大的效果，符合专利的申请要件。
然而，上述实施例仅例示性说明本发明的功效，而非用于限制本发明，任何熟习此技术领域的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。此外，在上述实施例中的组件的数量仅为例示性说明，也非用于限制本发明。因此本发明的权利保护范围，应如以下的申请专利范围所列。

Claims (10)

1.一种半导体封装结构，包括：导线架，具有多个引脚，所述引脚具有承放导线，相邻两个所述承放导线之间形成间隔区，所述承放导线相接于所述间隔区的底部形成内凹部；芯片，放置于所述承放导线上且遮蔽所述间隔区；引线，电性连接所述芯片与所述引脚；封胶体，包覆所述芯片、所述承放导线、所述引线且让所述引脚部份露出，其特征在于：所述芯片与所述承放导线接触区域设有黏胶体，且所述黏胶体分布于所述间隔区及所述内凹部内。
2.根据权利要求1所述的半导体封装结构，其特征在于：所述导线架以半蚀刻方式于所述承放导线底部形成所述内凹区。
3.根据权利要求1所述的半导体封装结构，其特征在于：所述间隔区的纵向尺寸是由上而下渐增。
4.根据权利要求3所述的半导体封装结构，其特征在于：所述承放导线对应于所述间隔区的所在位置是形成斜面。
5.根据权利要求3所述的半导体封装结构，其特征在于：所述承放导线对应于所述间隔区的所在位置是形成弧面。
6.根据权利要求1所述的半导体封装结构，其特征在于：所述承放导线与所述黏胶体相接触的区域为粗糙面。
7.根据权利要求6所述的半导体封装结构，其特征在于：所述粗糙面位于所述承放导线的顶面、侧面及底面。
8.一种半导体封装方法，其特征在于包括如下步骤：
涂布黏胶体于晶圆；
贴附胶膜于所述黏胶体上；
切割所述晶圆形成多个芯片，所述芯片黏附着所述黏胶体；
自所述胶膜上取下黏附着所述黏胶体的所述芯片；
将所述芯片以所述黏胶体放置于导线架的对称设置的承放导线上，所述黏胶体填满所述承放导线之间的间隔区内，且分布于所述承放导线底部的内凹部内；
执行打线作业，使引线两端分别电性连接所述芯片及所述引脚；
由封胶体塑封所述芯片、所述承放导线、所述引线且让所述引脚部份露出。
9.根据权利要求8所述的半导体封装方法，其特征在于：在所述芯片放置于对称的所述承放导线上会同步加热，使得所述黏胶体软化填满所述间隔区并流至所述内凹部内。
10.根据权利要求8所述的半导体封装方法，其特征在于：将所述芯片以所述黏胶体放置于对称的所述承放导线上，系利用黏晶头将所述芯片及所述黏胶体下压，使部份所述黏胶体，填入所述间隔区并流至所述内凹部内。
CN201910535814.8A 2019-06-20 2019-06-20 半导体封装方法及其结构 Pending CN112117241A (zh)

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