CN111969063A - 一种具有漏端肖特基接触的超结mosfet - Google Patents

一种具有漏端肖特基接触的超结mosfet Download PDF

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CN111969063A
CN111969063A CN202010994844.8A CN202010994844A CN111969063A CN 111969063 A CN111969063 A CN 111969063A CN 202010994844 A CN202010994844 A CN 202010994844A CN 111969063 A CN111969063 A CN 111969063A
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CN111969063B (zh
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郑崇芝
夏云
吴毅
孙瑞泽
刘超
陈万军
张波
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University of Electronic Science and Technology of China
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions

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Abstract

本发明涉及功率半导体技术，特别涉及一种具有漏端肖特基接触的超结MOSFET。相对于传统的超结MOSFET，本发明在器件的漏极一侧引入肖特基接触，其由延伸到器件漏极的N型漂移区与漏极金属形成。在反向导通时，漂移区内的空穴可以通过此肖特基接触泄放，并且此肖特基接触不向漂移区内注入电子，因此漂移区内的电荷数量极大地降低。本发明的有益成果：体二极管反向导通时注入的电荷降低明显，从而反向恢复过程中的反向恢复电荷极大地降低，反向恢复特性得以显著改善。

Description

一种具有漏端肖特基接触的超结MOSFET
技术领域
本发明属于功率半导体技术领域，特别涉及一种具有低反向恢复电荷的超结MOSFET(金属-氧化物半导体场效应晶体管，Metal-Oxide-Semiconductor Field-EffectTransistor,简称MOSFET)。
背景技术
超结MOSFET在全桥等驱动电机应用电路中，其体二极管起到续流作用。体二极管导通时，漂移区内存储着大量的空穴载流子。体二极管从导通状态到耐压状态切换的过程，需要排出体内存储的载流子，形成较大的反向电流。这不仅会增加了自身的损耗，另一方面会带来电磁干扰噪声，对应用系统造成不利影响。
发明内容
本发明的目的，就是针对上述问题，提出一种具有漏端肖特基接触的低反向恢复电荷超结MOSFET。
本发明的技术方案：一种具有漏端肖特基接触的超结MOSFET，如图1所示，其半元胞包括漏极结构、耐压层结构、源极结构和栅极结构，其中耐压层结构位于漏极结构之上，源极结构和栅极结构位于耐压层结构之上；
所述漏极结构包括漏极金属1以及N+漏区2；所述N+漏区2位于漏极金属1一侧的上表面；所述漏极金属1引出端为漏极D；
所述耐压层结构包括并列设置的N型漂移区4及P型漂移区3，N型漂移区4与P型漂移区3构成超结结构；所述P型漂移区3位于N+漏区2上表面，N型漂移区4位于漏极金属1上表面，N型漂移区4与N+漏区2的侧面接触；
所述源极结构包括P型阱区5、N+源区6、P+短路区7和源极金属8；所述P型阱区5位于P型漂移区3上表面，且P型阱区5沿器件横向方向延伸入N型漂移区4上层，N+源区6和P+短路区7并列设置于P型阱区5上层，且N+源区6位于靠近N型漂移区4的一侧；源极金属8位于P+短路区7和部分N+源区6上表面，源极金属10引出端为源极S；
所述栅极结构为平面栅，所述平面栅由绝缘介质9和位于绝缘介质9之上的导电材料10构成；所述绝缘介质9位于N型漂移区4、P型阱区5和部分N+源区6上表面；导电材料10的引出端为栅极G；
所述源极金属1与N型漂移区4形成肖特基接触。
本发明的有益效果为，本发明的具有低反向恢复电荷的超结MOSFET，极大地减小了反向恢复电荷，优化了反向恢复特性。
附图说明
图1是本发明的超结MOSFET示意图；
图2是常规超结MOSFET示意图；
图3是本发明超结MOSFET与常规超结MOSFET的反向导通I-V曲线示意图；
图4是本发明超结MOSFET与常规超结MOSFET漂移区内空穴载流子分布示意图；
图5是常规超结MOSFET反向导通时空穴分布示意图；
图6是常规超结MOSFET反向导通时电子分布示意图；
图7是本发明超结MOSFET反向导通时空穴分布示意图；
图8是本发明超结MOSFET反向导通时电子分布示意图；
图9是本发明超结MOSFET与常规超结MOSFET反向恢复电流仿真对比图；
具体实施方式
下面结合附图对本发明进行详细的描述
如图1所示，为本发明的具有漏端肖特基接触的低反向恢复电荷超结MOSFET。图2为常规的超结MOSFET。本发明的超结MOSFET与常规超结MOSFET体内都存在由P+短路区7/P型阱区5/P型漂移区3和N型漂移区4/N+漏区2组成的体二极管。本发明的超结MOSFET在漏极一侧引入了由N型漂移区4与漏极金属1组成肖特基接触。
其工作原理如下：
反向导通时，器件栅源极同接高电位，漏极接地。源极向漂移区注入空穴，而N+漏区2往漂移区注入电子。与普通超结MOSFET体二极管对比，一方面，由于本发明器件的N+漏区面积更小，从而电子注入效率更低，从而减少了漂移区内的载流子，另一方面，反偏的N型肖特基二极管给空穴提供了泄放通道，漂移区内的载流子浓度进一步降低。从而，漂移区内的载流子浓度下降，器件反向恢复特性得以改善。
图3为利用二维仿真软件仿真的反向导通特性，可以看出本发明器件的反向导通压降相对于普通超结MOSFET略微更高，这是由于漂移区的空穴载流子数量极大地降低，从而电导调制效应减弱。图4为本发明超结MOSFET与普通超结MOSFET体内空穴载流子分布的对比，可以看出，本发明的超结MOSFET漂移区内的空穴浓度极大地降低了。
图5-图8为普通超结MOSFET与本发明的超结MOSFET反向导通时的空穴载流子分布图，图9为本发明超结MOSFET与常规超结MOSFET反向恢复电流仿真对比图。600V等级的两种MOSFET在400V下进行反向恢复特性仿真，可以看出本发明超结MOSFET较常规超结MOSFET的反向恢复电流和反向恢复电荷下降明显。

Claims (1)

1.一种具有漏端肖特基接触的超结MOSFET，其半元胞包括漏极结构、耐压层结构、源极结构和栅极结构，其中耐压层结构位于漏极结构之上，源极结构和栅极结构位于耐压层结构之上；
所述漏极结构包括漏极金属(1)以及N+漏区(2)；所述N+漏区(2)位于漏极金属(1)一侧的上表面；所述漏极金属(1)引出端为漏极；
所述耐压层结构包括并列设置的N型漂移区(4)及P型漂移区(3)，N型漂移区(4)与P型漂移区(3)构成超结结构；所述P型漂移区(3)位于N+漏区(2)上表面，N型漂移区(4)位于漏极金属(1)上表面，N型漂移区(4)与N+漏区(2)的侧面接触；
所述源极结构包括P型阱区(5)、N+源区(6)、P+短路区(7)和源极金属(8)；所述P型阱区(5)位于P型漂移区(3)上表面，且P型阱区(5)沿器件横向方向延伸入N型漂移区(4)上层，N+源区(6)和P+短路区(7)并列设置于P型阱区(5)上层，且N+源区(6)位于靠近N型漂移区(4)的一侧；源极金属(8)位于P+短路区(7)和部分N+源区(6)上表面，源极金属(10)引出端为源极；
所述栅极结构为平面栅，所述平面栅由绝缘介质(9)和位于绝缘介质(9)之上的导电材料(10)构成；所述绝缘介质(9)位于N型漂移区(4)、P型阱区(5)和部分N+源区(6)上表面；导电材料(10)的引出端为栅极；
所述源极金属(1)与N型漂移区(4)形成肖特基接触。
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