CN111954955B - 集成天线阵列封装结构和方法 - Google Patents

集成天线阵列封装结构和方法 Download PDF

Info

Publication number
CN111954955B
CN111954955B CN201980025252.0A CN201980025252A CN111954955B CN 111954955 B CN111954955 B CN 111954955B CN 201980025252 A CN201980025252 A CN 201980025252A CN 111954955 B CN111954955 B CN 111954955B
Authority
CN
China
Prior art keywords
sub
antenna array
package
pattern
antenna
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980025252.0A
Other languages
English (en)
Other versions
CN111954955A (zh
Inventor
顾晓雄
刘兑现
C·W·巴克斯
A·瓦尔德斯·加西亚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN111954955A publication Critical patent/CN111954955A/zh
Application granted granted Critical
Publication of CN111954955B publication Critical patent/CN111954955B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15323—Connection portion the connection portion being formed on the die mounting surface of the substrate being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Support Of Aerials (AREA)
  • Wire Bonding (AREA)

Abstract

一种装置包括天线阵列封装盖，该天线阵列封装盖包括辐射表面、与辐射表面相对设置的配合表面、以及天线阵列子方向图阵列，其中每个天线阵列子方向图包括至少一个天线元件。天线阵列封装还包括与天线阵列封装盖的配合表面配合的子方向图接口封装阵列。子方向图接口封装阵列中的每个子方向图接口封装包括封装载体、电耦合和机械耦合到封装载体的子方向图集成电路、以及与天线阵列子方向图的天线元件的一组接口线，天线阵列子方向图对应于子方向图接口封装。本文还公开了用于将上述装置安装到主机电路中的方法。

Description

集成天线阵列封装结构和方法
背景技术
本发明总体上涉及无线设备封装结构，并且具体地，涉及用于封装具有例如毫米波RF集成电路等半导体芯片的天线阵列结构以形成紧凑集成无线通信系统的技术。
当构造具有集成天线阵列的无线通信封装结构时，重要的是实现提供适当的天线特性(例如，高效率、宽带宽、良好的辐射特性等)和阵列可配置性(例如，行和列中的天线元件)同时提供低成本和可靠的封装解决方案的封装设计。
封装无线通信系统的典型方法包括创建单个封装或模块化封装。使用单个封装需要为可能需要的每个可能的天线配置创建完整的定制封装。这种方法增加了前期设计成本、制造返工成本和库存成本。模块化封装降低了上述成本，但是降低了大天线阵列的天线元件相对于彼此的均匀性和/或放置精度，并且由此降低了天线性能。
发明内容
在本发明的一个实施例中，一种装置包括天线阵列封装盖，其包括辐射表面、与辐射表面相对设置的配合表面、以及天线阵列子方向图阵列，其中每个天线阵列子方向图包括至少一个天线元件。天线阵列封装还包括与天线阵列封装盖的配合表面配合的子方向图接口封装阵列。每个子方向图接口封装可以包括封装载体；子方向图集成电路，其电耦合并且机械耦合到封装载体；以及一组接口线，其对应于天线阵列子方向图的天线元件，天线阵列子方向图对应于子方向图接口封装。
每个子方向图接口封装可以被设置在天线阵列子方向图阵列的对应天线阵列子方向图下方。子方向图集成电路可以倒装芯片接合到封装载体，并且包括封装载体的天线阵列封装可以安装在主机电路上。例如，天线阵列封装可以通过球栅格阵列(BGA)或平面栅格阵列(LGA)插座安装在主机电路上。主机电路可以包括一个或多个散热器，一个或多个散热器通过多个热导管热连接到子方向图集成电路。
本文还公开了用于将上述装置安装到主机电路中的方法。在本发明的一个实施例中，第一方法包括提供天线阵列封装盖，提供子方向图接口封装，将多个子方向图接口封装配合到天线阵列封装盖的配合表面以产生天线阵列封装，以及将天线阵列封装安装到主机电路上。在本发明的一个实施例中，第二种方法包括提供天线阵列封装盖，提供子方向图接口封装，以及将多个子方向图接口封装安装到主机电路上。第二种方法还包括在将多个子方向图接口封装安装到主机电路之后，将多个子方向图接口封装配合到天线阵列封装盖的配合表面。
上述装置和方法能够提供具有降低的前期设计成本、制造返工成本和库存成本的无线通信系统，而不降低那些系统所使用的天线元件的均匀性和放置精度。
附图说明
为了容易理解本发明的实施例的优点，将通过参考在附图中示出的具体实施例来呈现以上简要描述的实施例的更具体的描述。应理解，这些附图仅描述了本发明的一些实施例，因此不应被认为是对范围的限制，将通过使用附图以附加的特征和细节来描述和解释本发明的实施例，其中：
图1A、1B和1C是根据本发明的实施例的天线阵列封装的截面视图图示；
图2A、2B和2C是根据本发明的实施例的天线阵列封装盖的平面视图图示；
图3A、3B和3C是根据本发明的实施例的具有间隔器框架的天线阵列封装的截面视图图示；以及
图4A和4B是根据本发明的实施例的天线系统制造方法的示例的流程图。
具体实施方式
在整个说明书中，对"一个实施例"、"实施例"或类似语言的引用表示结合该实施例描述的特定特征、结构或特性被包括在至少一个实施例中。因此，在整个说明书中的短语"在一个实施例中"、"在实施例中"和类似语言的出现可以但不必都指代相同的实施例，而是表示"一个或多个但不是所有实施例"，除非另外明确指出。术语"包括"、"包含"、"具有"及其变体表示"包括但不限于"，除非另外明确指出。列举的项目列表并不意味着任何或所有项目是互斥的和/或相互包含的，除非另外明确指出。术语"一"、"一个"和"该"也指代"一个或多个"，除非另外明确指出。
图1A、1B和1C是根据本发明的一个或多个实施例的天线阵列系统100的几个示例的截面视图图示。如图所示，天线阵列系统100包括天线阵列封装110，其包括与天线阵列封装盖130配合的多个子方向图接口封装120。天线阵列封装110可以安装在主机电路140上。天线阵列系统100实现大天线阵列结构与对接到天线阵列结构的无线电路的紧凑的成本有效的集成。
天线阵列封装110可以包括一组主机电路连接器112，其提供到主机电路140的电连接和/或机械连接。在所描述的实施例中，主机电路连接器112包括具有受控直径和高度的焊球阵列(BGA)。
天线阵列封装110包括形成在天线阵列封装盖130上的一个或多个天线阵列114，一个或多个天线阵列114可以用于发射和/或接收电磁信号，例如毫米波信号。在所描述的实施例中，天线阵列封装110包括单个天线阵列114，单个天线阵列114包括由放置在天线阵列封装盖130的一个或多个封装层132上的一个或多个导电结构形成的天线元件134。例如，天线元件134可以对应于不同类型的天线，诸如微带天线；(例如，贴片和倒F天线)堆叠贴片天线；环形天线；偶极天线；蝶形天线；分形天线；缝隙天线；行波天线，例如螺旋、盘旋和八木-宇田天线；反射器天线；等等。
子方向图接口封装120可以经由一组天线馈电123向天线阵列114提供信号和/或从其接收信号。在所描述的实施例中，每个子方向图接口封装120包括与天线元件134的子集相对应的天线馈电123，这里将其称为天线阵列子方向图116。在本发明的一些实施例中，每个子方向图接口封装120被设置在对应的天线阵列子方向图116下方。将每个接口封装120设置在对应的天线阵列子方向图116下方缩短了封装120和对应的天线元件134之间的信号路径，并且可以提高性能。此外，将天线阵列子方向图116放置在天线阵列封装盖130上和对应的子方向图接口封装120上方，实现多个天线阵列子方向图116的相邻放置，并且由此减小天线阵列系统100的表面面积。在本发明的一些实施例中，每个天线阵列子方向图116是天线阵列114的子阵列。
每个子方向图接口封装120包括封装载体121，封装载体121包括多个封装层122，多个封装层122可以用于对经由一个或多个芯片连接器126连接到一个或多个子方向图集成电路125的天线馈电123进行布线。芯片连接器126可以包括C4焊球，C4焊球在规模上小于主机电路连接器112的焊球。集成电路125可以经由天线馈电123与天线元件134对接，并且为每个天线元件134提供诸如频率转换功能以及幅度和/或相位控制功能之类的其他功能。
在本发明的一些实施例中，封装载体121和/或天线阵列封装盖130包括多层有机载体，多层有机载体可以使用已知的载体制造技术来构造，例如SLC(表面层合电路)、HDI(高密度互连)或实现具有高集成密度的基于有机物的多层电路板的形成的其他载体制造技术。利用这些载体制造技术，载体衬底可以由包括金属化和电介质/绝缘体材料的交替层的层合的堆叠形成，其中金属化层通过电介质/绝缘材料的相应层与上覆和/或下覆金属化层分离。金属化层可以由铜形成，而介电/绝缘层可以由有机堆积物和芯材料形成。其他类型的材料可以用于封装载体121和/或天线阵列封装盖130的金属化层和绝缘层，例如LCP(液晶聚合物)、玻璃或LTCC(低温共烧陶瓷)。此外，这些技术能够使用例如激光烧蚀、光成像或蚀刻形成小的导电通孔(例如，相邻金属化层之间的部分或掩埋通孔)，以能够在载体衬底内形成高密度布线和互连结构。
子方向图集成电路125可以包括形成在每个芯片的芯片连接器侧(如所示的顶侧)上的金属化方向图(未具体示出)。金属化方向图可以包括其上形成芯片连接器126的接合/接触焊盘。接合/接触焊盘可以包括例如接地焊盘、DC电源焊盘、输入/输出焊盘、控制信号焊盘、相关联布线等，它们形成为子方向图集成电路125的BEOL(后段)布线结构的一部分。
每个子方向图集成电路125可以经由倒装芯片接合(在此期间，可以将子方向图接口封装120的定向从所示的方向翻转)而电连接和机械连接到特定的子方向图接口封装120，并由此连接到天线阵列封装110。根据应用，子方向图集成电路125单独地或共同地可以包括RF电路和形成在其上的电子部件，包括例如接收器、发射器或收发器电路、以及通常用于实现无线RF芯片的其他有源或无源电路元件。
天线阵列封装盖130可以包括辐射表面136和配合表面138，电磁辐射优选地从该辐射表面136被发射，配合表面138用于将天线阵列封装盖130与子方向图接口封装120配合。在一些实施例中，天线阵列封装盖130通常使用环氧树脂粘合剂或一些其他粘合材料与子方向图接口封装120配合，并且具体地与封装载体121配合。备选地，天线阵列封装盖130可以通过紧固件(例如，见图3A-3C)或通过焊球(未示出)和焊料回流工艺与子方向图接口封装120配合。
主机电路140可以包括多个电路层142，多个电路层142可以用于在主机电路连接器112和安装在主机电路140的在所描述的示例中未示出的部分上的部件之间对信号迹线进行布线。在一些实施例中，热连接层127设置在主机电路140和每个子方向图集成电路125之间。热连接层127可以将子方向图集成电路125的非有源表面(如图所示的底表面)热耦合到主机电路140的与散热器144和一个或多个热导管146(例如，金属填充的通孔或基座)对准的区域。热连接层127用于将热量从子方向图集成电路125传递到热导管146，该热导管146将热量传递到散热器144以进行散热(例如，通过传导、对流和辐射)。
天线元件134可以经由各种天线馈电结构耦合到天线馈电123，天线馈电结构包括本领域技术人员已知的结构，诸如孔径耦合结构和微带馈电耦合结构。天线馈电结构可以设置在天线阵列封装盖130和/或子方向图接口封装120的表面之内或之上。例如，图1A和1C描述了天线馈电结构完全位于子方向图接口封装120内的布置。相反，图1B描述了其中天线馈电结构的至少一部分位于天线阵列封装盖130中的布置。在所描述的布置中，天线馈电123经由连接元件137从子方向图接口封装120交叉到天线阵列封装盖130中。
可能的连接元件137的示例包括诸如柱的层叠封装互连。一些连接元件137可以连接到测试引脚139，以能够测试子方向图集成电路125。在未示出的另一布置中，连接元件137可以连接到微带馈线结构，该微带馈线结构直接连接到天线元件134。在未示出的另一布置中，所有连接元件137连接到外部测试引脚139，形成支持用于测试目的的连接器化测量的封装盖的替换版本。这种测试可以支持返工组装的天线阵列封装110并减少制造损失。
图2A、2B和2C是根据本发明的实施例的天线阵列封装盖130的几个示例的平面视图图示。如所描述的，天线阵列封装盖130包括2×2(即，2行和2列)配置200A、1×5(即，1行和5列)配置200B、以及2×3(即，2行和3列)配置200C。在所描述的示例中，为了清楚起见，行和列边界用虚线指示。每个结构与一组子方向图接口封装120配合，其中该组中的封装数目等于特定配置的行数和列数的乘积。
本领域技术人员将理解，通过将多个子方向图接口封装120与对应于期望天线阵列尺寸的天线阵列封装盖130配合来提供天线阵列封装110降低了提供各种尺寸的天线阵列(例如图2A-2C中所描述的那些)的复杂性。此外，可以简化天线阵列封装盖130上或其内的信号布线，因为各种大小的天线阵列封装盖130的信号布线方向图可以使用用于(即，重复用于)天线阵列114内的每个阵列子方向图116的公共单位单元。此外，天线元件134的大小和间隔均匀性可以用公共天线阵列封装盖130来实现。
图3A、3B和3C是根据本发明的实施例的天线阵列封装300的几个示例的截面视图图示。每个所描述的示例包括具有紧固件320的单个间隔器框架310，该紧固件将间隔器框架固定在天线阵列封装盖130和主机电路140之间。紧固件320可以包括各种紧固装置，例如销、铆钉、螺钉、螺栓、螺母等。
图3A描述了具有间隔器框架310A和BGA电路连接器112的天线阵列封装300A，BGA电路连接器112如先前图中所示直接连接到主机电路140。图3B描述了具有间隔器框架310B和设置在电路连接器112和主机电路140之间的LGA内插件330的天线阵列封装300B。一组引脚332确保电路连接器112和主机电路140之间的电连接。在所描述的布置中，LGA内插件330与间隔器框架310B集成。图3C描述了具有多级间隔器框架310C和多个长度的长度紧固件320以及与间隔器框架310C集成的LGA内插件330的天线阵列封装300C。多级间隔器框架310C使得能够经由天线阵列封装盖130中的孔径340和设置在其中的紧固件320直接固定封装载体121。
图4A和4B是根据本发明的实施例的天线系统制造方法400的两个示例的流程图。图4A所示的第一示例400A包括提供410天线阵列封装盖，将多个子方向图接口封装配合420到天线阵列封装盖的配合表面以产生天线阵列封装，以及将天线阵列封装安装430到主机电路上。所描述的布置基本上使用盖作为用于构建安装到主PCB的天线封装的衬底。
天线系统制造方法400的第二实例400B包括提供460子方向图接口封装和将多个子方向图接口封装安装470到主机电路上。第二实例还包括在将多个子方向图接口封装安装到主机电路之后，将多个子方向图接口封装配合480到天线阵列封装盖的配合表面。所描述的布置基本上将多个子方向图接口封装(载体+RFIC)安装到主机PCB，并用公共天线盖覆盖子方向图接口封装。
本领域技术人员将理解，本文公开的本发明的实施例提供了一种用于封装无线通信系统的模块化方法，其降低了前期设计成本、制造返工成本和库存成本，而不会降低大型天线阵列的天线元件相对于彼此的均匀性和放置精度，并且不会降低天线性能。
本文所述的本发明的实施例的特征、优点和特性可以以任何合适的方式组合。相关领域的技术人员将认识到，可以在没有本发明的特定实施例的一个或多个特定特征或优点的情况下实践本发明的实施例。在其他情况下，在本发明的某些实施例中可以认识到可能不在本发明的所有实施例中存在的附加特征和优点。
在整个说明书中，对"一个实施例"、"实施例"或类似语言的引用表示结合该实施例描述的特定特征、结构或特性被包括在至少一个实施例中。因此，在整个说明书中的短语"在一个实施例中"、"在实施例中"和类似语言的出现可以但不必都指代相同的实施例，而是表示"一个或多个但不是所有实施例"，除非另外明确指出。术语"包括"、"包含"、"具有"及其变体表示"包括但不限于"，除非另外明确指出。列举的项目列表并不意味着任何或所有项目是互斥的和/或相互包含的，除非另外明确指出。术语"一"、"一个"和"该"也指代"一个或多个"，除非另外明确指出。
附图中的示意性流程图和/或示意性框图示出了可能实现的架构、功能和操作。还应当注意，在一些备选实现中，框中所标注的功能可以不按图中所标注的顺序发生。例如，连续示出的两个框实际上可以基本上同时执行，或者这些框有时可以以相反的顺序执行，这取决于所涉及的功能。尽管在流程图和/或框图中可以采用各种箭头类型和线类型，但是应当理解，它们不限制本发明的对应实施例的范围。实际上，一些箭头或其他连接符可以用于仅指示本发明的所描述的实施例的示例性逻辑流程。
每幅图中的元件的描述可以参考前面各图中的元件。在所有附图中，相同的附图标记表示相同的元件，包括相同元件的替代实施例。本发明的实施例可以以其他具体形式实践。本发明的所述实施例在所有方面都应被认为仅是说明性的而非限制性的。因此，本发明的范围由所附权利要求而不是由前面的描述来指示。在权利要求的等效含义和范围内的所有改变都将包含在其范围内。

Claims (16)

1.一种装置，包括：
天线阵列封装盖，其包括辐射表面、与所述辐射表面相对设置的配合表面、以及包括多个天线阵列子方向图的天线阵列子方向图阵列，其中每个天线阵列子方向图包括至少一个天线元件；
与所述天线阵列封装盖的所述配合表面配合的子方向图接口封装阵列，其中所述子方向图接口封装阵列包括多个子方向图接口封装；以及，
其中所述子方向图接口封装阵列中的每个子方向图接口封装包括封装载体、电气耦合和机械耦合到所述封装载体的子方向图集成电路、以及与所述天线阵列子方向图的所述天线元件相对应的一组接口线，所述天线阵列子方向图对应于所述子方向图接口封装，以及
其中所述子方向图接口封装被设置在对应的所述天线阵列子方向图下方，并且所述天线阵列子方向图被设置在天线阵列封装盖上对应的所述子方向图接口封装上方。
2.根据权利要求1所述的装置，其中所述子方向图集成电路被倒装芯片接合到所述封装载体。
3.根据权利要求1所述的装置，其中所述天线阵列封装盖和所述子方向图接口封装阵列形成天线阵列封装。
4.根据权利要求3所述的装置，其中所述天线阵列封装被安装在主机电路上。
5.根据权利要求4所述的装置，其中所述天线阵列封装经由球栅格阵列(BGA)或平面栅格阵列(LGA)插座被安装在所述主机电路上。
6.根据权利要求4所述的装置，其中所述主机电路包括一个或多个散热器，所述一个或多个散热器经由多个热导管热连接到所述多个子方向图集成电路。
7.根据权利要求6所述的装置，其中所述一个或多个热导管中的热导管包括基座。
8.根据权利要求4所述的装置，还包括设置在所述天线阵列封装盖和所述主机电路之间的间隔器框架。
9.根据权利要求1所述的装置，其中所述天线阵列封装盖包括用于所述天线阵列子方向图阵列中的每个天线阵列子方向图的一组天线馈电。
10.根据权利要求1所述的装置，其中所述天线阵列封装盖包括测试接口元件，所述测试接口元件电连接到至少一个子方向图集成电路。
11.根据权利要求1所述的装置，其中所述子方向图接口封装阵列通过支撑球、粘合剂和至少一个紧固件中的一个或多个固定到所述天线阵列封装盖的所述配合表面。
12.根据权利要求1所述的装置，其中所述天线阵列封装盖或所述封装载体包括多个层。
13.根据权利要求1所述的装置，其中所述封装载体包括用于焊球栅格阵列的接合焊盘。
14.根据权利要求1所述的装置，其中每个天线元件包括设置在所述辐射表面上或下方的导电材料贴片。
15.根据权利要求1所述的装置，其中所述天线元件被设置在所述天线阵列封装盖的多个层上。
16.一种方法，包括：
提供天线阵列封装盖，所述天线阵列封装盖包括辐射表面、与所述辐射表面相对设置的配合表面、以及包括多个天线阵列子方向图的天线阵列子方向图阵列，其中每个天线阵列子方向图包括至少一个天线元件；
提供多个子方向图接口封装，其中所述多个子方向图接口封装中的每个子方向图接口封装包括封装载体和接合到所述封装载体的接合焊盘的子方向图集成电路；以及以下之一：
将所述多个子方向图接口封装配合到所述天线阵列封装盖的所述配合表面以产生天线阵列封装，以及将所述天线阵列封装安装到主机电路上；以及，
将所述多个子方向图接口封装安装到主机电路上，并且在将所述多个子方向图接口封装安装到所述主机电路上之后，将所述多个子方向图接口封装配合到天线阵列封装盖的所述配合表面，以及
将所述子方向图接口封装设置在对应的所述天线阵列子方向图下方，并且将所述天线阵列子方向图设置在天线阵列封装盖上对应的所述子方向图接口封装上方，
其中所述多个子方向图接口封装中的每个子方向图接口封装包括与所述天线阵列子方向图的所述天线元件相对应的一组接口线，所述天线阵列子方向图对应于所述子方向图接口封装。
CN201980025252.0A 2018-04-13 2019-03-05 集成天线阵列封装结构和方法 Active CN111954955B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/953,075 2018-04-13
US15/953,075 US11189905B2 (en) 2018-04-13 2018-04-13 Integrated antenna array packaging structures and methods
PCT/IB2019/051759 WO2019197916A1 (en) 2018-04-13 2019-03-05 Integrated antenna array packaging structures and methods

Publications (2)

Publication Number Publication Date
CN111954955A CN111954955A (zh) 2020-11-17
CN111954955B true CN111954955B (zh) 2023-05-23

Family

ID=68160495

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980025252.0A Active CN111954955B (zh) 2018-04-13 2019-03-05 集成天线阵列封装结构和方法

Country Status (6)

Country Link
US (1) US11189905B2 (zh)
JP (1) JP7268949B2 (zh)
CN (1) CN111954955B (zh)
DE (1) DE112019001942T5 (zh)
GB (1) GB2587106B (zh)
WO (1) WO2019197916A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110401008B (zh) * 2018-04-25 2022-02-25 华为技术有限公司 带有封装天线的封装架构及通信设备
US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package
KR102593888B1 (ko) * 2019-06-13 2023-10-24 삼성전기주식회사 안테나 모듈 및 이를 포함하는 전자기기
KR102603106B1 (ko) * 2019-09-04 2023-11-15 삼성전기주식회사 어레이 안테나
KR20210072938A (ko) * 2019-12-10 2021-06-18 삼성전기주식회사 안테나 기판 및 이를 포함하는 안테나 모듈
CN110994116B (zh) * 2019-12-24 2022-02-11 瑞声精密制造科技(常州)有限公司 一种天线的散热结构和天线组件
KR102283081B1 (ko) * 2020-01-30 2021-07-30 삼성전기주식회사 안테나 장치
KR20220111503A (ko) * 2021-02-02 2022-08-09 삼성전자주식회사 안테나 모듈 및 이를 포함하는 전자 장치
CN112994730A (zh) * 2021-02-04 2021-06-18 广东富宇鸿通讯有限公司 一种通信天线系统、通讯信号的收发方法、应用
KR20220114965A (ko) * 2021-02-09 2022-08-17 삼성전자주식회사 안테나 모듈 및 이를 포함하는 장치
US11710902B2 (en) 2021-02-09 2023-07-25 International Business Machines Corporation Dual-polarized magneto-electric antenna array
US20220321239A1 (en) * 2021-04-01 2022-10-06 Hughes Network Systems, Llc Cavity Resonance Suppression Using Discrete Thermal Pedestals in Active Electronically Scanned Array
US11876059B2 (en) * 2021-05-17 2024-01-16 Nxp Usa, Inc. Semiconductor device with directing structure and method therefor
WO2023282810A1 (en) * 2021-07-09 2023-01-12 Telefonaktiebolaget Lm Ericsson (Publ) Topside cooled antenna-in-package
US20230307846A1 (en) * 2022-03-22 2023-09-28 Intel Corporation High precision scalable packaging architecture based on radio frequency scanning
TWI793024B (zh) * 2022-05-26 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000013138A (ja) * 1998-06-18 2000-01-14 Mitsubishi Electric Corp アレーアンテナ給電装置
CN103400829A (zh) * 2012-08-01 2013-11-20 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN103618130A (zh) * 2013-10-18 2014-03-05 中国电子科技集团公司第十研究所 嵌入式智能蒙皮天线
CN103779319A (zh) * 2012-10-19 2014-05-07 英飞凌科技股份有限公司 具有集成天线的半导体封装及其形成方法
WO2015088486A1 (en) * 2013-12-09 2015-06-18 Intel Corporation Antenna on ceramics for a packaged die

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512901A (en) * 1991-09-30 1996-04-30 Trw Inc. Built-in radiation structure for a millimeter wave radar sensor
US20020170746A1 (en) * 2000-01-13 2002-11-21 Raj N Master Organic packages with solders for reliable flip chip connections
TW498961U (en) 2001-04-17 2002-08-11 Yu-Peng Liou Structure improvement of lamp holder for decorative light
JP2003309483A (ja) 2002-04-16 2003-10-31 Mitsubishi Electric Corp 高周波モジュール，アクティブフェーズドアレーアンテナ及び通信装置
JP2004363347A (ja) * 2003-06-05 2004-12-24 Oki Electric Ind Co Ltd 多層プリント基板
US7119745B2 (en) 2004-06-30 2006-10-10 International Business Machines Corporation Apparatus and method for constructing and packaging printed antenna devices
US7236666B2 (en) 2004-09-30 2007-06-26 Intel Corporation On-substrate microlens to couple an off-substrate light emitter and/or receiver with an on-substrate optical device
US7531407B2 (en) * 2006-07-18 2009-05-12 International Business Machines Corporation Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same
US7671696B1 (en) * 2006-09-21 2010-03-02 Raytheon Company Radio frequency interconnect circuits and techniques
US7675465B2 (en) * 2007-05-22 2010-03-09 Sibeam, Inc. Surface mountable integrated circuit packaging scheme
US7880677B2 (en) 2007-12-12 2011-02-01 Broadcom Corporation Method and system for a phased array antenna embedded in an integrated circuit package
GB2458656A (en) 2008-03-26 2009-09-30 Jonathan Gregory Leckey Compact integrated circuit antenna
US7696930B2 (en) * 2008-04-14 2010-04-13 International Business Machines Corporation Radio frequency (RF) integrated circuit (IC) packages with integrated aperture-coupled patch antenna(s) in ring and/or offset cavities
US7852281B2 (en) 2008-06-30 2010-12-14 Intel Corporation Integrated high performance package systems for mm-wave array applications
JP2010098274A (ja) * 2008-10-20 2010-04-30 Sibeam Inc 表面実装可能な集積回路のパッケージ化機構
CN102217064A (zh) 2008-11-19 2011-10-12 Nxp股份有限公司 毫米波射频天线模块
US8587482B2 (en) 2011-01-21 2013-11-19 International Business Machines Corporation Laminated antenna structures for package applications
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
US8901688B2 (en) 2011-05-05 2014-12-02 Intel Corporation High performance glass-based 60 ghz / mm-wave phased array antennas and methods of making same
KR101218989B1 (ko) 2011-07-15 2013-01-21 삼성전기주식회사 반도체 패키지 및 그 제조방법
US8816929B2 (en) 2011-07-27 2014-08-26 International Business Machines Corporation Antenna array package and method for building large arrays
US9203159B2 (en) * 2011-09-16 2015-12-01 International Business Machines Corporation Phased-array transceiver
US8648454B2 (en) 2012-02-14 2014-02-11 International Business Machines Corporation Wafer-scale package structures with integrated antennas
US9711465B2 (en) 2012-05-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
US8952521B2 (en) * 2012-10-19 2015-02-10 Infineon Technologies Ag Semiconductor packages with integrated antenna and method of forming thereof
US9196951B2 (en) 2012-11-26 2015-11-24 International Business Machines Corporation Millimeter-wave radio frequency integrated circuit packages with integrated antennas
CN103869329A (zh) * 2012-12-13 2014-06-18 北京天中磊智能科技有限公司 一种一体化卫星导航芯片及其制造方法
JP5986499B2 (ja) * 2012-12-21 2016-09-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9413079B2 (en) * 2013-03-13 2016-08-09 Intel Corporation Single-package phased array module with interleaved sub-arrays
US9461355B2 (en) * 2013-03-29 2016-10-04 Intel Corporation Method apparatus and material for radio frequency passives and antennas
US9214433B2 (en) * 2013-05-21 2015-12-15 Xilinx, Inc. Charge damage protection on an interposer for a stacked die assembly
US9806422B2 (en) * 2013-09-11 2017-10-31 International Business Machines Corporation Antenna-in-package structures with broadside and end-fire radiations
US9531087B2 (en) 2013-10-31 2016-12-27 Sony Corporation MM wave antenna array integrated with cellular antenna
US9659904B2 (en) 2013-12-12 2017-05-23 Intel Corporation Distributed on-package millimeter-wave radio
US9773742B2 (en) * 2013-12-18 2017-09-26 Intel Corporation Embedded millimeter-wave phased array module
US9472859B2 (en) 2014-05-20 2016-10-18 International Business Machines Corporation Integration of area efficient antennas for phased array or wafer scale array antenna applications
US9620464B2 (en) * 2014-08-13 2017-04-11 International Business Machines Corporation Wireless communications package with integrated antennas and air cavity
US9331030B1 (en) 2014-12-15 2016-05-03 Industrial Technology Research Institute Integrated antenna package and manufacturing method thereof
US10340607B2 (en) 2015-08-26 2019-07-02 Qualcomm Incorporated Antenna arrays for communications devices
EP3381085A4 (en) 2015-09-18 2019-09-04 Anokiwave, Inc. LAMINAR PHASE CONTROL NETWORK ANTENNA
DE112015007212T5 (de) * 2015-12-22 2018-10-04 Intel Corporation Mikroelektronische Vorrichtungen mit effizienter Partitionierung von Hochfrequenzkommunikationsvorrichtungen, die auf einem Gehäuse-Fabric integriert sind
CN108463923A (zh) 2016-01-14 2018-08-28 华为技术有限公司 相控天线阵列器件
US10074900B2 (en) * 2016-02-08 2018-09-11 The Boeing Company Scalable planar packaging architecture for actively scanned phased array antenna system
SG11201811465WA (en) * 2016-06-24 2019-01-30 Agency Science Tech & Res Semiconductor package and method of forming the same
CN106207492B (zh) 2016-08-28 2019-06-28 中国电子科技集团公司第十研究所 高密度集成一体化瓦式有源相控阵天线架构
CN107564900B (zh) * 2017-08-29 2019-09-03 中国电子科技集团公司第五十八研究所 基于射频信号传输的扇出型封装结构及制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000013138A (ja) * 1998-06-18 2000-01-14 Mitsubishi Electric Corp アレーアンテナ給電装置
CN103400829A (zh) * 2012-08-01 2013-11-20 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN103779319A (zh) * 2012-10-19 2014-05-07 英飞凌科技股份有限公司 具有集成天线的半导体封装及其形成方法
CN103618130A (zh) * 2013-10-18 2014-03-05 中国电子科技集团公司第十研究所 嵌入式智能蒙皮天线
WO2015088486A1 (en) * 2013-12-09 2015-06-18 Intel Corporation Antenna on ceramics for a packaged die

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BGA organic module for 60 GHz LOS communications;Aimeric Bisognin;《 2016 International Symposium on Antennas and Propagation (ISAP)》;全文 *

Also Published As

Publication number Publication date
US11189905B2 (en) 2021-11-30
DE112019001942T5 (de) 2021-01-21
JP2021520739A (ja) 2021-08-19
CN111954955A (zh) 2020-11-17
JP7268949B2 (ja) 2023-05-08
GB2587106A (en) 2021-03-17
WO2019197916A1 (en) 2019-10-17
US20190319338A1 (en) 2019-10-17
GB2587106B (en) 2022-05-18
GB202016144D0 (en) 2020-11-25

Similar Documents

Publication Publication Date Title
CN111954955B (zh) 集成天线阵列封装结构和方法
US9064787B2 (en) Integrated antennas in wafer level package
US9985346B2 (en) Wireless communications package with integrated antennas and air cavity
JP6964381B2 (ja) 集積アンテナ・アレーを有するワイヤレス通信パッケージ
TWI676219B (zh) 半導體封裝
US8648454B2 (en) Wafer-scale package structures with integrated antennas
US11004810B2 (en) Semiconductor package structure
US7675465B2 (en) Surface mountable integrated circuit packaging scheme
US9196951B2 (en) Millimeter-wave radio frequency integrated circuit packages with integrated antennas
US9305888B2 (en) Integrated antenna structure and array
CN111276473A (zh) 用于扇出式封装的具有背面互连线的单片微波集成电路
US10714829B2 (en) Planar phased array antenna
Gu et al. An enhanced 64-element dual-polarization antenna array package for W-band communication and imaging applications
CN115332779B (zh) 相控阵天线的封装组件
EP2178119B1 (en) Surface mountable integrated circuit package
JP2010098274A (ja) 表面実装可能な集積回路のパッケージ化機構
CN111128909A (zh) 一种射频系统微型封装结构及其制备方法
CN112864147B (zh) 一种可组合式的三维多芯片封装结构
JP5762452B2 (ja) 表面実装可能な集積回路のパッケージ化機構
JP2015026873A (ja) 表面実装可能な集積回路のパッケージ化機構
TWI812283B (zh) 天線結構及封裝天線
CN117748105A (zh) 集成基板的三维模塑扇出型毫米波封装天线及其制作方法
CN116259615A (zh) 多材料体系复合集成的晶圆子阵互联结构及晶圆子阵
AU2008230024C1 (en) Surface mountable integrated circuit packaging scheme
CN117638482A (zh) 基于可扩展AiP的相控阵前端架构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant