CN111952314A - 非挥发性存储器结构 - Google Patents
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- 230000014759 maintenance of location Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
本发明公开一种非挥发性存储器结构,其包括基底、堆叠结构、导体柱、通道层、电荷存储结构与第二介电层。堆叠结构设置在基底上,且具有开口。堆叠结构包括交替堆叠的多个第一导体层与多个第一介电层。导体柱设置在开口中。通道层设置在堆叠结构与导体柱之间。电荷存储结构设置在堆叠结构与通道层之间。第二介电层设置在通道层与导体柱之间。上述非挥发性存储器结构可有效地提升存储器元件的电性效能及可靠度。
Description
技术领域
本发明涉及一种存储器结构,且特别是涉及一种非挥发性存储器结构。
背景技术
由于非挥发性存储器(non-volatile memory)可进行多次数据的存入、读取与抹除等操作,且具有当电源供应中断时,所存储的数据不会消失、数据存取时间短以及低消耗功率等优点,所以已成为个人计算机和电子设备所广泛采用的一种存储器。
然而,随着非挥发性存储器的集成度不断提升,如何提升存储器元件的电性效能及可靠度为目前业界所持续努力的目标。
发明内容
本发明提供一种非挥发性存储器结构,其可有效地提升存储器元件的电性效能及可靠度。
本发明提出一种非挥发性存储器结构,包括基底、堆叠结构、导体柱、通道层、电荷存储结构与第二介电层。堆叠结构设置在基底上,且具有开口。堆叠结构包括交替堆叠的多个第一导体层与多个第一介电层。导体柱设置在开口中。通道层设置在堆叠结构与导体柱之间。电荷存储结构设置在堆叠结构与通道层之间。第二介电层设置在通道层与导体柱之间。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第一导体层的材料例如是金属或掺杂多晶硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第一介电层的材料例如是氧化硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,导体柱的材料例如是金属或掺杂多晶硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,通道层还可设置在导体柱与基底之间。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,通道层的材料例如是多晶硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,电荷存储结构可包括电荷存储层、第三介电层与第四介电层。电荷存储层设置在堆叠结构与通道层之间。第三介电层设置在堆叠结构与电荷存储层之间。第四介电层设置在电荷存储层与通道层之间。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,电荷存储层例如是电荷捕捉层。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,电荷存储层的材料例如是氮化硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第三介电层与第四介电层的材料例如是氧化硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第二介电层的材料例如是氧化硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,还可包括半导体层。半导体层设置在通道层与基底之间。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,半导体层的材料例如是外延硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,还可包括第二导体层。第二导体层设置在最上层的第一导体层上方,且连接于通道层。第二导体层与最上层的第一导体层可彼此隔离。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第一介电层可设置在第二导体层与最上层的第一导体层之间。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第二导体层的材料例如是掺杂多晶硅。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,还可包括接触窗。接触窗电连接于第二导体层。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,还可包括接垫(pad)。接垫设置在导体柱上。接垫与通道层彼此隔离。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,第二介电层还可设置在接垫与通道层之间。
依照本发明的一实施例所述,在上述非挥发性存储器结构中,还可包括接触窗。接触窗电连接于接垫。
基于上述,在本发明所提出的非挥发性存储器结构中,由于导体柱可作为背部电极(back side electrode)使用,因此可有效地提升非挥发性存储器的电性效能及可靠度。举例来说,导体柱可降低随机电报噪声(random telegraph noise,RTN)且可提升电子迁移率(electron mobility)。此外,在进行抹除操作时,可通过导体柱作来提升抹除均匀性(erase uniformity)。另外,导体柱可具有快速电子释放(quick electron detrapping,QED)的功能,由此可提升数据保存能力(data retention capacity)。另一方面,通过导体柱可防止编程干扰的问题。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附的附图作详细说明如下。
附图说明
图1为本发明一实施例的非挥发性存储器结构的剖视图;
图2为图1的局部立体示意图;
图3为沿着图2中的I-I’剖面线的剖视图。
符号说明
10:非挥发性存储器结构
100:基底
102:导体柱
104:通道层
106:电荷存储结构
108、114、118、120、124、128:介电层
110:开口
112、126:导体层
116:电荷存储层
122:半导体层
130、134:接触窗
132:接垫
SS:堆叠结构
具体实施方式
图1为本发明一实施例的非挥发性存储器结构的剖视图。图2为图1的局部立体示意图。图3为沿着图2中的I-I’剖面线的剖视图。
请参照图1至图3,非挥发性存储器结构10包括基底100、堆叠结构SS、导体柱102、通道层104、电荷存储结构106与介电层108。非挥发性存储器结构10例如是具有垂直通道的三维反极栅闪存存储器(3D NAND flash memory)。基底100可为半导体基底,如硅基底。此外,依据产品设计需求,可于基底100中形成所需的掺杂区(未示出)。
堆叠结构SS设置在基底100上,且具有开口110。开口110可暴露出基底100。在本实施例中,开口110可延伸至基底100中,但本发明并不以此为限。在其他实施例中,开口110可仅暴露出基底100,而不延伸至基底100中。堆叠结构SS包括交替堆叠的多个导体层112与多个介电层114。在堆叠设置的多个导体层112中,最上层与最下层的导体层112分别可作为选择栅极使用,且其余的导体层112可作为控制栅极使用,但本发明并不以此为限。导体层112的材料例如是金属或掺杂多晶硅,其中金属例如是钨、铜或铝。此外,在导体层112的材料为金属的情况下,非挥发性存储器结构10还可包括设置在导体层112与电荷存储结构106之间以及导体层112与介电层114之间的阻障层(未示出)。另外,介电层114可设置在最下层的导体层112与基底100之间,以隔离最下层的导体层112与基底100,但本发明并不以此为限。介电层114的材料例如是氧化硅。
导体柱102设置在开口110中。导体柱102可作为背部电极使用。导体柱102的材料例如是金属或掺杂多晶硅,其中金属例如是钨、铜或铝。当导体柱102的材料为金属时,导体柱102可帮助散热,由此可改善因过热而导致的数据保存能力变差的问题。
通道层104设置在堆叠结构SS与导体柱102之间。此外,通道层104还可设置在导体柱102与基底100之间。通道层104的材料例如是多晶硅。
电荷存储结构106设置在堆叠结构SS与通道层104之间。电荷存储结构106可包括电荷存储层116、介电层118与介电层120。电荷存储层116设置在堆叠结构SS与通道层104之间。电荷存储层116例如是电荷捕捉层。电荷存储层116的材料例如是氮化硅。介电层118设置在堆叠结构SS与电荷存储层116之间。介电层118可作为阻挡层(block layer)使用。介电层118的材料例如是氧化硅。介电层120设置在电荷存储层116与通道层104之间。介电层120可作为穿隧介电层使用。介电层120的材料例如是氧化硅。
介电层108设置在通道层104与导体柱102之间。介电层108的材料例如是氧化硅。
非挥发性存储器结构10还可包括半导体层122、介电层124、导体层126、介电层128、接触窗130、接垫132与接触窗134中的至少一者。
半导体层122设置在通道层104与基底100之间。通道层104可连接半导体层122。在其他实施例中,非挥发性存储器结构10可不包括半导体层,且通道层104可直接连接于基底100。半导体层122的材料例如是外延硅。介电层124设置在半导体层122与最下层的导体层112之间。介电层124的材料例如是氧化硅。
导体层126设置在最上层的导体层112上方,且连接于通道层104。导体层126可作为位线接垫(bit line pad)使用。导体层126与最上层的导体层112可彼此隔离。举例来说,介电层114可设置在导体层126与最上层的导体层112之间,以隔离导体层126与最上层的导体层112,但本发明并不以此为限。在本实施例中,如图1所示,导体层126位在通道层104的一侧的侧壁上,亦即导体层126位在通道层104的部分侧壁上,但本发明并不以此为限。在其他实施例中,导体层126可环绕通道层104的整个侧壁。导体层126的材料例如是掺杂多晶硅。
介电层128设置在堆叠结构SS上,且覆盖导体层126。介电层128可为单层结构或多层结构。介电层128的材料例如是氧化硅、氮化硅或其组合。
接触窗130电连接于导体层126。在本实施例中,接触窗130可设置在介电层128中。接触窗130的材料例如是钨。在本实施例中,通道层104可通过导体层126与接触窗130耦接至位线(未示出),但本发明并不以此为限。
接垫132设置在导体柱102上。在本实施例中,接垫132可设置在介电层128中。接垫132与通道层104彼此隔离。举例来说,介电层108还可设置在接垫132与通道层104之间,以隔离接垫132与通道层104,但本发明并不以此为限。接垫132的材料例如是铜、铝或钨。
接触窗134电连接于接垫132。在本实施例中,接触窗134可设置在介电层128中。接触窗134的材料例如是钨。
非挥发性存储器结构10还可包括所属技术领域具有通常知识者所周知的其他构件(如,位线与源极线),在此省略其说明。
基于上述实施例可知,在非挥发性存储器结构10中,由于导体柱102可作为背部电极使用,因此可有效地提升非挥发性存储器的电性效能及可靠度。举例来说,导体柱102可降低随机电报噪声(RTN)且可提升电子迁移率。此外,在进行抹除操作时,可通过导体柱102作来提升抹除均匀性。另外,导体柱102可具有快速电子释放(QED)的功能,由此可提升数据保存能力。另一方面,通过导体柱102可防止编程干扰的问题。
综上所述,上述实施例的非挥发性存储器结构可通过导体柱(内部电极)来有效地提升非挥发性存储器的电性效能及可靠度。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (20)
1.一种非挥发性存储器结构,其特征在于,包括:
基底;
堆叠结构,设置在所述基底上,且具有开口,其中所述堆叠结构包括交替堆叠的多个第一导体层与多个第一介电层;
导体柱,设置在所述开口中;
通道层,设置在所述堆叠结构与所述导体柱之间;
电荷存储结构,设置在所述堆叠结构与所述通道层之间;以及
第二介电层,设置在所述通道层与所述导体柱之间。
2.如权利要求1所述的非挥发性存储器结构,其中所述多个第一导体层的材料包括金属或掺杂多晶硅。
3.如权利要求1所述的非挥发性存储器结构,其中所述多个第一介电层的材料包括氧化硅。
4.如权利要求1所述的非挥发性存储器结构,其中所述导体柱的材料包括金属或掺杂多晶硅。
5.如权利要求1所述的非挥发性存储器结构,其中所述通道层还可设置在所述导体柱与所述基底之间。
6.如权利要求1所述的非挥发性存储器结构,其中所述通道层的材料包括多晶硅。
7.如权利要求1所述的非挥发性存储器结构,其中所述电荷存储结构包括:
电荷存储层,设置在所述堆叠结构与所述通道层之间;
第三介电层,设置在所述堆叠结构与所述电荷存储层之间;以及
第四介电层,设置在所述电荷存储层与所述通道层之间。
8.如权利要求7所述的非挥发性存储器结构,其中所述电荷存储层包括电荷捕捉层。
9.如权利要求7所述的非挥发性存储器结构,其中所述电荷存储层的材料包括氮化硅。
10.如权利要求7所述的非挥发性存储器结构,其中所述第三介电层与所述第四介电层的材料包括氧化硅。
11.如权利要求1所述的非挥发性存储器结构,其中所述第二介电层的材料包括氧化硅。
12.如权利要求1所述的非挥发性存储器结构,还包括:
半导体层,设置在所述通道层与所述基底之间。
13.如权利要求12所述的非挥发性存储器结构,其中所述半导体层的材料包括外延硅。
14.如权利要求1所述的非挥发性存储器结构,还包括:
第二导体层,设置在最上层的所述第一导体层上方,且连接于所述通道层,其中所述第二导体层与最上层的所述第一导体层彼此隔离。
15.如权利要求14所述的非挥发性存储器结构,其中所述第一介电层设置在所述第二导体层与最上层的所述第一导体层之间。
16.如权利要求14所述的非挥发性存储器结构,其中所述第二导体层的材料包括掺杂多晶硅。
17.如权利要求14所述的非挥发性存储器结构,还包括:
接触窗,电连接于所述第二导体层。
18.如权利要求1所述的非挥发性存储器结构,还包括:
接垫,设置在所述导体柱上,且与所述通道层彼此隔离。
19.如权利要求18所述的非挥发性存储器结构,其中所述第二介电层还设置在所述接垫与所述通道层之间。
20.如权利要求18所述的非挥发性存储器结构,还包括:
接触窗,电连接于所述接垫。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200701440A (en) * | 2005-06-27 | 2007-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
US20090242968A1 (en) * | 2008-03-26 | 2009-10-01 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing same |
US20140061776A1 (en) * | 2012-08-31 | 2014-03-06 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
KR101450008B1 (ko) * | 2013-05-21 | 2014-10-15 | 한국과학기술원 | 3차원 구조의 비휘발성 메모리 소자의 제조방법 |
CN106684090A (zh) * | 2017-01-26 | 2017-05-17 | 合肥兆芯电子有限公司 | 三维非易失性存储器结构及其制造方法 |
US10229931B1 (en) * | 2017-12-05 | 2019-03-12 | Sandisk Technologies Llc | Three-dimensional memory device containing fluorine-free tungsten—word lines and methods of manufacturing the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130037062A (ko) * | 2011-10-05 | 2013-04-15 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 소자 및 캐패시터 |
US9419135B2 (en) * | 2014-11-13 | 2016-08-16 | Sandisk Technologies Llc | Three dimensional NAND device having reduced wafer bowing and method of making thereof |
US10014311B2 (en) * | 2016-10-17 | 2018-07-03 | Micron Technology, Inc. | Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon |
US10403637B2 (en) * | 2017-01-20 | 2019-09-03 | Macronix International Co., Ltd. | Discrete charge trapping elements for 3D NAND architecture |
US10312239B2 (en) * | 2017-03-16 | 2019-06-04 | Toshiba Memory Corporation | Semiconductor memory including semiconductor oxie |
JP6563988B2 (ja) * | 2017-08-24 | 2019-08-21 | ウィンボンド エレクトロニクス コーポレーション | 不揮発性半導体記憶装置 |
US10304852B1 (en) * | 2018-02-15 | 2019-05-28 | Sandisk Technologies Llc | Three-dimensional memory device containing through-memory-level contact via structures |
US10903230B2 (en) * | 2018-02-15 | 2021-01-26 | Sandisk Technologies Llc | Three-dimensional memory device containing through-memory-level contact via structures and method of making the same |
CN109712980B (zh) * | 2018-11-21 | 2023-08-08 | 长江存储科技有限责任公司 | 3d存储器件的制造方法及3d存储器件 |
US11107901B2 (en) * | 2019-04-03 | 2021-08-31 | Sandisk Technologies Llc | Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same |
-
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- 2019-05-15 TW TW108116754A patent/TWI685949B/zh active
- 2019-05-28 CN CN201910449969.XA patent/CN111952314A/zh active Pending
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200701440A (en) * | 2005-06-27 | 2007-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
US20090242968A1 (en) * | 2008-03-26 | 2009-10-01 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for manufacturing same |
US20140061776A1 (en) * | 2012-08-31 | 2014-03-06 | SK Hynix Inc. | Semiconductor device and method of manufacturing the same |
KR101450008B1 (ko) * | 2013-05-21 | 2014-10-15 | 한국과학기술원 | 3차원 구조의 비휘발성 메모리 소자의 제조방법 |
CN106684090A (zh) * | 2017-01-26 | 2017-05-17 | 合肥兆芯电子有限公司 | 三维非易失性存储器结构及其制造方法 |
US10229931B1 (en) * | 2017-12-05 | 2019-03-12 | Sandisk Technologies Llc | Three-dimensional memory device containing fluorine-free tungsten—word lines and methods of manufacturing the same |
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