CN111883584A - 沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法 - Google Patents

沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法 Download PDF

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CN111883584A
CN111883584A CN202010783147.8A CN202010783147A CN111883584A CN 111883584 A CN111883584 A CN 111883584A CN 202010783147 A CN202010783147 A CN 202010783147A CN 111883584 A CN111883584 A CN 111883584A
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卢烁今
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Suzhou Huatai Electronics Co Ltd
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Abstract

本发明公开了一种沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法。所述沟槽栅功率器件包括半导体基材和栅极，所述半导体基材内分布有至少一个沟槽，所述栅极设置在所述沟槽内，所述沟槽内壁与栅极之间设置有栅介质层，并且在所述沟槽的深度方向上，所述栅极的顶端低于所述沟槽的槽口。本发明提供的沟槽栅功率器件，在所述沟槽的深度方向上，栅极的顶端比沟槽的槽口低0.1‑0.2μm，在测试栅极击穿电压时，沟槽的上边缘(即槽口位置处)的栅介质层两边不会施加电压，使得击穿转而在其他质量更好的栅介质层位置处发生，从而使实际的栅极击穿电压会得到提高。

Description

沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法
技术领域
本发明涉及一种沟槽栅功率器件，特别涉及一种沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法，属于半导体技术领域。
背景技术
本申请人所知的一种沟槽栅功率器件(包括IGBT和VDMOS)的结构如图1a所示，沟槽栅功率器件栅极的制作流程如图1b所示，其主要包括先在硅片1上刻蚀出沟槽2；在所述沟槽2内壁上形成牺牲氧化层3；刻蚀除去牺牲氧化层3；在沟槽2内生长栅介质层4；在沟槽2内淀积多晶硅5；刻蚀多晶硅5和栅介质层4，刻蚀完成后，硅片1上表面以上的多晶硅5和栅介质层4都被刻蚀掉，沟槽2内的多晶硅5中间低、边缘高，靠近沟槽2边缘的多晶硅5上表面与沟槽2的边缘(也就是硅片的上表面)平齐。
然而，采用该工艺，在生长栅介质层时，沟槽的顶端附近由于有两个方向的栅介质层生长，在这个区域的栅介质层由于挤压效应，导致质量较差，在测试栅极击穿电压时，这里会首先发生击穿，从而拉低测试出的栅极击穿电压。
发明内容
针对现有技术的不足，本发明的主要目的在于提供一种沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法，以克服现有技术中的不足。
为实现前述发明目的，本发明采用的技术方案包括：
本发明实施例一方面提供了一种沟槽栅功率器件，其包括半导体基材和栅极，所述半导体基材内分布有至少一个沟槽，所述栅极设置在所述沟槽内，所述沟槽内壁与栅极之间设置有栅介质层，并且在所述沟槽的深度方向上，所述栅极的顶端低于所述沟槽的槽口。
进一步的，在沿所述沟槽的深度方向上，所述栅极的顶端比所述沟槽的槽口低0.1-0.2μm。
本发明实施例还提供了一种提高沟槽栅功率器件栅极击穿电压的方法，其包括：
提供半导体基材，并在所述半导体基材内加工形成至少一个沟槽；
在所述沟槽的内壁形成栅介质层，
在所述沟槽内形成栅极，并使所述栅极的顶端在所述沟槽的深度方向上低于所述沟槽的槽口。
与现有技术相比，本发明实施例提供的一种沟槽栅功率器件，在所述沟槽的深度方向上，栅极的顶端比沟槽的槽口低0.1-0.2μm，在测试栅极击穿电压时，沟槽的上边缘(即槽口位置，下同)的栅介质层两边不会施加电压，也就不会发生击穿，使得击穿转而在其他质量更好的栅介质层位置处发生，从而使实际的栅极击穿电压会得到提高。
附图说明
图1a是现有一种沟槽栅功率器件的结构示意图；
图1b是现有一种沟槽栅功率器件的栅极的制作流程结构示意图；
图2是本发明一典型实施案例中提供的一种沟槽栅功率器件的结构示意图；
图3本发明一典型实施案例中提供的一种沟槽栅功率器件的栅极的制作流程示意图；
图4本发明一典型实施案例中提供的一种沟槽栅功率器件的栅极的制作流程结构示意图。
具体实施方式
鉴于现有技术中的不足，本案发明人经长期研究和大量实践，得以提出本发明的技术方案。如下将对该技术方案、其实施过程及原理等作进一步的解释说明。
IGBT：Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管
VDMOSFET：Vertical Diffused Metal-Oxide-Semiconductor Field-EffectTransistor，垂直扩散金属氧化物半导体场效应晶体管
为了克服现有技术中的缺陷，本发明实施例一方面提供了一种沟槽栅功率器件，其包括半导体基材和栅极，所述半导体基材内分布有至少一个沟槽，所述栅极设置在所述沟槽内，所述沟槽内壁与栅极之间设置有栅介质层，并且在所述沟槽的深度方向上，所述栅极的顶端低于所述沟槽的槽口。
进一步的，所述栅极的顶端比所述沟槽的槽口低0.1-0.2μm。
进一步的，在所述沟槽的深度方向上，所述栅极顶部的周缘部高于中心部。
进一步的，所述栅介质层将所述沟槽内壁完全覆盖。
进一步的，所述栅介质层的顶端与所述沟槽的槽口平齐。
进一步的，所述栅介质层的材质为氧化硅，所述栅介质层的厚度为
Figure BDA0002620944760000031
进一步的，所述栅极的材质包括多晶硅。
进一步的，所述半导体基材内还分布有漂移区、体区、阱区、源区和漏区，所述源区、漏区分别与源极、漏极配合。
本发明实施例另一方面提供了一种提高沟槽栅功率器件栅极击穿电压的方法，其包括：
提供半导体基材，并在所述半导体基材内加工形成至少一个沟槽；
在所述沟槽的内壁形成栅介质层，
在所述沟槽内形成栅极，并使所述栅极的顶端在所述沟槽的深度方向上低于所述沟槽的槽口。
进一步的，所述的方法具体包括：在所述沟槽内填充多晶硅作为栅极，并采用刻蚀的方式对所述多晶硅的顶部进行加工处理，以使所述栅极顶部的周缘部在所述沟槽的深度方向上高于中心部；并使所述多晶硅的顶端在所述沟槽的深度方向上低于所述沟槽的槽口。
进一步的，所述栅极的顶端比所述沟槽的槽口低0.1-0.2μm。
进一步的，所述的方法具体包括：
提供半导体基材，并在所述半导体基材内加工形成至少一个沟槽；
至少在所述沟槽的内壁上形成牺牲氧化层，以消除所述沟槽表面的缺陷；
除去所述的牺牲氧化层，并至少在所述沟槽的内壁上形成栅介质层，并使所述栅介质层的顶端与所述沟槽的槽口平齐；
在所述沟槽内填充多晶硅作为栅极；
采用刻蚀的方式对所述多晶硅的顶部进行加工处理，以使所述栅极顶部的周缘部在所述沟槽的深度方向上高于中心部；并使所述多晶硅的顶端在所述沟槽的深度方向上低于所述沟槽的槽口。
如下将结合附图对该技术方案、其实施过程及原理等作进一步的解释说明，需要说明的是，本发明实施例中所采用刻蚀、淀积等工艺均为本领域技术人员已知的现有工艺，其中的具体工艺参数可以根据具体情况进行调整。
实施例1
请参阅图2，一种沟槽栅功率器件，其包括半导体基材(本发明实施例采用硅片作为半导体基材，下同)1和栅极(本发明实施例采用多晶硅作为栅极，下同)5，所述半导体基材1内分布有至少一个沟槽2，所述栅极5设置在所述沟槽2内，所述沟槽2内壁与栅极5之间设置有栅介质层4，并且在所述沟槽的深度方向上，所述栅极5的顶端51比所述沟槽2的槽口21低0.1-0.2μm。
具体的，在所述沟槽的深度方向上，所述栅极5顶部的周缘部高于中心部，以及，所述栅介质层4将所述沟槽2内壁完全覆盖，且所述栅介质层4的顶端与所述沟槽2的槽口平齐，即至少栅介质层4的局部分布在所述栅极5的顶端51与沟槽2的槽口21之间。
当然，该一种沟槽栅功率器件，例如包括IGBT器件和VDMOS器件还包括诸如阱区、漂移区、体区、源区、漏区、源极、漏极等结构，阱区、漂移区、体区、源区、漏区、源极、漏极等结构的厚度、掺杂类型和掺杂浓度等均可以采用本领域技术人员已知的特征参数，在此不再赘述。
请参阅图3和图4，一种提高沟槽栅功率器件栅极击穿电压的方法，其包括：
提供半导体基材1，并在所述半导体基材1内加工形成至少一个沟槽2；
至少在所述沟槽2的内壁上形成牺牲氧化层3，之后再除去所述的牺牲氧化层3，沟槽2的侧壁有缺陷，通过先形成牺牲氧化层3氧化再去除的方式，可以消除这些缺陷；
至少在所述沟槽2的内壁上形成栅介质层4；
在所述沟槽2内填充多晶硅5；
采用刻蚀的方式除去位于半导体基材1表面以上多余的多晶硅5和栅介质层4，且使所述栅介质层4的顶端与所述沟槽2的槽口平齐；
采用刻蚀的方式对所述多晶硅5的顶部进行加工处理，以使在所述沟槽的深度方向上，所述多晶硅5顶部的周缘部高于中心部(即中间低、边缘高)，并使多晶硅5的顶端在所述沟槽的深度方向上比所述沟槽的槽口低0.15μm。
对比例1
对比例1中的一种沟槽栅功率器件如图1a所示，其包括半导体基材1和栅极5，所述半导体基材1内分布有至少一个沟槽2，所述栅极5设置在所述沟槽2内，所述栅极5与沟槽2之间还形成有栅介质层4，其中，所述沟槽的槽口与栅极5的顶部齐平。
实施例1和对比例1中沟槽栅功率器件的栅介质层的厚度均为
Figure BDA0002620944760000051
分别对实施例1和对比例1中的沟槽栅功率器件进行击穿电压测试，对比例1中沟槽栅功率器件的栅极击穿电压是43V，实施例1中的沟槽栅功率器件的栅极击穿电压是75V。
本发明实施例提供的一种沟槽栅功率器件，所述沟槽的深度方向上，栅极的顶端比沟槽的槽口低0.1-0.2μm，在测试栅极击穿电压时，沟槽的上边缘(即槽口位置处)的栅介质层两边不会施加电压，也就不会发生击穿，使得击穿转而在其他质量更好的栅介质层位置处发生，从而使实际的栅极击穿电压会得到提高。
应当理解，上述实施例仅为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (10)

1.一种沟槽栅功率器件，其特征在于包括半导体基材和栅极，所述半导体基材内分布有至少一个沟槽，所述栅极设置在所述沟槽内，所述沟槽内壁与栅极之间设置有栅介质层，并且在所述沟槽的深度方向上，所述栅极的顶端低于所述沟槽的槽口。
2.根据权利要求1所述的沟槽栅功率器件，其特征在于：所述栅极的顶端比所述沟槽的槽口低0.1-0.2μm。
3.根据权利要求1所述的沟槽栅功率器件，其特征在于：在所述沟槽的深度方向上，所述栅极顶部的周缘部高于中心部。
4.根据权利要求1所述的沟槽栅功率器件，其特征在于：所述栅介质层将所述沟槽内壁完全覆盖。
5.根据权利要求1所述的沟槽栅功率器件，其特征在于：所述栅介质层的顶端与所述沟槽的槽口平齐。
6.根据权利要求1所述的沟槽栅功率器件，其特征在于：所述栅介质层的材质为氧化硅，所述栅介质层的厚度为
Figure FDA0002620944750000011
优选的，所述栅极的材质包括多晶硅。
7.根据权利要求1所述的沟槽栅功率器件，其特征在于：所述半导体基材内还分布有漂移区、体区、阱区、源区和漏区，所述源区、漏区分别与源极、漏极配合。
8.一种提高沟槽栅功率器件栅极击穿电压的方法，其特征在于包括：
提供半导体基材，并在所述半导体基材内加工形成至少一个沟槽；
在所述沟槽的内壁形成栅介质层，
在所述沟槽内形成栅极，并使所述栅极的顶端在所述沟槽的深度方向上低于所述沟槽的槽口。
9.根据权利要求8所述的方法，其特征在于具体包括：在所述沟槽内填充多晶硅作为栅极，并采用刻蚀的方式对所述多晶硅的顶部进行加工处理，以使所述栅极顶部的周缘部在所述沟槽的深度方向上高于中心部；并使所述多晶硅的顶端在所述沟槽的深度方向上低于所述沟槽的槽口；优选的，所述栅极的顶端比所述沟槽的槽口低0.1-0.2μm。
10.根据权利要求9所述的方法，其特征在于具体包括：
提供半导体基材，并在所述半导体基材内加工形成至少一个沟槽；
至少在所述沟槽的内壁上形成牺牲氧化层，以消除所述沟槽表面的缺陷；
除去所述的牺牲氧化层，并至少在所述沟槽的内壁上形成栅介质层，并使所述栅介质层的顶端与所述沟槽的槽口平齐；
在所述沟槽内填充多晶硅作为栅极；
采用刻蚀的方式对所述多晶硅的顶部进行加工处理，以使所述栅极顶部的周缘部在所述沟槽的深度方向上高于中心部；并使所述多晶硅的顶端在所述沟槽的深度方向上低于所述沟槽的槽口。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6351009B1 (en) * 1999-03-01 2002-02-26 Fairchild Semiconductor Corporation MOS-gated device having a buried gate and process for forming same
US20100090274A1 (en) * 2008-10-10 2010-04-15 Force Mos Technology Co. Ltd. Trench mosfet with shallow trench contact
CN102315264A (zh) * 2010-07-09 2012-01-11 苏州东微半导体有限公司 一种使用球形沟槽的功率器件及其制造方法
WO2012165329A1 (ja) * 2011-05-27 2012-12-06 新電元工業株式会社 トレンチゲートパワー半導体装置及びその製造方法
CN104103694A (zh) * 2014-07-25 2014-10-15 苏州东微半导体有限公司 一种沟槽型绝缘栅场效应晶体管及其制造方法
US20150349091A1 (en) * 2014-05-31 2015-12-03 Hamza Yilmaz Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
CN105529273A (zh) * 2016-01-15 2016-04-27 上海华虹宏力半导体制造有限公司 沟槽栅功率器件的制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6351009B1 (en) * 1999-03-01 2002-02-26 Fairchild Semiconductor Corporation MOS-gated device having a buried gate and process for forming same
US20100090274A1 (en) * 2008-10-10 2010-04-15 Force Mos Technology Co. Ltd. Trench mosfet with shallow trench contact
CN102315264A (zh) * 2010-07-09 2012-01-11 苏州东微半导体有限公司 一种使用球形沟槽的功率器件及其制造方法
WO2012165329A1 (ja) * 2011-05-27 2012-12-06 新電元工業株式会社 トレンチゲートパワー半導体装置及びその製造方法
US20150349091A1 (en) * 2014-05-31 2015-12-03 Hamza Yilmaz Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
CN104103694A (zh) * 2014-07-25 2014-10-15 苏州东微半导体有限公司 一种沟槽型绝缘栅场效应晶体管及其制造方法
CN105529273A (zh) * 2016-01-15 2016-04-27 上海华虹宏力半导体制造有限公司 沟槽栅功率器件的制造方法

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