CN111863749A - 一种具备微流道散热功能的扇出型器件及其制作方法 - Google Patents
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- 230000017525 heat dissipation Effects 0.000 title claims abstract description 29
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- 239000000853 adhesive Substances 0.000 claims abstract description 14
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
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- 239000010931 gold Substances 0.000 claims description 4
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 4
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
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- 238000003892 spreading Methods 0.000 claims 2
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 9
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- 238000004132 cross linking Methods 0.000 description 2
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- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005057 refrigeration Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
本发明公开一种具备微流道散热功能的扇出型器件及其制作方法,属于集成电路封装技术领域。扇出型器件包括粘接体和联接体,粘接体包括微流道和与其通过粘接层连接的有源芯片;联接体设置在所述粘接体四周,与所述粘接体形成扇出体。本发明将微流道与有源芯片通过联接体形成内部嵌入微流道结构的扇出型器件,弥补扇出型器件受传统散热能力限制的不足,赋予扇出型器件的主动散热能力,有效提升扇出型器件的散热水平,可满足高功率密度的扇出型器件的应用需求;将预制的微流道贴装于测试良好的有源芯片背面,通过联接体形成扇出体,可提高封装良率,结构紧凑,安全可靠。
Description
技术领域
本发明涉及集成电路封装技术领域,特别涉及一种具备微流道散热功能的扇出型器件及其制作方法。
背景技术
针对电子产品向小型化、高性能、高可靠的方向趋势,系统集成度也日益提高。在这种情况下,靠进一步缩小集成电路的特征尺寸和互连线的线宽来提高性能的方式受到材料物理特性和设备工艺的限制,传统的摩尔定律已经很难继续发展下去。扇出型封装技术无需LTCC载板,可以减重约40%以上;且晶圆级集成可实现微米级尺度的制造精度,互连延迟和损耗降低,同时提高生产效率,已成为实现电子系统元器件高集成度、小型化和低成本应用的有效途径,目前正在发展成为集成灵活性高的主要先进封装技术。
随着扇出型封装器件集成度的增加、功耗的上升和尺寸的减小,快速增加的系统发热已经成为扇出型封装技术研发和应用中的一项重大挑战。一般地,元器件的失效率随着器件温度的上升呈指数规律上升,器件在70~80℃水平上每升高1℃,其可靠性降低5%。当器件的功率密度高于100W/cm2时,常规散热方式如热传导、对流、热点制冷等根本无法满足散热需求。所以为了满足高功率密度的单片级/系统级扇出型封装器件研制需求,亟需开发一种具备微流道散热功能的扇出型器件。
发明内容
本发明的目的在于提供一种具备微流道散热功能的扇出型器件及其制作方法,以解决现有的扇出型封装器件散热效果差的问题。
为解决上述技术问题,本发明提供一种具备微流道散热功能的扇出型器件,包括:
粘接体,所述粘接体包括微流道和与其通过粘接层连接的有源芯片;
联接体,设置在所述粘接体四周,与所述粘接体形成扇出体。
可选的,所述微流道包括微流道凹槽和微流体出入口,所述微流道凹槽和所述微流体出入口连接形成所述微流道。
可选的,所述微流道凹槽的结构包括直线型、S型和折线型。
可选的,所述有源芯片的正面制作有再布线层,所述再布线层覆盖所述扇出体的表面,并于所述有源芯片电连接。
可选的,所述再布线层上制作有阵列凸点,所述阵列凸点与所述再布线层电连接。
可选的,所述阵列凸点的大小根据所述再布线层表面焊盘的直径和节距而定;所述阵列凸点的材料包括铜、锡铅、锡银和锡银铜。
可选的,所述粘接层的材料包括金、金锡和有机树脂。
可选的,所述联接体的厚度不低于所述粘接体的厚度。
本发明还提供了一种具备微流道散热功能的扇出型器件的制备方法,包括:
提供基板,在基板上制作所需结构、深宽比的微流道凹槽,所述微流道凹槽的深度不超过基板的厚度;
重新提供基板,在该基板上制作所需尺寸的微流体出入口,所述微流道出入口的深度不超过该基板的厚度;
将所述微流道凹槽和所述微流道出入口进行连接,通过划片工艺截取得到独立的微流道;
提供有源芯片,将微流道通过粘接层连接在所述有源芯片的背面,得到粘接体;
在所述粘接体周围通过交联联接体形成扇出体,使所述有源芯片的正面暴露在外,所述联接体的厚度不低于所述粘接体;
在有源芯片的正面制作再布线层,所述再布线层覆盖所述扇出体的表面并于所述有源芯片电连接;
在所述再布线层上制作阵列凸点,该阵列凸点与再布线层电连接;
减薄扇出体表面的联接体直至露出微流体出入口,得到独立的扇出型器件。
在本发明中提供了一种具备微流道散热功能的扇出型器件及其制作方法,扇出型器件包括粘接体和联接体,粘接体包括微流道和与其通过粘接层连接的有源芯片;联接体设置在所述粘接体四周,与所述粘接体形成扇出体。本发明将微流道与有源芯片通过联接体形成内部嵌入微流道结构的扇出型器件,弥补扇出型器件受传统散热能力限制的不足,赋予扇出型器件的主动散热能力,有效提升扇出型器件的散热水平,可满足高功率密度的扇出型器件的应用需求;将预制的微流道贴装于测试良好的有源芯片背面,通过联接体形成扇出体,可提高封装良率,结构紧凑,安全可靠。
附图说明
图1是本发明提供的具备微流道散热功能的扇出型器件结构示意图;
图2是利用基板制备得到微流道凹槽的示意图;
图3是利用基板制备得到微流体出入口的示意图;
图4是将微流道凹槽和微流体出入口粘接得到微流道的示意图;
图5是将微流道与有源芯片连接得到粘接体的示意图;
图6是通过粘接体四周交联得到扇出体的示意图;
图7是在扇出体表面制作再布线层的示意图;
图8是在再布线层上制作阵列凸点的示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的一种具备微流道散热功能的扇出型器件及其制作方法作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
本发明提供了一种具备微流道散热功能的扇出型器件,如图1所示,该扇出型器件1包括粘接体和联接体。所述粘接体包括微流道和与其通过粘接层4连接的有源芯片2,所述有源芯片2的类型包括数/模、高频、功率等芯片;所述粘接层4的材料为金、金锡、有机树脂或其他材料。所述微流道包括微流道凹槽11和微流体出入口10,所述微流道凹槽11和所述微流体出入口10连接形成所述微流道。所述微流道凹槽11的结构包括直线型、S型和折线型。所述联接体6设置在所述粘接体四周,与所述粘接体形成扇出体,所述联接体6的厚度不低于所述粘接体的厚度。
所述有源芯片2的正面制作有再布线层8,所述再布线层8覆盖所述扇出体的表面,并于所述有源芯片2电连接。所述再布线层8上制作有阵列凸点9,所述阵列凸点9与所述再布线层8电连接。其中所述阵列凸点9的大小根据所述再布线层8表面焊盘的直径和节距而定;所述阵列凸点9的材料为铜、锡铅、锡银以及锡银铜等材料。
本实施例一的扇出型器件通过具有高效主动散热功能的微流道3埋入在扇出型器件1内,有效增加了扇出型器件1的散热能力,从而满足高功率密度单片级/系统级扇出型器件的散热需求。
实施例二
本发明提供了一种具备微流道散热功能的扇出型器件的制备方法,包括如下步骤:
提供基板12,所述基板12的材料为硅或玻璃等材料,在基板12上采用常规刻蚀工艺制作所需结构、深宽比的微流道凹槽11,如图2所示;所述微流道凹槽11的深度不超过基板12的厚度;所述微流道凹槽11的结构根据产品散热需求而定,所述微流道凹槽11的结构可以为直线型、S型、折线型等结构;
重新提供基板12,在该基板12上制作所需尺寸的微流体出入口10,如图3所示,所述微流道出入口10的深度不超过该基板12的厚度;
通过热压焊、回流焊等连接工艺,将所述微流道凹槽11和所述微流道出入口10进行连接,通过划片工艺截取得到独立的微流道3,如图4所示;
提供有源芯片2,通过热压焊、回流焊、胶接等连接工艺,将微流道3通过粘接层4连接在所述有源芯片2的背面,得到如图5所示的粘接体5;所述粘接层4的材料包括金、金锡、有机树脂等材料;
通过临时键合/解键合、压缩成型等工艺,在如图5所示的所述粘接体5周围通过交联联接体6形成扇出体7,使所述有源芯片2的正面暴露在外,如图6所示,所述联接体6的厚度不低于所述粘接体5;
通过溅射、光刻、电镀等工艺,在所述有源芯片2的正面制作再布线层8,如图7所示,所述再布线层8覆盖所述扇出体7的表面并于所述有源芯片2电连接;
通过电镀、植球等工艺,在所述再布线层8上制作阵列凸点9,该阵列凸点9与再布线层8电连接,如图8所示;所述阵列凸点9的大小根据再布线层8表面焊盘的直径和节距而定,所述阵列凸点9的材料可以为铜、锡铅、锡银以及锡银铜等材料;
通过标准减划工艺,减薄扇出体7表面的联接体6,直至露出微流体出入口10,得到如图1所示独立的扇出型器件1。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (9)
1.一种具备微流道散热功能的扇出型器件,其特征在于,包括:
粘接体,所述粘接体包括微流道和与其通过粘接层连接的有源芯片;
联接体,设置在所述粘接体四周,与所述粘接体形成扇出体。
2.如权利要求1所述的具备微流道散热功能的扇出型器件,其特征在于,所述微流道包括微流道凹槽和微流体出入口,所述微流道凹槽和所述微流体出入口连接形成所述微流道。
3.如权利要求2所述的具备微流道散热功能的扇出型器件,其特征在于,所述微流道凹槽的结构包括直线型、S型和折线型。
4.如权利要求1所述的具备微流道散热功能的扇出型器件,其特征在于,所述有源芯片的正面制作有再布线层,所述再布线层覆盖所述扇出体的表面,并于所述有源芯片电连接。
5.如权利要求4所述的具备微流道散热功能的扇出型器件,其特征在于,所述再布线层上制作有阵列凸点,所述阵列凸点与所述再布线层电连接。
6.如权利要求5所述的具备微流道散热功能的扇出型器件,其特征在于,所述阵列凸点的大小根据所述再布线层表面焊盘的直径和节距而定;所述阵列凸点的材料包括铜、锡铅、锡银和锡银铜。
7.如权利要求1所述的具备微流道散热功能的扇出型器件,其特征在于,所述粘接层的材料包括金、金锡和有机树脂。
8.如权利要求1所述的具备微流道散热功能的扇出型器件,其特征在于,所述联接体的厚度不低于所述粘接体的厚度。
9.一种具备微流道散热功能的扇出型器件的制备方法,其特征在于,包括:
提供基板,在基板上制作所需结构、深宽比的微流道凹槽,所述微流道凹槽的深度不超过基板的厚度;
重新提供基板,在该基板上制作所需尺寸的微流体出入口,所述微流道出入口的深度不超过该基板的厚度;
将所述微流道凹槽和所述微流道出入口进行连接,通过划片工艺截取得到独立的微流道;
提供有源芯片,将微流道通过粘接层连接在所述有源芯片的背面,得到粘接体;
在所述粘接体周围通过交联联接体形成扇出体,使所述有源芯片的正面暴露在外,所述联接体的厚度不低于所述粘接体;
在有源芯片的正面制作再布线层,所述再布线层覆盖所述扇出体的表面并于所述有源芯片电连接;
在所述再布线层上制作阵列凸点,该阵列凸点与再布线层电连接;
减薄扇出体表面的联接体直至露出微流体出入口,得到独立的扇出型器件。
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