CN111863743B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN111863743B
CN111863743B CN202010316374.XA CN202010316374A CN111863743B CN 111863743 B CN111863743 B CN 111863743B CN 202010316374 A CN202010316374 A CN 202010316374A CN 111863743 B CN111863743 B CN 111863743B
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width
transistor
portions
diode
region
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CN111863743A (zh
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江口佳佑
米山玲
青木伸亲
日高大树
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

本发明的目的在于，提供对骤回动作进行抑制且散热性优异的半导体装置。半导体装置包含半导体基板、表面电极、外部配线、多个晶体管部及多个二极管部。多个晶体管部和多个二极管部设置于半导体基板，且配置于与半导体基板的表面平行的一个方向。外部配线的接合部与表面电极接合。多个晶体管部和多个二极管部设置于半导体基板的俯视观察时的第1区域和第2区域。晶体管部和二极管部交替地配置于一个方向。第1区域处的第1晶体管宽度和第1二极管宽度比外部配线的接合部的宽度小。第2区域处的第2晶体管宽度和第2二极管宽度比外部配线的接合部的宽度大。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
当前,在半导体装置的领域中，为了对在半导体动作时产生的温度上升进行抑制，进行了半导体元件的薄化等半导体元件的特性的改善。在半导体装置的小型化的发展中，半导体元件的面积缩小化是必须的。但是，随着半导体元件的特性改善接近极限，半导体模块的热设计变得更加严格。
近年来，作为对散热性进行改良的半导体装置，已知如下半导体装置(参照专利文献1)，该半导体装置包含：晶体管部，其包含绝缘栅极双极晶体管(Insulated GateBipolar Transistor，IGBT)；以及二极管部。
专利文献1所示的半导体装置在从基板的表面方向观察的情况下具有晶体管部和二极管部交替地配置的平面形状。另外，半导体装置具有与表面电极接合的外部配线，外部配线和表面电极的接触宽度比晶体管部的宽度及二极管部的宽度的一者大。通过这样的构造，专利文献1的半导体装置减轻了外部配线的接合部的热疲劳，但另一方面，容易引起骤回动作，担心接通电压恶化。
在专利文献2中公开了对骤回动作进行抑制的技术。专利文献2所示的半导体装置具有条形的多个IGBT元件区域和多个二极管元件区域相邻交替地配置的结构。多个IGBT元件区域由该条形的宽度窄的窄条形宽度区域、宽度比该窄条形宽度区域宽的至少1个宽条形宽度区域构成。专利文献2的半导体装置通过宽条形宽度区域对IGBT元件区域的通电开始时的骤回动作进行抑制。但是，在专利文献2中没有考虑二极管元件区域处的通电开始时的骤回动作，担心二极管的接通电压恶化。
专利文献1：国际公开第2018/225571号
专利文献2：日本特开2013-138069号公报
为了对晶体管部的通电开始时的骤回动作进行抑制，晶体管部的背面的p+层的宽度需要比由n-漂移层的电阻率和厚度决定的规定值大。为了对二极管部的通电开始时的骤回动作进行抑制，二极管部的表面的p+层的宽度需要比由n-漂移层的电阻率和厚度决定的规定值大。
这样，为了对骤回动作进行抑制，使用宽度比规定值大的晶体管部及二极管部。另一方面，从散热性的改善的观点出发，使用热量的分散特性良好的宽度小的晶体管部及二极管部。因此，难以实现对骤回动作进行抑制且散热性优异的半导体装置。
发明内容
本发明就是为了解决上述那样的课题而提出的，其目的在于，提供对骤回动作进行抑制且散热性优异的半导体装置。
本发明涉及的半导体装置包含半导体基板、表面电极、外部配线、多个晶体管部、多个二极管部。多个晶体管部和多个二极管部设置于半导体基板，且配置于与半导体基板的表面平行的一个方向。表面电极设置于半导体基板的表面，与多个晶体管部和多个二极管部电连接。外部配线包含与表面电极接合的接合部，外部配线通过接合部与表面电极电连接。多个晶体管部和多个二极管部设置于半导体基板的俯视观察时的第1区域和第2区域。多个晶体管部的每一者和多个二极管部的每一者交替地配置于一个方向。第1区域处的多个晶体管部的每一者的一个方向的宽度即第1晶体管宽度和第1区域处的多个二极管部的每一者的一个方向的宽度即第1二极管宽度比外部配线的接合部的宽度小。第2区域处的多个晶体管部的每一者的一个方向的宽度即第2晶体管宽度和第2区域处的多个二极管部的每一者的一个方向的宽度即第2二极管宽度比外部配线的接合部的宽度大。
发明的效果
根据本发明，能够提供对骤回动作进行抑制且散热性优异的半导体装置。
通过下面的详细的说明和附图，本发明的目的、特征、方案、及优点会变得更加明了。
附图说明
图1是表示实施方式1中的半导体装置的结构的俯视图。
图2是图1所示的A-A’处的剖视图。
图3是表示实施方式2中的半导体装置的结构的俯视图。
图4是表示实施方式3中的半导体装置的结构的俯视图。
图5是表示实施方式4中的半导体装置的结构的俯视图。
图6是表示实施方式5中的半导体装置的结构的俯视图。
图7是表示实施方式6中的半导体装置的结构的俯视图。
标号的说明
10半导体基板，11第1区域，12第2区域，13末端区域，20晶体管部，25边界部，30二极管部，40栅极电极，50表面电极，60外部配线，61接合部，70沟槽栅极，80背面电极，90n-漂移层，100信号配线，110信号配线图案，120主电流配线图案。
具体实施方式
<实施方式1>
图1是表示实施方式1中的半导体装置的结构的俯视图。图2是图1所示的A-A’处的剖视图。
半导体装置由半导体基板10、栅极电极40、表面电极50(在图1中未图示)、外部配线60、多个晶体管部20及多个二极管部30构成。
半导体基板10在俯视观察时具有第1区域11、第2区域12及末端区域13。末端区域13是沿半导体基板10的外周设置的。第1区域11和第2区域12位于末端区域13的内侧，换言之，末端区域13包围第1区域11及第2区域12。另外，在实施方式1中，第1区域11和第2区域12是相邻的。
多个晶体管部20和多个二极管部30如图1所示，配置于第1区域11及第2区域12这两者，且如图2所示配置于半导体基板10的纵向。上述多个晶体管部20和多个二极管部30是以排列于与半导体基板10的表面平行的一个方向的方式配置的。下面，将该一个方向称为排列方向。另外，多个晶体管部20的每一者和多个二极管部30的每一者交替地配置于该排列方向。另外，实施方式1中的第1区域11及第2区域12是在与排列方向相同的方向相邻地配置的。
多个晶体管部20和多个二极管部30各自具有条带构造。即，晶体管部20和二极管部30在俯视观察时，呈在与排列方向正交的方向上长的矩形。第1区域11处的晶体管部20的排列方向的宽度即第1晶体管宽度(D2)与第2区域12处的晶体管部20的排列方向的宽度即第2晶体管宽度(D4)不同。另外，第1区域11处的二极管部30的排列方向的宽度即第1二极管宽度(D3)与第2区域12处的二极管部30的排列方向的宽度即第2二极管宽度(D5)不同。
栅极电极40配置于半导体基板10的第2区域12处的表面。此外，在图1中省略了与栅极电极40连接的信号配线的图示。
如图2所示，表面电极50设置于多个晶体管部20及多个二极管部30的上方，即半导体基板10的表面。表面电极50与多个晶体管部20、多个二极管部30电连接。
如图1所示，外部配线60包含与表面电极50接合的接合部61。外部配线60通过接合部61与表面电极50电连接。
第1晶体管宽度(D2)及第1二极管宽度(D3)比外部配线60的接合部61的宽度(下面，称为接合宽度(D1))小。第2晶体管宽度(D4)及第2二极管宽度(D5)比外部配线60的接合部61的接合宽度(D1)大。
如图2所示，多个沟槽栅极70设置于晶体管部20及二极管部30的表面。另外，在半导体基板10的背面设置有背面电极80。实施方式1中的半导体装置是对在表面电极50和背面电极80之间流动的电流进行控制的所谓的纵向型的半导体装置。另外，晶体管部20例如为IGBT(Insulated Gate Bipolar Transistor)、MOSFET(Metal Oxide SemiconductorField Effect Transistor)等。半导体基板10例如包含SiC、GaN等宽带隙半导体作为材料。半导体装置例如为将晶体管部20及二极管部30集成于1个半导体芯片的RC-IGBT(Reverseconducting IGBT)等电力用半导体装置(功率半导体装置)。
接着，对晶体管部20开始了通电的情况下的半导体装置的动作进行说明。在开始晶体管部20的通电时，pn结部的电压达到内建电势，电子向图2所示的虚线的箭头方向转移。由于第1晶体管宽度(D2)比外部配线60的接合宽度(D1)小，因此n-漂移层90的寄生电阻R1小。因此，在第1区域11容易引起骤回动作。但是，由于第2晶体管宽度(D4)比外部配线60的接合宽度(D1)大，因此n-漂移层90的寄生电阻R2大。因此，在第2区域12实现正常的双极动作。这样，实施方式1中的半导体装置通过第2区域12，减轻了开始晶体管部20的通电时的骤回动作。其结果，对接通电压的恶化进行抑制。
另一方面，由于第1晶体管宽度(D2)比第2晶体管宽度(D4)窄，因此第1区域11处的散热特性比第2区域12好。实施方式1中的半导体装置通过第1区域11使半导体装置的散热性提高。
这里，以开始晶体管部20的通电时为例对半导体装置的动作进行了说明，但在开始二极管部30的通电时，半导体装置也与上述相同地进行动作，取得相同的效果。即，开始二极管部30的通电时的骤回动作减轻，且半导体装置的散热性提高。
综上所述，实施方式1中的半导体装置包含半导体基板10、表面电极50、外部配线60、多个晶体管部20、多个二极管部30。多个晶体管部20和多个二极管部30设置于半导体基板10，且配置于与半导体基板10的表面平行的一个方向(排列方向)。表面电极50设置于半导体基板10的表面，与多个晶体管部20、多个二极管部30电连接。外部配线60包含与表面电极50接合的接合部61，外部配线60通过接合部61与表面电极50电连接。多个晶体管部20和多个二极管部30设置于半导体基板10的俯视观察时的第1区域11和第2区域12。多个晶体管部20的每一者和多个二极管部30的每一者交替地配置于一个方向。第1区域11处的多个晶体管部20的每一者的一个方向的宽度即第1晶体管宽度和第1区域11处的多个二极管部30的每一者的一个方向的宽度即第1二极管宽度比外部配线60的接合部61的宽度小。第2区域12处的多个晶体管部20的每一者的一个方向的宽度即第2晶体管宽度和第2区域12处的多个二极管部30的每一者的一个方向的宽度即第2二极管宽度比外部配线60的接合部61的宽度大。
就这样的半导体装置而言，即使在开始晶体管部20或二极管部30的通电时，在第1区域11发生骤回动作的情况下，也能够在第2区域12实现正常的双极动作。因此，半导体装置减轻了骤回动作，其结果，对接通电压的恶化进行抑制。另外，由于第1区域11处的晶体管部20或二极管部30比第2区域12的它们密集，因此使半导体装置整体的散热性提高。
<实施方式2>
对实施方式2中的半导体装置进行说明。此外，对于与实施方式1相同的结构及动作，省略说明。
图3是表示实施方式2中的半导体装置的结构的俯视图。
外部配线60的接合部61接合至第1区域11的晶体管部20和与该晶体管部20相邻的第1区域11的二极管部30之间的边界部25之上的表面电极50。
在晶体管部20及二极管部30通电时，外部配线60的接合部61成为发热源。但是，就实施方式2中的半导体装置而言，由于外部配线60的接合部61位于散热性良好的第1区域11之上，因此半导体装置整体的散热性提高。并且，由于外部配线60的接合部61配置于边界部25之上，因此减轻了外部配线60的接合部61的热疲劳。其结果，半导体装置的长期可靠性提高。
<实施方式3>
对实施方式3中的半导体装置进行说明。此外，对于与实施方式1或2相同的结构及动作，省略说明。
图4是表示实施方式3中的半导体装置的结构的俯视图。
第1区域11设置于与连接至栅极电极40的信号配线100相反的方向。
信号配线100将在半导体基板10的外部设置的信号配线图案110和在半导体基板10的表面设置的栅极电极40电连接。这里，信号配线100在与晶体管部20及二极管部30的排列方向正交的方向延伸。
外部配线60的接合部61接合至晶体管部20和二极管部30之间的边界部25之上的表面电极50。外部配线60将表面电极50和在半导体基板10的外部设置的主电流配线图案120电连接。外部配线60从接合部61向与信号配线100所在的方向不同的方向延伸。
在半导体装置的制造过程中，需要以使得外部配线60和信号配线100彼此不干涉的方式，将外部配线60及信号配线100各自与主电流配线图案120及信号配线图案110连接。在实施方式3中，由于第1区域11设置于信号配线100的相反方向，因此在外部配线60向表面电极50接合时，外部配线60和信号配线100的干涉减轻。
就实施方式3中的半导体装置而言，在其制造工序中，能够将外部配线60稳定地连接于第1区域11。其结果，制造工序中的生产率及可靠性提高。并且，由于外部配线60的接合部61与边界部25之上的表面电极50连接，因此接合部61的热疲劳减轻。其结果，半导体装置的长期可靠性提高。
<实施方式4>
对实施方式4中的半导体装置进行说明。此外，对于与实施方式1至3中的任意者相同的结构及动作，省略说明。
图5是表示实施方式4中的半导体装置的结构的俯视图。
如上所述，晶体管部20和二极管部30在俯视观察时，呈在与该排列方向正交的方向上长的矩形。因此，第1区域11处的晶体管部20和二极管部30之间的边界部25在与该排列方向正交的方向具有长的边界线。外部配线60与第1区域11处的晶体管部20和二极管部30之间的边界平行地连接。
外部配线60包含多个接合部61，多个接合部61在该边界部25的多个位置处与表面电极50接合。换言之，外部配线60缝焊接合于边界线之上，将这样的配线称为缝焊配线。
另外，外部配线60从接合部61与边界线平行地延伸。换言之，晶体管部20和二极管部30是与外部配线60的连接方向平行地配置的。
就实施方式4中的半导体装置而言，在外部配线60的接合工序中的外部配线60与接合位置的定位时，仅准确地固定图5所示的X方向的位置即可。接合部61的Y方向的位置的波动减轻。
这样，就实施方式4中的半导体装置而言，在其制造工序中，能够将外部配线60稳定地接合于晶体管部20和二极管部30之间的边界部25之上的表面电极50。
并且，由于将外部配线60缝焊接合，因此分散了外部配线60的接合部61所产生的热量。外部配线60的接合部61的热疲劳减轻，其结果，半导体装置的长期可靠性提高。
<实施方式5>
对实施方式5中的半导体装置进行说明。此外，对于与实施方式1至4中的任意者相同的结构及动作，省略说明。
图6是表示实施方式5中的半导体装置的结构的俯视图。
在实施方式5中，第1区域11及第2区域12在与晶体管部20及二极管部30的排列方向(在图5中为X方向)正交的方向(Y方向)相邻地配置。第1区域11设置于与连接至栅极电极40的信号配线100相反的方向。
信号配线100将在半导体基板10的外部设置的信号配线图案110和在半导体基板10的表面设置的栅极电极40电连接。这里，信号配线100在晶体管部20及二极管部30的排列方向延伸。
外部配线60的接合部61接合至第1区域11的晶体管部20和二极管部30之间的边界部25之上的表面电极50。外部配线60将表面电极50和在半导体基板10的外部设置的主电流配线图案120电连接。外部配线60从接合部61向与信号配线100所在的方向不同的方向延伸。
如上所述，晶体管部20和二极管部30在俯视观察时，呈在与该排列方向正交的方向上长的矩形。因此，第1区域11处的晶体管部20和二极管部30之间的边界部25在与该排列方向正交的方向具有长的边界线。外部配线60与第1区域11处的晶体管部20和二极管部30之间的边界线平行地连接。
外部配线60包含多个接合部61，多个接合部61在该边界部25的多个位置处与表面电极50接合。换言之，外部配线60缝焊接合于边界线之上，将这样的配线称为缝焊配线。
另外，外部配线60从接合部61与边界线平行地延伸。换言之，晶体管部20和二极管部30是与外部配线60的连接方向平行地配置的。
在半导体装置的制造过程中，需要以使得外部配线60和信号配线100彼此不干涉的方式，将外部配线60及信号配线100各自与主电流配线图案120及信号配线图案110连接。在实施方式5中，由于第1区域11设置于信号配线100的相反方向，因此在外部配线60向表面电极50接合时，外部配线60和信号配线100的干涉减轻。
就实施方式5中的半导体装置而言，在其制造工序中，能够将外部配线60稳定地连接于第1区域11。其结果，制造工序中的生产率及可靠性提高。并且，由于将外部配线60缝焊接合，因此分散了外部配线60的接合部61所产生的热量。外部配线60的接合部61的热疲劳减轻，其结果，半导体装置的长期可靠性提高。
<实施方式6>
对实施方式6中的半导体装置进行说明。此外，对于与实施方式1至5中的任意者相同的结构及动作，省略说明。
图7是表示实施方式6中的半导体装置的结构的俯视图。
第1晶体管宽度(D2)比第1二极管宽度(D3)大，且第2晶体管宽度(D4)比第2二极管宽度(D5)大。
在这样的半导体装置中，晶体管部20的电流密度小。因此，半导体装置的温度上升受到抑制。
<实施方式7>
对实施方式7中的半导体装置进行说明。此外，对于与实施方式1至6中的任意者相同的结构及动作，省略说明。
实施方式7中的半导体装置具有与实施方式1至6中的任意者所示的半导体装置相同的结构。但是，第1晶体管宽度(D2)及第1二极管宽度(D3)中的小的一者的宽度的二分之一的值比半导体基板10的厚度(D6)的2倍的值大。换言之，实施方式7中的半导体装置满足D2×0.5>D6×2、或D3×0.5>D6×2的关系式。
这样的半导体装置充分地减轻了骤回动作，对接通电压的恶化进行抑制。
此外，本发明可以在其发明的范围内将各实施方式自由地组合，对各实施方式适当进行变形、省略。
虽然对本发明进行了详细说明，但上述的说明在全部的方面都只是例示，本发明并不限定于此。应当理解为，在不脱离本发明的范围的情况下，能够设想到未例示的无数的变形例。

Claims (10)

1.一种半导体装置，其具有：
半导体基板；
多个晶体管部和多个二极管部，它们设置于所述半导体基板，且配置于与所述半导体基板的表面平行的一个方向；
表面电极，其设置于所述半导体基板的所述表面，与所述多个晶体管部和所述多个二极管部电连接；以及
外部配线，其包含与所述表面电极接合的接合部，该外部配线通过所述接合部与所述表面电极电连接，
所述多个晶体管部和所述多个二极管部设置于所述半导体基板的俯视观察时的第1区域和第2区域，
所述多个晶体管部的每一者和所述多个二极管部的每一者交替地配置于所述一个方向，
所述第1区域处的所述多个晶体管部的每一者的所述一个方向的宽度即第1晶体管宽度和所述第1区域处的所述多个二极管部的每一者的所述一个方向的宽度即第1二极管宽度比所述外部配线的所述接合部的宽度小，
所述第2区域处的所述多个晶体管部的每一者的所述一个方向的宽度即第2晶体管宽度和所述第2区域处的所述多个二极管部的每一者的所述一个方向的宽度即第2二极管宽度比所述外部配线的所述接合部的所述宽度大。
2.根据权利要求1所述的半导体装置，其中，
所述外部配线的所述接合部接合至所述第1区域处的所述多个晶体管部中的一个晶体管部和所述第1区域处的所述多个二极管部中的与所述一个晶体管部相邻的一个二极管部之间的边界部之上的所述表面电极。
3.根据权利要求1或2所述的半导体装置，其中，
还具有在所述半导体基板的所述第2区域的所述表面设置的栅极电极，
所述第1区域设置于与连接于所述栅极电极的信号配线相反的方向。
4.根据权利要求2所述的半导体装置，其中，
所述多个晶体管部的每一者和所述多个二极管部的每一者是与所述外部配线的连接方向平行地配置的，
所述外部配线与所述第1区域处的所述一个晶体管部和所述一个二极管部之间的边界线平行地连接，
所述接合部连接于所述边界部。
5.根据权利要求4所述的半导体装置，其中，
还具有在所述半导体基板的所述第2区域的所述表面设置的栅极电极，
所述第1区域设置于与连接于所述栅极电极的信号配线相反的方向。
6.根据权利要求1至5中任一项所述的半导体装置，其中，
所述第1晶体管宽度比所述第1二极管宽度大，且所述第2晶体管宽度比所述第2二极管宽度大。
7.根据权利要求1至6中任一项所述的半导体装置，其中，
所述第1晶体管宽度及所述第1二极管宽度中的小的一者的宽度的二分之一的值比所述半导体基板的厚度的2倍的值大。
8.根据权利要求1或2所述的半导体装置，其中，
在所述半导体基板的所述第2区域的所述表面还具有栅极电极，
所述外部配线从所述接合部向与连接于所述栅极电极的信号配线所在的方向不同的方向延伸。
9.根据权利要求2所述的半导体装置，其中，
所述外部配线包含有在所述边界部之上的所述表面电极的多个位置处与所述表面电极接合的多个接合部，
所述多个接合部的每一者与所述接合部对应。
10.根据权利要求9所述的半导体装置，其中，
在所述半导体基板的所述第2区域的所述表面还具有栅极电极，
所述外部配线从所述多个接合部向与连接于所述栅极电极的信号配线所在的方向不同的方向延伸。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283205A (ja) * 2009-06-05 2010-12-16 Toyota Motor Corp 半導体装置
JP2011151155A (ja) * 2010-01-20 2011-08-04 Nec Corp 電界効果トランジスタ、電子装置、電界効果トランジスタの製造方法及び使用方法
JP2013138069A (ja) * 2011-12-28 2013-07-11 Denso Corp 半導体装置
JP2015065213A (ja) * 2013-09-24 2015-04-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2017201722A (ja) * 2017-08-03 2017-11-09 ルネサスエレクトロニクス株式会社 半導体装置
WO2018225571A1 (ja) * 2017-06-09 2018-12-13 富士電機株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5103830B2 (ja) * 2006-08-28 2012-12-19 三菱電機株式会社 絶縁ゲート型半導体装置
JP5045733B2 (ja) 2008-12-24 2012-10-10 株式会社デンソー 半導体装置
US8058670B2 (en) * 2009-06-04 2011-11-15 Force—MOS Technology Corporation Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up
JP2013201360A (ja) * 2012-03-26 2013-10-03 Toshiba Corp 半導体装置
US9373615B2 (en) * 2014-11-03 2016-06-21 Texas Instruments Incorporated Bipolar transistor including lateral suppression diode
JP6801324B2 (ja) * 2016-09-15 2020-12-16 富士電機株式会社 半導体装置
JP6736531B2 (ja) * 2017-09-14 2020-08-05 株式会社東芝 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283205A (ja) * 2009-06-05 2010-12-16 Toyota Motor Corp 半導体装置
JP2011151155A (ja) * 2010-01-20 2011-08-04 Nec Corp 電界効果トランジスタ、電子装置、電界効果トランジスタの製造方法及び使用方法
JP2013138069A (ja) * 2011-12-28 2013-07-11 Denso Corp 半導体装置
JP2015065213A (ja) * 2013-09-24 2015-04-09 ルネサスエレクトロニクス株式会社 半導体装置
WO2018225571A1 (ja) * 2017-06-09 2018-12-13 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2017201722A (ja) * 2017-08-03 2017-11-09 ルネサスエレクトロニクス株式会社 半導体装置

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