JP7353482B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7353482B2 JP7353482B2 JP2022524780A JP2022524780A JP7353482B2 JP 7353482 B2 JP7353482 B2 JP 7353482B2 JP 2022524780 A JP2022524780 A JP 2022524780A JP 2022524780 A JP2022524780 A JP 2022524780A JP 7353482 B2 JP7353482 B2 JP 7353482B2
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- 238000005516 engineering process Methods 0.000 description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- 230000035945 sensitivity Effects 0.000 description 3
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- 102100029442 28S ribosomal protein S22, mitochondrial Human genes 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 101000699890 Homo sapiens 28S ribosomal protein S22, mitochondrial Proteins 0.000 description 1
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
(1) チップ用接合材の下面は平面視して配線接続領域の表面形状と合致する形状を有する。
(2) センス配線は配線接続領域に接続される。
(3) 半導体チップは、センスパッド及びセンス配線の下方の領域において、スイッチング素子が機能しない無効領域を有する。
(4) センス用接続点は、チップ用接続点及び上記電極遠隔位置のうち、チップ用接続点に近い位置に設けられる接続点配置条件を満足する。
図9は基礎技術となる半導体装置の構造を示す説明図である。図9の上図が断面図であり、下図が平面図である。下図のG-G断面が上図となる。図9の上図及び下図にそれぞれXYZ直交座標系を記す。図9の下図では最上層として絶縁膜42を示している。
式(1)において、エミッタ電極抵抗成分R9の抵抗値に「R9」をそのまま用い、コレクタ電流Ic2の電流値に「Ic2」をそのまま用いている。
図1及び図2は本開示の実施の形態1である半導体装置51の構造を示す説明図である。図1の上図が断面図であり、下図が平面図であり、図2が平面図である。図1の下図のA-A断面が図1の上図となり、図2のB-B断面も図1の上図となる。図1の上図及び下図並びに図2それぞれにXYZ直交座標系を記す。
式(2)において、エミッタ電極抵抗成分R1の抵抗値に「R1」をそのまま用い、コレクタ電流Ic1の電流値に「Ic1」をそのまま用いている。
(1) チップ上接合材13の下面S13は主電流配線接続領域11の表面形状と平面視して合致する形状を有する。
(2) エミッタセンス配線10は、主電流配線接続領域11の側面に直接接続される。
(3) IGBTチップ1は、エミッタセンスパッド9及びエミッタセンス配線10の下方の領域において、IGBTが機能しない無効領域20を有する。
図4は本開示の実施の形態2である半導体装置52の構造を示す説明図である。図4の上図が断面図であり、下図が平面図である。図4の下図のC-C断面が図4の上図となり、図4の上図及び下図それぞれにXYZ直交座標系を記す。
(4) 制御ワイヤ7Bのセンス用接続点25Bは、エミッタ電極3におけるチップ用接続点23B及び電極遠隔位置のうち、チップ用接続点23Bに近い位置に設けられる接続点配置条件を満足する。
図5は本開示の実施の形態3である半導体装置53の構造を示す説明図である。図5の上図が断面図であり、下図が平面図である。図5の下図のD-D断面が図5の上図となり、図5の上図及び下図それぞれにXYZ直交座標系を記す。
図6及び図7は本開示の実施の形態4である半導体装置54の構造を示す説明図である。図6の上図が断面図であり、下図が平面図であり、図7が平面図である。図6の下図のE-E断面が図6の上図となり、図7のF-F断面も図6の上図となる。図6の上図及び下図並びに図7それぞれにXYZ直交座標系を記す。
(5) IGBTチップ1Dは、本来のIGBTと等価なスイッチング動作を行う電流検出用IGBTをさらに有し、電流検出用IGBTはIGBTチップ1Dの電流検出素子形成領域27内に設けられる。
(6) IGBTチップ1Dの電流検出素子形成領域27の表面上に、エミッタ電極3に接触することなく設けられ、電流検出用IGBTの動作時に検出電流が流れる電流検出出力パッド15をさらに備えている。
(7) 電流検出出力パッド15より得られる電流がセンス電流Isとなる。
実施の形態1~実施の形態4の半導体装置51~54では、スイッチング素子としてIGBTを用いている。スイッチング素子としてIGBTを用いることにより、以下の効果を奏する。以下、実施の形態1の半導体装置51を代表して説明する。
Claims (6)
- 内部にスイッチング素子を有する半導体チップと、
前記半導体チップの表面上に設けられ、前記スイッチング素子の動作時に主電流が流れる表面電極とを備え、前記スイッチング素子は制御電極を有し、前記表面電極の電位を基準電位とした制御電圧を前記制御電極に印加することにより前記スイッチング素子は動作制御され、
前記表面電極上に設けられる絶縁膜をさらに備え、前記絶縁膜は開口領域を有し、前記表面電極において前記開口領域内の領域が配線接続領域となり、
下面を有し、下面と前記配線接続領域の表面とが接触することにより、前記表面電極に電気的に接続されるチップ用接合材と、
前記半導体チップの表面上に前記表面電極と独立して設けられるセンスパッドと、
前記半導体チップの表面上に設けられ、前記表面電極と前記センスパッドとを電気的に接続するセンス配線とをさらに備え、
前記センスパッドの電位が前記スイッチング素子の制御用基準電位となり、
前記チップ用接合材の下面は平面視して前記配線接続領域の表面形状と合致する形状を有し、
前記センス配線は前記配線接続領域に接続され、
前記半導体チップは、前記センスパッド及び前記センス配線の下方の領域において、前記スイッチング素子が機能しない無効領域を有する、
半導体装置。 - 内部にスイッチング素子を有する半導体チップと、
前記半導体チップの表面上に設けられ、前記スイッチング素子の動作時に主電流が流れる表面電極とを備え、前記スイッチング素子は制御電極を有し、前記表面電極の電位を基準電位とした制御電圧を前記制御電極に印加することにより、前記スイッチング素子は動作制御され、
前記表面電極の表面上のチップ用接続点で接触することにより、前記表面電極と電気的に接続されるチップ用ワイヤと、
前記表面電極のセンス用接続点で接触することにより、前記表面電極と電気的に接続されるセンス用接続部材と、
前記センス用接続点の電位が前記スイッチング素子の制御用基準電位となり、前記表面電極において前記チップ用接続点を含む領域が配線接続領域として規定され、前記表面電極において前記配線接続領域から最も離れた位置が電極遠隔位置として規定され、
前記センス用接続点は、前記チップ用接続点及び前記電極遠隔位置のうち、前記チップ用接続点に近い位置に設けられる接続点配置条件を満足し、
前記センス用接続部材は
前記半導体チップの表面上に前記表面電極と独立して設けられるセンスパッドと、
前記半導体チップの表面上に設けられ、前記表面電極と前記センスパッドとを電気的に接続するセンス配線とを含み、
前記センス用接続点は、前記配線接続領域の側面に存在し、
前記センス配線は前記センス用接続点で前記表面電極と接触することにより、前記表面電極と電気的に接続され、
前記半導体チップは、前記センスパッド及び前記センス配線の下方の領域において、前記スイッチング素子が機能しない無効領域を有する、
半導体装置。 - 請求項2記載の半導体装置であって、
前記チップ用ワイヤは複数のチップ用ワイヤを含み、
前記センス用接続点は、前記複数のチップ用ワイヤのうち少なくとも一つのチップ用ワイヤとの関係において、前記接続点配置条件を満足する、
半導体装置。 - 請求項1から請求項3のうち、いずれか1項に記載の半導体装置であって、
前記半導体チップは、前記スイッチング素子と独立して設けられ、前記スイッチング素子と等価なスイッチング動作を行う電流検出素子をさらに有し、前記電流検出素子は前記半導体チップの電流検出素子形成領域内に設けられ、
前記半導体装置は、
前記半導体チップの前記電流検出素子形成領域上に、前記表面電極と独立して設けられ、前記電流検出素子の動作時に検出電流が流れる電流検出用パッドをさらに備える、
半導体装置。 - 請求項1から請求項4のうち、いずれか1項に記載の半導体装置であって、
前記スイッチング素子はIGBTである、
半導体装置。 - 請求項1から請求項5のうち、いずれか1項に記載の半導体装置であって、
前記スイッチング素子はワイドバンドギャップ半導体により構成される、
半導体装置。
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