CN111863603A - 一种低压低漏流高效保护芯片制造工艺 - Google Patents

一种低压低漏流高效保护芯片制造工艺 Download PDF

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CN111863603A
CN111863603A CN202010767349.3A CN202010767349A CN111863603A CN 111863603 A CN111863603 A CN 111863603A CN 202010767349 A CN202010767349 A CN 202010767349A CN 111863603 A CN111863603 A CN 111863603A
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崔文荣
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Jiangsu Shengchi Microelectronics Co ltd
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract

本发明公开了一种低压低漏流高效保护芯片制造工艺，涉及芯片技术领域，具体为一种低压低漏流高效保护芯片制造工艺，包括以下步骤：S1、扩散前处理；S2、氧化；S3、光刻；S4、双面开管磷沉积；S5、开管扩磷；S6、蚀刻沟槽；S7、电泳钝化；S8、完成芯片制造。该低压低漏流高效保护芯片制造工艺通过芯片表面高浓度N+层有助于提升抗浪涌能力，沟道扩散有助于降低漏电，电泳的致密性薄层提升可靠性；芯片采取台面工艺，增加N型区耗尽层结构，改变了N型扩散区的浓度结构曲线，利用N型扩散区耗尽层宽度的附加耐压，增加了P+区宽度；增宽了高导电率区域，增强了P+区对P基区发射电子的能力。

Description

一种低压低漏流高效保护芯片制造工艺
技术领域
本发明涉及芯片技术领域，具体为一种低压低漏流高效保护芯片制造工艺。
背景技术
芯片，又称微电路、微芯片或集成电路。芯片是指内含集成电路的硅片，体积很小，常常是计算机或其他电子设备的一部分。晶体管发明并大量生产之后，各式固态半导体组件如二极管、晶体管等大量使用，取代了真空管在电路中的功能与角色。到了20世纪中后期半导体制造技术进步，使得集成电路成为可能。相对于手工组装电路使用个别的分立电子组件，集成电路可以把很大数量的微晶体管集成到一个小芯片，是一个巨大的进步。集成电路的规模生产能力，可靠性，电路设计的模块化方法确保了快速采用标准化IC代替了设计使用离散晶体管。
现有的芯片在使用过程中，低压电路容易受到外部干扰，影响低压电路运行的稳定性，以及低压电路产生漏电现象，影响芯片的抗干扰的性能的缺点。
发明内容
针对现有技术的不足，本发明提供了一种低压低漏流高效保护芯片制造工艺，解决了上述背景技术中提出现有的芯片在使用过程中，低压电路容易受到外部干扰，影响低压电路运行的稳定性，以及低压电路产生漏电现象，影响芯片的抗干扰的性能的问题。
为实现以上目的，本发明通过以下技术方案予以实现：一种低压低漏流高效保护芯片制造工艺，所述包括以下步骤：
S1、扩散前处理；
S2、氧化；
S3、光刻；
S4、双面开管磷沉积；
S5、开管扩磷；
S6、蚀刻沟槽；
S7、电泳钝化；
S8、完成芯片制造。
可选的，所述步骤S1、扩散前处理中，采用P型单晶硅片，通过酸、晟驰2#清洗等工序，对硅片表面进行化学处理。
可选的，所述步骤S2、氧化中，把经过扩散前处理的硅片在1100～1200℃的氧化炉中长一层氧化层。
可选的，所述步骤S3、光刻中，把氧化后的硅片进行涂胶、曝光、显影、去氧化层等工序，双向在双面刻出一次扩散图形。
可选的，所述步骤S4、双面开管磷沉积中，采用的双面开管磷源沉积工艺，在合适的温度时，沉积250分钟左右，可得到合适的高浓度沉积层，借助后道扩磷流程，将N+深度推到本产品所需的合适深度，形成宽N+层区。
可选的，所述步骤S5、开管扩磷中，将硅片表面用100％HF腐蚀干净，再次扩磷使其形成高浓度的N+层，以及使用高温推结将基区结深推到合适的深度，使其能达到目标耐压。
可选的，所述步骤S6、蚀刻沟槽中，扩散后的硅片采用台面工艺蚀刻沟槽，露出P/N结。
可选的，所述步骤S7、电泳钝化中，采取电泳钝化保护，烧结温度650～900℃。
可选的，所述步骤S8、完成芯片制造中，后续通过光刻孔与蒸发金属及划片的方式完成芯片制造。
本发明提供了一种低压低漏流高效保护芯片制造工艺，具备以下有益效果：
P型使用沟道扩散降低漏流，使用台面降低芯片电容，使用电泳钝化提升可靠性；
表面高浓度N+层有助于提升抗浪涌能力，沟道扩散有助于降低漏电，电泳的致密性薄层提升可靠性；
芯片采取台面工艺，增加N型区耗尽层结构，改变了N型扩散区的浓度结构曲线，利用N型扩散区耗尽层宽度的附加耐压，增加了P+区宽度；增宽了高导电率区域，增强了P+区对P基区发射电子的能力。
附图说明
图1为本发明工艺流程示意图；
图2为本发明芯片结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
请参阅图1至图2，本发明提供一种技术方案：一种低压低漏流高效保护芯片制造工艺，包括以下步骤：
S1、扩散前处理；
S2、氧化；
S3、光刻；
S4、双面开管磷沉积；
S5、开管扩磷；
S6、蚀刻沟槽；
S7、电泳钝化；
S8、完成芯片制造。
步骤S1、扩散前处理中，采用P型单晶硅片，通过酸、晟驰2#清洗等工序，对硅片表面进行化学处理。
步骤S2、氧化中，把经过扩散前处理的硅片在1100～1200℃的氧化炉中长一层氧化层。
步骤S3、光刻中，把氧化后的硅片进行涂胶、曝光、显影、去氧化层等工序，双向在双面刻出一次扩散图形。
步骤S4、双面开管磷沉积中，采用的双面开管磷源沉积工艺，在合适的温度时，沉积250分钟左右，可得到合适的高浓度沉积层，借助后道扩磷流程，将N+深度推到本产品所需的合适深度，形成宽N+层区。
步骤S5、开管扩磷中，将硅片表面用100％HF腐蚀干净，再次扩磷使其形成高浓度的N+层，以及使用高温推结将基区结深推到合适的深度，使其能达到目标耐压。
步骤S6、蚀刻沟槽中，扩散后的硅片采用台面工艺蚀刻沟槽，露出P/N结。
步骤S7、电泳钝化中，采取电泳钝化保护，烧结温度650～900℃。
步骤S8、完成芯片制造中，后续通过光刻孔与蒸发金属及划片的方式完成芯片制造。
以上，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，根据本发明的技术方案及其发明构思加以等同替换或改变，都应涵盖在本发明的保护范围之内。

Claims (9)

1.一种低压低漏流高效保护芯片制造工艺，其特征在于，所述包括以下步骤：
S1、扩散前处理；
S2、氧化；
S3、光刻；
S4、双面开管磷沉积；
S5、开管扩磷；
S6、蚀刻沟槽；
S7、电泳钝化；
S8、完成芯片制造。
2.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S1、扩散前处理中，采用P型单晶硅片，通过酸、晟驰2#清洗等工序，对硅片表面进行化学处理。
3.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S2、氧化中，把经过扩散前处理的硅片在1100～1200℃的氧化炉中长一层氧化层。
4.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S3、光刻中，把氧化后的硅片进行涂胶、曝光、显影、去氧化层等工序，双向在双面刻出一次扩散图形。
5.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S4、双面开管磷沉积中，采用的双面开管磷源沉积工艺，在合适的温度时，沉积250分钟左右，可得到合适的高浓度沉积层，借助后道扩磷流程，将N+深度推到本产品所需的合适深度，形成宽N+层区。
6.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S5、开管扩磷中，将硅片表面用100％HF腐蚀干净，再次扩磷使其形成高浓度的N+层，以及使用高温推结将基区结深推到合适的深度，使其能达到目标耐压。
7.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S6、蚀刻沟槽中，扩散后的硅片采用台面工艺蚀刻沟槽，露出P/N结。
8.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S7、电泳钝化中，采取电泳钝化保护，烧结温度650～900℃。
9.根据权利要求1所述的一种低压低漏流高效保护芯片制造工艺，其特征在于：所述步骤S8、完成芯片制造中，后续通过光刻孔与蒸发金属及划片的方式完成芯片制造。
CN202010767349.3A 2020-08-03 2020-08-03 一种低压低漏流高效保护芯片制造工艺 Pending CN111863603A (zh)

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Cited By (1)

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CN115472605A (zh) * 2022-09-10 2022-12-13 江苏晟驰微电子有限公司 一种大功率低钳位保护器件的制作方法及保护器件

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CN105609549A (zh) * 2016-01-15 2016-05-25 上海瞬雷电子科技有限公司 双向放电管芯片及其制造方法

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* Cited by examiner, † Cited by third party
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US3631312A (en) * 1969-05-15 1971-12-28 Nat Semiconductor Corp High-voltage mos transistor method and apparatus
CN102543722A (zh) * 2011-12-26 2012-07-04 天津中环半导体股份有限公司 一种高电压瞬态电压抑制器芯片及生产工艺
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115472605A (zh) * 2022-09-10 2022-12-13 江苏晟驰微电子有限公司 一种大功率低钳位保护器件的制作方法及保护器件
CN115472605B (zh) * 2022-09-10 2023-11-28 江苏晟驰微电子有限公司 一种大功率低钳位保护器件的制作方法及保护器件

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Application publication date: 20201030