CN111833792A

CN111833792A - Quasi-position converter

Info

Publication number: CN111833792A
Application number: CN202010297049.3A
Authority: CN
Inventors: 杨毓群
Original assignee: Sitronix Technology Corp
Current assignee: Sitronix Technology Corp
Priority date: 2019-04-15
Filing date: 2020-04-15
Publication date: 2020-10-27
Anticipated expiration: 2040-04-15
Also published as: TW202040938A; CN111833792B; TWI779277B

Abstract

The invention relates to a level shifter, which comprises a shifting circuit and a plurality of switching circuits. The converting circuit converts a voltage level of an input signal. The switching circuits are coupled between a plurality of reference voltages and the converting circuit, and switch the reference voltages and provide the reference voltages to the converting circuit.

Description

Quasi-position converter

Technical Field

The present invention relates to a level shifter, and more particularly, to a level shifter with reduced number of high voltage difference tolerant electronic components.

Background

The level shifter (LEVEL SHIFTER) is widely used in various fields of circuits, such as a driving circuit of a display panel, and is mainly used for shifting the voltage level of a signal, so as to provide a signal with a proper voltage level, thereby enabling the circuit to operate normally. However, in the voltage level conversion process of the level converter, the internal electronic components of the level converter need to bear high voltage difference, such as transistors, so the internal electronic components of the level converter are almost high voltage difference resistant electronic components, that is, the voltage level conversion is performed by using the high voltage difference resistant electronic components with large size, which results in more consumption of instantaneous current, and because the high voltage difference resistant electronic components have large size, the related circuits of high voltage and low voltage need to be separated by using a larger circuit area during layout. In addition, the high voltage difference resistant electronic component can only be manufactured by using a high voltage resistant process, which results in a high manufacturing cost

In view of the above problems, the present invention provides a level shifter, which can be applied to various circuits requiring voltage level shifting of input signals, and can reduce the number of devices using high voltage differential tolerant circuits to reduce the circuit size, thereby achieving the reduction of circuit area and cost, and solving the above problems.

Disclosure of Invention

The present invention provides a level shifter, which uses a plurality of reference voltages with different voltage levels to shift the voltage level of an input signal, thereby reducing the number of high-dropout-resistance electronic components and achieving the reduction of circuit area and cost.

Drawings

FIG. 1: it is a circuit diagram of a level shifter according to a first embodiment of the present invention;

FIG. 2: it is a circuit diagram of a level shifter according to a second embodiment of the present invention;

FIG. 3: it is a circuit diagram of an embodiment of the level shifter of the present invention for controlling a buffer circuit; and

FIG. 4: it is a circuit diagram of an embodiment of the level shifter of the present invention applied to a display device.

[ brief description of the drawings ]

10 level converter

20 input circuit

21 enable circuit

22 switching circuit

30 first switching circuit

31 second switching circuit

32 first switching circuit

33 second switching circuit

40 display panel

41 source driving circuit

42 gate drive circuit

43 controller

A1-A8 Source line

B1-B6 gate lines

CLK clock signal

DATA

EN enable signal

G1-G6 gate signals

M11-M18 transistor

M21-M28 transistor

M31-M32 transistor

O output terminal

OL inverting output terminal

S input signal

S1-S8 Source signals

Sub-Pixel

VDDK first reference level

VDDL first reference level

VDDM third reference level

VDDN third reference level

Second reference level of VSSK

VSSL second reference level

Fourth reference level of VSSM

VSSN fourth reference level

XEN enable signal

XO (oxygen oxide) inverting output end

XOL inverting output terminal

XS input signal

Detailed Description

In order to provide a further understanding and appreciation for the structural features and advantages achieved by the present invention, the following detailed description of the presently preferred embodiments is provided:

although certain terms are used herein to refer to particular components, those skilled in the art will appreciate that various names are possible for manufacturers to refer to the same components, and that the description and the claims are not intended to distinguish one component from another, but are to be construed broadly, in a manner that distinguishes and distinguishes between the components as a whole. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is intended to include any direct or indirect connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and other connections.

Please refer to fig. 1, which is a circuit diagram of a level shifter according to a first embodiment of the present invention. As shown, the level shifter 10 includes a plurality of

switching circuits

30 and 31, and the

switching circuits

30 and 31 are coupled to a plurality of reference voltages. The reference voltages include a first reference voltage and a second reference voltage. The level shifter 10 includes a converting circuit 22, and the converting circuit 22 converts a voltage level of an input signal S/XS. The switching

circuits

30, 31 are coupled between the reference voltages and the converting circuit 22, so that the switching

circuits

30, 31 can switch the reference voltages and provide one of the reference voltages to the converting circuit 22. Furthermore, the level shifter 10 includes an input circuit 20. The input circuit 20 receives an input signal S/XS, wherein the input signal XS and the input signal S are mutually inverse signals. The level shifter 10 can shift the voltage level of the input signal S/XS received by the input circuit 20 to different voltage levels, wherein the level shifter 10 can be applied to various circuits that need to shift the voltage level of the input signal S/XS, such as a source driver circuit or a gate driver circuit for driving a display panel, and thus the input signal S/XS may be a voltage signal or a data signal.

In connection with the above, the converting circuit 22 is coupled to the input circuit 20 and is coupled to the first reference voltage or the second reference voltage through the switching

circuits

30 and 31, in the embodiment, the first reference voltage includes a first reference level VDDL and a second reference level VSSL, and the second reference voltage includes a third reference level VDDM and a fourth reference level VSSM. Moreover, the level difference between the first reference level VDDL and the second reference level VSSL may be equal to or close to the level difference between the third reference level VDDM and the fourth reference level VSSM. For example, the level of the first reference level VDDL is 6V and the level of the second reference level VSSL is 0V, and the level difference between the two levels is 6V, i.e., the first reference voltage may be 6V. The level of the third reference level VDDM is 15V and the level of the fourth reference level VSSM is 9V, and the level difference between the third reference level VDDM and the fourth reference level VSSM is 6V, i.e., the second reference voltage may be 6V, but the level of the second reference voltage is different from the level of the first reference voltage. In addition, the levels of the first reference level VDDL, the second reference level VSSL, the third reference level VDDM, the fourth reference level VSSM, the first reference voltage and the second reference voltage are for illustration only, and the first reference voltage and the second reference voltage may be supplied by the same or different power circuits, for example, two power circuits independent from each other, or one power circuit provides different reference levels, so the above-mentioned examples are not intended to limit the embodiments of the present invention.

Referring to fig. 1 again, the first switch circuit 30 is coupled to the first reference level VDDL and the third reference level VDDM, the second switch circuit 31 is coupled to the second reference level VSSL and the fourth reference level VSSM, and the

switch circuits

30 and 31 switch the first reference level VDDL, the second reference level VSSL, the third reference level VDDM and the fourth reference level VSSM and provide the first reference level VDDL and the second reference level VSSL to the switch circuit 22, or provide the third reference level VDDM and the fourth reference level VSSM to the switch circuit 22, that is, the

switch circuits

30 and 31 provide the first reference voltage or the second reference voltage to the switch circuit 22. Therefore, during the period when the converting circuit 22 is coupled to the first reference voltage, for example, during the period when the converting circuit 22 is coupled to 6V (the first reference level VDDL) and 0V (the second reference level VSSL), the converting circuit 22 converts the voltage level of the input signal S/XS to a first voltage level, i.e., the first reference level VDDL or the second reference level VSSL, for example, 6V or 0V, according to the level of the first reference voltage. During the period when the converting circuit 22 is coupled to the second reference voltage, for example, during the period when the converting circuit 22 is coupled to 15V (third reference level VDDM) and 9V (fourth reference level VSSM), the converting circuit 22 converts the voltage level of the input signal S/XS from the first voltage level (6V/0V) to a second voltage level (15V/9V) according to the level of the second reference voltage, i.e., from the first reference level VDDL to the third reference level VDDM, or from the second reference level VSSL to the fourth reference level VSSM. In other words, the level shifter 10 shifts the voltage level of the input signal S/XS to the first voltage level according to the first reference voltage, and shifts the voltage level of the input signal S/XS from the first voltage level to the second voltage level according to the second reference voltage. Thus, the converting circuit 22 of the level shifter 10 can output the input signal S and the input signal XS with the second voltage level at an output terminal O and an inverted output terminal XO.

In the embodiment, when the level of the input signal S is a high level (1) and the level of the input signal XS is a low level (0), the output terminal O outputs the input signal S with the second voltage level being the third reference level VDDM, and the inverting output terminal XO outputs the input signal XS with the second voltage level being the fourth reference level VSSM. When the level of the input signal S is the low level (0) and the level of the input signal XS is the high level (1), the output terminal O outputs the input signal S with the second voltage level being the fourth reference level VSSM, and the inverted output terminal XO outputs the input signal XS with the second voltage level being the third reference level VDDM.

The first switching circuit 30 and the second switching circuit 31 are coupled to the switching circuit 22, the first reference voltage and the second reference voltage, and the switching circuit 22 is coupled to the first reference voltage or the second reference voltage through the first switching circuit 30 and the second switching circuit 31. Therefore, the first switching circuit 30 and the second switching circuit 31 switch the first reference voltage coupling converting circuit 22, the voltage level of the input signal S/XS can be converted to the first voltage level, the first switching circuit 30 and the second switching circuit 31 switch the second reference voltage coupling converting circuit 22, and the voltage level of the input signal S/XS can be converted from the first voltage level to the second voltage level. One of the embodiments of the first switching circuit 30 and the second switching circuit 31 may respectively include a plurality of switches, and the on-state switching circuit 22 is coupled to the path of the first reference voltage or the second reference voltage, and the off-state switching circuit 22 is coupled to the path of the first reference voltage or the second reference voltage.

Furthermore, the level shifter 10 may include an enable circuit 21, which receives an enable signal EN, so that the level shifter 10 has the function of latching the voltage level of the level-shifted input signal S/XS at the output terminal O and the output terminal XO. The enabling circuit 21 is coupled between the converting circuit 22 and the input circuit 20, and controls the converting circuit 22 to latch the levels of the output terminal O and the inverting output terminal XO. That is, the enabling circuit 21 controls the converting circuit 22 to latch the second voltage level converted by the level of the output terminal O and the inverted output terminal XO, that is, latch the third reference level VDDM (15V) or the fourth reference level VSSM (9V) of the output terminal O and the inverted output terminal XO, wherein each reference level may be other levels corresponding to different circuit requirements besides the above-mentioned values.

For example, when the first switching circuit 30 and the second switching circuit 31 switch the first reference level VDDL and the second reference level VSSL to be coupled to the converting circuit 22, that is, when the converting circuit 22 is coupled to the first reference voltage, if the level of the enable signal EN is high (1), the level of the input signal S is high, and the level of the input signal XS is low (0), a gate of a transistor M11 of the input circuit 20 is controlled by the input signal S and the transistor M11 is in an on state, a gate of a transistor M17 of the input circuit 20 is controlled by the input signal XS and the transistor M17 is in an off state, and gates of a transistor M12 and a transistor M18 of the enable circuit 21 are both controlled by the enable signal EN and the transistors M12 and M18 are in an on state. The sources of the transistors M11 and M17 are coupled to a second reference level VSSL, which may be, but not limited to, ground. The transistors M12 and M18 have sources respectively coupled to drains of the transistors M11 and M17, and the transistors M11, M12, M17, and M18 may be NMOS transistors. Thus, the level of the inverted output XO coupled to a drain of the transistor M12 of the enabling circuit 21 is at the level of the second reference level VSSL. Furthermore, a gate of a transistor M16 and a gate of a transistor M15 of the conversion circuit 22 are coupled to the inverted output XO, and the transistor M16 may be a PMOS transistor and the transistor M15 may be an NMOS transistor.

Therefore, when the level of the inverted output XO is the level of the second reference level VSSL, the transistor M16 is turned on, and the transistor M15 is turned off. Thus, the first switching circuit 30 coupled to a source of the transistor M16 provides the first reference level VDDL, which is raised by the voltage level at the output terminal O of the drain charge converting circuit 22 of the transistor M16. In other words, the voltage level of the input signal S is converted to the level of the first reference level VDDL by the conversion circuit 22. The output terminal O may be the drain of the transistor M16, a drain of the transistor M15 and a drain of the transistor M18 are coupled to the drain of the transistor M16, a source of the transistor M15 is coupled to the second switching circuit 31, and a source of the transistor M15 is coupled to the second reference level VSSL via the second switching circuit 31. In addition, the drain of the transistor M18 is also coupled to the output terminal O. The first reference level VDDL is higher than the second reference level VSSL, the third reference level VDDM is higher than the fourth reference level VSSM, the third reference level VDDM is higher than the first reference level VDDL, and the fourth reference level VSSM is higher than the second reference level VSSL.

A gate of a transistor M14 and a gate of a transistor M13 of the conversion circuit 22 are coupled to the output terminal O, a source and a drain of the transistor M14 are coupled to the first switching circuit 30 and the inverted output terminal XO, respectively, and the transistor 14 may be a PMOS transistor, a source and a drain of the transistor M13 are coupled to the second switching circuit 31 and the inverted output terminal XO, respectively, and the transistor M13 may be an NMOS transistor. Therefore, when the level of the output terminal O is the level of the first reference level VDDL, the transistor M14 is in the off state, and the transistor M13 is in the on state. Thus, the first reference level VDDL coupled to the source of the transistor M14 through the first switching circuit 30 does not charge the inverting output XO of the switching circuit 22, and the transistor M13 is turned on to keep the inverting output XO at the level of the second reference level VSSL through the second switching circuit 31. The drain of the transistor M13, the drain of the transistor M14, and the drain of the transistor M12 are coupled to each other to form an inverting output XO.

Therefore, when the first switching circuit 30 and the second switching circuit 31 switch the first reference level VDDL (6V) and the second reference level VSSL (0V) to be coupled to the converting circuit 22, the voltage difference to be borne by the four transistors M13, M14, M15, M16 of the converting circuit 22 and the transistor M18 on the right side thereof is the level difference between the first reference level VDDL and the second reference level VSSL, for example, 6V, or is smaller than the level difference between the first reference level VDDL and the second reference level VSSL. Furthermore, the input signal S with the first voltage level is to be raised to a higher level, and before the level of the input signal S is changed to a low level, the level of the enable signal EN is changed to a low level (0), and the first switching circuit 30 and the second switching circuit 31 switch the third reference level VDDM (15V) and the fourth reference level VSSM (9V) to be coupled to the converting circuit 22, that is, the converting circuit 22 is coupled to the second reference voltage, so that the voltage level of the input signal S at the output terminal O can be raised from the first voltage level (6V) to the second voltage level (15V), and the voltage level of the input signal XS at the inverted output terminal XO can be raised from the first voltage level (0V) to the second voltage level (9V). Moreover, the voltage difference to be borne by the four transistors M13, M14, M15, M16 of the converting circuit 22 is the level difference between the third reference level VDDM and the fourth reference level VSSM, for example, 6V, or is smaller than the level difference between the third reference level VDDM and the fourth reference level VSSM. However, the transistors M12 and M18 are subject to high voltage difference.

In other words, when the level shifter 10 is to raise the voltage level of the input signal S to the second voltage level, although the voltage level of the second reference voltage is higher than the voltage level of the first reference voltage, the converting circuit 22 can maintain the voltage across the transistors M13, M14, M15, M16 of the converting circuit 22 to be the same, for example, 6V, or to be within a predetermined range, for example, the range of voltage withstanding capability of the middle and low voltage difference electronic components, regardless of whether the converting circuit 22 is coupled to the first reference voltage or the second reference voltage. Thus, the electronic components of the conversion circuit 22 do not need to be high voltage difference resistant electronic components, i.e., electronic components manufactured by a high voltage difference resistant process, so that the size of the electronic components is small, the number of the high voltage difference resistant electronic components is reduced, and the circuit area and the cost are reduced. As can be seen from the embodiment shown in fig. 1, the level shifter 10 converts the voltage levels of the input signal S/XS by using a plurality of reference voltages, so that the level shift circuit 22 does not need to use electronic components resistant to high voltage difference, and thus the level shifter 10 of the present invention can greatly reduce the number of electronic components resistant to high voltage difference.

Referring to fig. 1, when the level of the input signal S is low (0), the level of the input signal XS is high (1), and the level of the enable signal EN is also high (1), the transistor M11 of the input circuit 20 is in an off state, and the transistor M17 of the input circuit 20 is in an on state. The transistor M12 and the transistor M18 of the enabling circuit 21 are in a conducting state, and the level of the output terminal O of the converting circuit 22 is the level of the second reference level VSSL. Moreover, the transistor M14 is in the on state, the transistor M13 is in the off state, so that the level of the inverting output terminal XO is the level of the first reference level VDDL, when the switching

circuits

30 and 31 switch the third reference level VDDM and the fourth reference level VSSM, and the level of the enable signal EN is converted to the low level (0), the third reference level VDDM charges the inverting output terminal XO of the converting circuit 22, the level of the inverting output terminal XO rises from the first reference level VDDL to the level of the third reference level VDDM, and the level of the output terminal O of the converting circuit 22 rises from the second reference level VSSL to the level of the fourth reference level VSSM. In addition, in an embodiment of the present invention, when the level of the input signal S received by the input circuit 20 is changed from the high level (1) to the low level (0) and the level of the input signal XS is changed from the low level (0) to the high level (1), since the level of the inverted output terminal XO has not risen to the capability of turning off the transistor M16, the discharging capability (the capability of pulling down the level) of the transistor M17 on the output terminal O is higher than the charging capability (the capability of raising the level) of the third reference level VDDM on the output terminal O through the transistor M16, so that the charging capability of the third reference level VDDM on the output terminal O through the transistor M16 is limited by adjusting the third reference level VDDM, and the high-low level of the output terminal O is changed. Similarly, when the level of the input signal S received by the input circuit 20 changes from the low level (0) to the high level (1) and the level of the input signal XS changes from the high level (1) to the low level (0), the ability of the third reference level VDDM to charge the inverting output terminal XO through the transistor M14 is limited to facilitate the transition of the high and low voltage levels of the inverting output terminal XO.

Please refer to fig. 2, which is a circuit diagram of a level shifter according to a second embodiment of the present invention. As shown, the input circuit 20 and the enabling circuit 21 of the level shifter 10 can be implemented by replacing the NMOS transistors M11, M17, M12, M18 of fig. 1 with the PMOS transistors M21, M27, M22, M28, and the connection relationship is not changed, while the transistors M13, M14, M15, M16 of the implementation transforming circuit 22 of fig. 1 are the same type as the transistors M24, M23, M26, M25 of fig. 2, and the connection relationship is not changed. The enable circuit 21 shown in fig. 2 is coupled to the enable signal XEN, and the enable signal XEN and the enable signal EN are mutually inverse signals. Furthermore, the embodiment of fig. 1 is used for converting positive voltage levels, the embodiment of fig. 2 is used for converting negative voltage levels, and the converting circuit 22 of fig. 2 is coupled to the first reference voltage and the second reference voltage through the first switching circuit 32 and the second switching circuit 33. The first reference voltage and the second reference voltage of this embodiment can be negative voltages and respectively include a first reference level VDDKK, a second reference level VSSK, a third reference level VDDN, and a fourth reference level VSSN, such as 0V, -6V, and-9V-15V. Furthermore, the sources of the transistors M21 and M27 of the input circuit 20 in the embodiment of fig. 2 are coupled to the first reference level VDDK, the output terminal of the level shifter 10 is labeled OL, the inverted output terminal is labeled XOL, and the levels of the output terminal OL and the inverted output terminal XOL may be the second voltage level after the level shifting of the shifting circuit 22, that is, the third reference level VDDN or the fourth reference level VSSN. The remaining techniques are similar to the description of fig. 1 and will not be repeated. In addition, the first reference level VDDK and the second reference level VSSK may be replaced by the first reference level VDDL and the second reference level VSSL in the first embodiment, so that the first reference level VDDK, the second reference level VSSK, the third reference level VDDN and the fourth reference level VSSN may be designed according to the usage requirement.

Please refer to fig. 3, which is a circuit diagram illustrating an embodiment of a level shifter according to the present invention controlling a buffer circuit. As shown, the buffer circuit includes a transistor M32 and a transistor M31, a source of the transistor M32 is coupled to the first switching circuit 30, a gate of the transistor M32 is coupled to the output O of the level shifter 10 in the embodiment of fig. 1, a source of the transistor M31 is coupled to the second switching circuit 33, a gate of the transistor M31 is coupled to the output OL of the level shifter 10 in the embodiment of fig. 2, and a drain of the transistor M32 is coupled to a drain of the transistor M31 as the output. Moreover, the buffer circuit shown in fig. 3 can be used as a driver for driving a gate driving circuit of a display device to output gate signals (e.g., fig. 4G1, G2, G3, G4, G5, G6) to a display panel. The buffer circuit is coupled to the first reference level VDDL or the third reference level VDDM through the first switch circuit 30, and the buffer circuit is coupled to the second reference level VSSK and the fourth reference level VSSN through the second switch circuit 33. Furthermore, the first switching circuit 30 shown in fig. 1 and 3 is switched synchronously, so that the first switching circuit 30 shown in fig. 1 switches the first reference level VDDL or the third reference level VDDM to couple to the level shifter 10 shown in fig. 1, so that when the level of the output terminal O of the level shifter 10 shown in fig. 1 is the first voltage level (the first reference level VDDL) or the second voltage level (the third reference level VDDM), the first switching circuit 30 shown in fig. 3 is also switched, so that the source of the transistor M32 is also the first voltage level (the first reference level VDDL) or the second voltage level (the third reference level VDDM), and thus the transistor M32 does not need to bear a higher voltage difference, i.e., the transistor M32 does not need to be a high voltage difference-tolerant electronic component, and the size and the circuit area of the electronic component can be reduced.

In view of the above, the second switching circuit 33 in fig. 2 and fig. 3 is switched synchronously, so that the second switching circuit 33 in fig. 2 switches the second reference level VSSK or the fourth reference potential VSSN to couple to the level shifter 10 in fig. 2, so that when the level of the output end OL of the level shifter 10 in fig. 2 is the first voltage level (the second reference level VSSK) or the second voltage level (the third reference level VSSN), the second switching circuit 33 in fig. 3 also switches, so that the source of the transistor M31 is also the first voltage level (the second reference level VSSK) or the second voltage level (the fourth reference level VSSN), and thus the transistor M31 does not need to bear a high voltage difference, i.e., the transistor M31 does not need to be a high voltage tolerant differential electronic component, and the number of high voltage tolerant differential electronic components can be reduced. In addition, the switching circuits shown in fig. 1, 2 and 3 may be different independent switching circuits, that is, the switching circuit shown in fig. 2 is changed to a third switching circuit and a fourth switching circuit, and the switching circuit shown in fig. 3 is changed to a fifth switching circuit and a sixth switching circuit, but the switching manner is also such that the electronic device does not need to bear a higher voltage difference, and the electronic device is maintained to bear a lower voltage difference.

Please refer to fig. 4, which is a circuit diagram of an embodiment of a level shifter according to the present invention applied to a display device. As shown, the display device includes a display panel 40, a source driving circuit 41, a gate driving circuit 42 and a controller 43. The display panel 40 includes a plurality of Sub-pixels, a plurality of source lines a1, a2, A3, a4, a5, a6, a7, A8, and a plurality of gate lines B1, B2, B3, B4, B5, B6. The areas surrounded by the source lines A1-A8 and the gate lines B1-B6 include the Sub-pixels. The source signals S1 to S8 outputted from the source driving circuit 41 are transmitted to the Sub-pixels via the source lines a1 to a8, and the gate signals G1, G2, G3, G4, G5, and G6 outputted from the gate driving circuit 42 are transmitted to the Sub-pixels via the gate lines B1 to B6. The Sub-pixels display images according to the source signals S1 to S8 under the control of the gate signals G1 to G6. Furthermore, in the embodiment, the gate driving circuit 42 may include the level shifter 10 shown in fig. 1 and fig. 2, however, during the driving of the display panel 40, the levels of the gate signals G1-G6 are scan levels or disable levels, and the gate lines B1, B2, B3, B4, B5, and B6 are scanned, so when the voltage levels of the gate signals G1-G6 are changed, the gate driving circuit 42 may cooperate with the level shifter 10 to drive the buffer shown in fig. 3 to output the gate signals G1-G6 with the scan levels or the disable levels, the scan levels may be positive voltages, and the disable levels may be negative voltages. In other words, the level shifter 10 of the present invention can be applied to various circuits requiring the voltage level of the signal to be shifted.

Referring back to fig. 4, the controller 43 generates a clock signal CLK and a DATA to the source driving circuit 41, wherein the DATA may be provided by the controller 43 or not provided by the controller 43, which is an optional design. In addition, the controller 43 also outputs the clock signal CLK to the gate driving circuit 42 to control the operation timings of the source driving circuit 41 and the gate driving circuit 42. .

In summary, the present invention relates to a level shifter, which includes a shifting circuit and a plurality of switching circuits. The converting circuit converts a voltage level of an input signal. The switching circuits are coupled between a plurality of reference voltages and the converting circuit, switch the reference voltages and provide the reference voltages to the converting circuit so as to convert the voltage level of the input signal.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.

Claims

1. A level shifter, comprising:

a conversion circuit for converting the voltage level of an input signal; and

and the switching circuits are coupled between a plurality of reference voltages and the conversion circuit, switch the reference voltages and provide the reference voltages to the conversion circuit.

2. The level shifter of claim 1, wherein the reference voltages comprise a first reference voltage and a second reference voltage, the switching circuits provide the first reference voltage or the second reference voltage to the shifting circuit, and the shifting circuit shifts the voltage level of the input signal from the first voltage level to a second voltage level according to the first reference voltage and the second reference voltage.

3. The level shifter of claim 1, wherein the reference voltages comprise a first reference voltage and a second reference voltage, the first reference voltage comprises a first reference level and a second reference level, the second reference voltage comprises a third reference level and a fourth reference level, the switching circuits are coupled to the first reference level, the second reference level, the third reference level and the fourth reference level, the switching circuits switch the first reference level, the second reference level, the third reference level and the fourth reference level and provide the first reference level and the second reference level to the shifting circuit or provide the third reference level and the fourth reference level to the shifting circuit.

4. The level shifter of claim 1, wherein the reference voltages include a first reference voltage and a second reference voltage, the first reference voltage includes a first reference level and a second reference level, the second reference voltage includes a third reference level and a fourth reference level, and a level difference between the first reference level and the second reference level is equal to a level difference between the third reference level and the fourth reference level.

5. The level shifter of claim 1, wherein the switching circuits comprise a first switching circuit and a second switching circuit, the reference voltages comprise a first reference voltage and a second reference voltage, the first switching circuit and the second switching circuit switch the first reference voltage to be coupled to the shifting circuit, the voltage level of the input signal is shifted to a first voltage level, the first switching circuit and the second switching circuit switch the second reference voltage to be coupled to the shifting circuit, and the voltage level of the input signal is shifted from the first voltage level to a second voltage level.

6. The level shifter of claim 1, wherein the plurality of reference voltages comprises a first reference voltage and a second reference voltage, the second reference voltage having a voltage level higher than that of the first reference voltage, the shifter circuit is coupled to the first reference voltage or the second reference voltage through the plurality of switching circuits and maintains a voltage step-over of the shifter circuit within a predetermined range.

7. The level shifter of claim 1, comprising:

an input circuit for receiving the input signal; and

an enable circuit, coupled between the input circuit and the converting circuit, for controlling the converting circuit to latch the converted voltage level of the input signal.