TWI462083B - Level shifter devices and methods and source driver for liquid crystal display - Google Patents

Description

Quasi-displacement device and method and data driver of liquid crystal display

The present invention relates to a quasi-positioner and a data driver for a liquid crystal display.

Traditionally, data drivers can only be used alone to generate AC common voltage or DC common voltage. When the data driver is used to generate the AC common voltage, there are two power supplies with different voltages in the data driver. When the data driver is used to generate a DC common voltage, there are two power supplies with the same voltage transformation in the data driver. Generally, there are two different types of quasi-displacers used in the data driver to generate the AC common voltage and two quasi-displacers of the same type to generate a DC common voltage in the data driver.

Figure 1A shows a circuit diagram of a conventional data driver for generating an alternating current common voltage of a liquid crystal display. Among the data drivers 100, there are a 5V power supply VDDA and a -5V power supply VDDAN. There is also a first quasi-positioner 110 and a second quasi-positioner 120 in the data drive 100. The first quasi-positioner 110 offsets a voltage between 0 and 1.8V to a voltage between 0 and 5V. The second quasi-positioner 120 moves the voltage between 0 and 1.8V to a voltage between 0 and -5V.

Figure 1B shows a circuit diagram of a conventional data driver for generating a DC common voltage of a liquid crystal display. Among the data drivers 101, there are a 5V power supply VDDA and a 5V power supply VSSAN. There is also a first quasi-positioner 130 and a second quasi-positioner 140 in the data drive 101. The first quasi-positioner 130 offsets a voltage between 0 and 1.8V to a voltage between 0 and 5V. The second quasi-positioner 140 moves the voltage between 0 and 1.8V to a voltage between 0 and 5V.

In general, a shifter for shifting a signal between 0 and 1.8 volts to a signal between 0 and 5 volts cannot be used to offset a signal between 0 and 1.8 volts to 0. Signal with -5 volts. Currently, based on the hardware architecture, the data drivers used to generate the AC common voltage and the data drivers used to generate the DC common voltage are not compatible due to the quasi-displacer.

Therefore, it is necessary to provide a data driver that can be used to offset a voltage range to two voltage ranges.

The present disclosure provides a quasi-displacement device for a data driver of a liquid crystal display, comprising: an input stage for generating a signal according to an input logic, the signal having a positive input supply voltage and a negative input supply voltage a voltage between the first stage, according to the signal to generate a first logic signal and a second logic signal; an output stage, according to the first logic signal and the second logic signal generated at a first output end a first output signal or a second output signal at a second output end, the first output signal having a voltage between a first positive output supply voltage and a first negative output supply voltage, The second output signal has a voltage between a second positive output supply voltage and a second negative output supply voltage.

The present disclosure further provides a data driver for a liquid crystal display device, comprising: a quasi-positioner for generating a first output signal or a second output according to an input logic, a first reference source and a second reference source a signal; a digital analog converter for generating a first analog signal or a second analog signal according to the first output signal or the second output signal and the first reference source and the second reference source; a wave device configured to limit the voltage level of the first output signal or the second output signal according to the first reference source and the second reference source; wherein when the first reference source is a positive voltage and the second reference source is Zero time, the first output signal is generated, and when the first reference source is zero and the second reference source is a negative voltage, the second output signal is generated.

The disclosure further provides a method for shifting a signal level, comprising: generating, by an input stage, a signal according to an input logic, the signal having a voltage between a positive input power supply voltage and a negative input power supply voltage; Generating a first logic signal and a second logic signal according to the signal by an intermediate stage; and generating a first output signal at the first output end according to the first logic signal and the second logic signal by an output stage And generating a second output signal at a second output end, the first output signal having a voltage between a first positive output power voltage and a first negative output power voltage, the second output signal having A voltage between a second positive output supply voltage and a second negative output supply voltage.

The quasi-displacer of the data driver of the above liquid crystal display and the method thereof can shift one signal of a voltage range into two signals having respective voltage ranges. Therefore, a data driver having the above quasi-displacer can be used to generate an AC common voltage and a DC common voltage.

The above described objects, features and advantages of the present invention will become more apparent from the following description of the preferred embodiments of the invention. Circuit diagram of the quasi-displacer. The quasi-displacer 200 includes an input stage 210, an intermediate stage 220, an output stage 230, a first switch 240 and a second switch 250.

Input stage 210 is operative to generate a signal between positive input supply voltage VDDD and negative input supply voltage VDDDN based on input logic (IN and INB). The intermediate stage 220 is configured to generate a first logic signal and a second logic signal based on the signal. The output stage 230 is configured to generate a first output signal between the first positive output power voltage and the first negative output power voltage at the first output terminal OUT1 according to the first logic signal and the second logic signal, and in the second Output terminal OUT2 produces a second output signal between the second positive output supply voltage and the second negative output supply voltage. When the first output signal is generated, the first switch 240 is turned on, and when the second output signal is generated, the second switch 250 is turned on.

The intermediate stage 220 further includes a first upper level circuit 260 and a first lower level circuit 270. The first upper level circuit 260 and the first lower level circuit 270 have two buffers connected in series. The buffer may be a non-inverting device, but is not limited thereto. The output stage 230 further includes a second upper level circuit 280 and a second lower level circuit 290. The first output terminal OUT1 of the second upper level circuit 280 is connected to the first switch 240, and the second output terminal OUT2 of the second lower level circuit 290 is connected to the second switch 250.

The second upper level circuit 280 further includes a first p-type transistor 281, a second p-type transistor 282, a first n-type transistor 283, a second n-type transistor 284, a third n-type transistor 285 and a Four n-type transistors 286. The second lower level circuit 290 includes a third p-type transistor 291, a fourth p-type transistor 292, a fifth p-type transistor 293, a sixth p-type transistor 294, a fifth n-type transistor 295 and a sixth N-type transistor.

The first p-type transistor 281 and the second p-type transistor 282 are coupled to the first voltage source VSSAN. The first n-type transistor 283 is coupled to the first p-type transistor 281, and the second n-type transistor 284 is coupled to the second p-type transistor 282. The gate of the first p-type transistor 281 is connected to the gate of the first n-type transistor 283 and the gate of the second p-type transistor 282 is connected to the gate of the second n-type transistor 284. The third n-type transistor 285 is coupled to the first n-type transistor 283 and the second voltage source VDDAN. The fourth n-type transistor 286 is coupled to the second n-type transistor 284 and the second voltage source VDDAN. The gate of the third n-type transistor 285 and the drain of the second p-type transistor 282 are connected to the first output terminal OUT1.

The fifth n-type transistor 295 and the sixth n-type transistor 296 are coupled to the third voltage source VDDA. The fifth p-type transistor 293 is coupled to the fifth n-type transistor 295 and the sixth p-type transistor 294 is coupled to the sixth n-type transistor 296. The gate of the fifth n-type transistor 295 is connected to the gate of the fifth p-type transistor 293. The gate of the sixth n-type transistor 296 is connected to the gate of the sixth p-type transistor 294. The third p-type transistor 291 is coupled to the fifth p-type transistor 293 and the fourth voltage source VSSA. The fourth p-type transistor 292 is coupled to the sixth p-type transistor 294 and the fourth voltage source VSSA. The gate of the third p-type transistor 291 and the drain of the sixth p-type transistor 294 are connected to the second output terminal OUT2.

Fig. 3 is a schematic view showing an embodiment of the shifter of Fig. 2. In an embodiment, among input stages 210, the positive input supply voltage VDDD is 1.8 volts and the negative input supply voltage VDDDN is the negative of the positive input supply voltage VDDD, ie -1.8 volts. The output voltage of input stage 210 is between 1.8 volts and -1.8 volts. In the intermediate stage 220, the first upper level circuit 260 outputs a logic signal having a voltage between 0 and -1.8 volts, and the first lower level circuit 270 outputs a logic signal having a voltage between 0 and 1.8 volts. Among the output stages 230, the first voltage source VSSAN and the fourth voltage source VSSA are grounded, that is, 0 volts. The second voltage source VDDAN and the third voltage source VDDA are -5 volts. In this manner, the second lower level circuit 290 will output a zero voltage signal at the second output terminal OUT2 and the second switch 250 will not be conductively corresponding. At the same time, the second upper level circuit 280 will output a signal having a voltage between 0 and -5 volts at the first output terminal OUT1 and the first switch 240 is turned on correspondingly. Therefore, the potential across the second switch 250 is limited to 5 volts.

Fig. 4 is a schematic view showing another embodiment of the shifter of Fig. 2. In an embodiment, in input stage 210, the positive input supply voltage VDDD is 1.8 volts and the negative input supply voltage VDDDN is the negative of the positive input supply voltage VDDD, ie -1.8 volts. The output voltage of input stage 210 will be between 1.8 and -1.8 volts. In the intermediate stage 220, the first upper level circuit 260 outputs a logic signal having a voltage of 0 volts, and the first lower level circuit 270 outputs a logic signal having a voltage between 0 and 1.8 volts. In the output stage 230, the first voltage source VSSAN, the second voltage source VDDAN and the third voltage source VDDA are grounded, that is, 0 volts. The fourth voltage source VSSA is 5 volts. In this manner, the second upper level circuit 280 will output a zero voltage signal at the first output terminal OUT1 to turn off the first switch 240. At the same time, the second lower level circuit 290 will output a signal having a voltage between 0 and 5 volts at the second output terminal OUT2 to turn on the second switch 250. Therefore, the potential across the first switch 240 will be limited to less than 5 volts.

Fig. 5 is a view showing an embodiment of a data drive of the inventive liquid crystal display. The data driver 500 includes a quasi-bit shifter 510, a digital analog converter 520, and a clipping device 530.

The quasi-bit shifter 510 is configured to generate a first output signal or a second output signal according to the input logic, the first reference source VSSAN and the second reference source VDDAN, as described above. In one embodiment, when the input voltage is 1.8 volts, its logic level is a high level, and when the input voltage is zero volts, its logic level is a low level. The first reference source VSSAN is zero volts and the second reference source VDDAN is -5 volts and produces a first output signal when the data driver 500 is operative to generate an alternating current common voltage. The first reference source VSSAN is zero volts and the second reference source VDDAN is 5 volts and produces a second output signal when the data driver 500 is operative to generate a DC common voltage. The first output signal is a negative voltage signal and the second output signal is a positive voltage signal.

The digital analog converter 520 is configured to generate a first analog signal or a second analog signal according to the first output signal or the second output signal, and the first reference source VSSAN and the second reference source VDDAN. The chopper device 530 is configured to limit the voltage level of the first output signal or the second output signal according to the first reference source VSSAN and the second reference source VDDAN.

Figure 6 is a flow chart showing the method of shifting the signal by the shifter of the data driver of the liquid crystal display of the invention. At step 610, the quasi-displacer generates a signal between the positive input supply voltage and the negative input supply voltage based on the input logic by the input stage.

Next, in step 620, the quasi-bit shifter generates a first logic signal and a second logic signal according to the signal by the intermediate stage. The first logic signal is generated by the first upper level circuit, and the voltage of the first logic signal is between the negative input power supply voltage and zero volts. The second logic signal is generated by the first lower level circuit, and the voltage of the second logic signal is between zero and the positive input power source voltage.

Finally, the quasi-displacer generates a first output signal at the first output end by the output stage according to the first logic signal and the second logic signal, and the voltage level is between the first positive output power supply voltage and the first negative output A second output signal is generated between the supply voltages or at the second output terminal, the voltage level being between the second positive output supply voltage and the second negative output supply voltage.

The first output signal is generated according to the first logic signal by the second upper level circuit, and the second output signal is generated according to the second logic circuit by the second lower level circuit.

In the end, it is obvious to those skilled in the art that they can easily use the disclosed concept and the specific embodiments to change and design other structures that can perform the same purpose without departing from the invention and the scope of the claims.

100. . . Data driver

110. . . First quasi-positioner

120. . . Second quasi-positioner

101. . . Data driver

130. . . First quasi-positioner

140. . . Second quasi-positioner

200. . . Quasi-displacer

210. . . Input stage

220. . . Intermediate level

230. . . Output stage

240. . . First switch

250. . . Second switch

260. . . First upper level circuit

270. . . First lower level circuit

280. . . Second upper level circuit

290. . . Second lower level circuit

281. . . First p-type transistor

282. . . Second p-type transistor

283. . . First n-type transistor

284. . . Second n-type transistor

285. . . Third n-type transistor

286. . . Fourth n-type transistor

291. . . Third p-type transistor

292. . . Fourth p-type transistor

293. . . Fifth p-type transistor

294. . . Sixth p-type transistor

295. . . Fifth n-type transistor

296. . . Sixth n-type transistor

500. . . Data driver

510. . . Quasi-displacer

520. . . Digital analog converter

530. . . Chopping device

610-630. . . Step method

Figure 1A is a circuit diagram showing a conventional data driver for generating an alternating current common voltage of a liquid crystal display;

Figure 1B is a circuit diagram showing a conventional data driver for generating a DC common voltage of a liquid crystal display;

Figure 2 is a circuit diagram showing a quasi-displacer of a data driver of the inventive liquid crystal display;

Figure 3 is a schematic view showing an embodiment of the shifter of Figure 2;

Figure 4 is a schematic view showing another embodiment of the shifter of Figure 2;

Figure 5 is a diagram showing an embodiment of a data drive of the inventive liquid crystal display;

Figure 6 is a flow chart showing the method of shifting the signal by the shifter of the data driver of the liquid crystal display of the invention.

200. . . Quasi-displacer

210. . . Input stage

220. . . Intermediate level

230. . . Output stage

240. . . First switch

250. . . Second switch

260. . . First upper level circuit

270. . . First lower level circuit

280. . . Second upper level circuit

290. . . Second lower level circuit

281. . . First p-type transistor

282. . . Second p-type transistor

283. . . First n-type transistor

284. . . Second n-type transistor

285. . . Third n-type transistor

286. . . Fourth n-type transistor

291. . . Third p-type transistor

292. . . Fourth p-type transistor

293. . . Fifth p-type transistor

294. . . Sixth p-type transistor

295. . . Fifth n-type transistor

296. . . Sixth n-type transistor

Claims (12)

A quasi-displacement device for a data driver of a liquid crystal display, comprising: an input stage for generating a signal according to an input logic, the signal having a voltage between a positive input supply voltage and a negative input supply voltage An intermediate stage, according to the signal, generating a first logic signal, a first inverted logic signal, a second logic signal, and a second inverted logic signal; and an output stage receiving the first logic signal, the The first inverted logic signal, the second logic signal, and the second inverted logic signal generate a first output signal at a first output terminal by using the received first logic signal and the first inverted logic signal Or generating a second output signal by using the received second logic signal and the second inverted logic signal at a second output end, the first output signal having a first positive output power voltage and a first A voltage between the negative output supply voltages, the second output signal having a voltage between a second positive output supply voltage and a second negative output supply voltage. The quasi-displacer according to claim 1, further comprising: a first switch connected to the first output end point; and a second switch connected to the second output end point; wherein when the generating The first switch is turned on when the first output signal is present, and the second switch is turned on when the second output signal is generated. For example, the quasi-positioner described in claim 1 of the patent scope, wherein the middle The inter-stage further includes: a first upper level circuit for generating the first logic signal and the first inverted logic signal, the first logic signal and the first inverted logic signal having the negative input power a voltage between the voltage and zero; and a first lower level circuit for generating the second logic signal and the first inverted logic signal, the second logic signal and the first inverted logic signal having a A voltage between zero and the positive input supply voltage. The quasi-displacer of claim 3, wherein the first upper level circuit and the first lower level circuit each comprise two buffers connected in series. The quasi-displacer of claim 1, wherein the output stage further comprises: a second upper level circuit for generating the first signal according to the first logic signal and the first inverted logic signal An output signal; and a second lower level circuit for generating the second output signal according to the second logic signal and the second inverted logic signal. The quasi-displacement device of claim 5, wherein the second upper level circuit further comprises: a first p-type transistor and a second p-type transistor coupled to a first voltage source a first n-type transistor coupled to the first p-type transistor, and a second n-type transistor coupled to the second p-type transistor, wherein the first p-type transistor has a gate connection a gate of the first n-type transistor, and a gate of the second p-type transistor is connected to a gate of the second n-type transistor; a third n-type transistor coupled to the first n-type Transistor and a second a voltage source; and a fourth n-type transistor coupled to the second n-type transistor and the second voltage source; wherein the gate of the third n-type transistor and the drain of the second p-type transistor Connect to the first output endpoint. The quasi-displacement device of claim 5, wherein the second lower level circuit further comprises: a fifth n-type transistor and a sixth n-type transistor coupled to a third voltage source a fifth p-type transistor coupled to the fifth n-type transistor, and a sixth p-type transistor coupled to the sixth n-type transistor, wherein the fifth n-type transistor has a gate connection a gate of the fifth p-type transistor, and a gate of the sixth n-type transistor is connected to a gate of the sixth p-type transistor; a third p-type transistor coupled to the fifth p-type a transistor and a fourth voltage source; and a fourth p-type transistor coupled to the sixth p-type transistor and the fourth voltage source; wherein the gate of the third p-type transistor and the sixth p The drain of the transistor is connected to the second output terminal. A data driver for a liquid crystal display device, comprising: a quasi-positioner according to claim 1 for generating a first output signal according to an input logic, a first reference source and a second reference source or a second output signal; a digital analog converter for generating a first according to the first output signal or the second output signal and the first reference source and the second reference source An analog signal or a second analog signal; and a chopping device for limiting the voltage level of the first output signal or the second output signal according to the first reference source and the second reference source; wherein The first output signal is generated when a reference source is a positive voltage and the second reference source is zero, and the second output signal is generated when the first reference source is zero and the second reference source is a negative voltage. The data driver of the liquid crystal display device of claim 8, wherein the first output signal is a negative voltage signal and the second output signal is a positive voltage signal. A method for shifting a signal level includes: generating, by an input stage, a signal having a voltage between a positive input power supply voltage and a negative input power supply voltage according to an input logic; Generating a first logic signal, a first inverted logic signal, a second logic signal, and a second inverted logic signal by an intermediate stage; receiving the first logic signal, the first inverted logic signal, a second logic signal and the second inverted logic signal; and utilizing the received first logic signal and the first inverted logic signal to generate a first output signal at a first output terminal by an output stage, And generating, by the second logic signal and the second inverted logic signal, a second output signal at a second output end, the first output signal having a first positive output power voltage and a first A voltage between a negative output supply voltage, the second output signal having a voltage between a second positive output supply voltage and a second negative output supply voltage. The method of shifting a signal level according to claim 10, wherein the generating the first logic signal and the second logic signal comprises: generating the first logic signal by a first upper level circuit and The first inverted logic signal, the first logic signal and the first inverted logic signal have a voltage between the negative input supply voltage and zero; and the first lower level circuit generates the first The second logic signal and the second inverted logic signal, the second logic signal and the second inverted logic signal having a voltage between zero and the positive input supply voltage. The method for shifting a signal level according to claim 10, wherein the generating the first output signal and the second output signal comprises: borrowing according to the first logic signal and the first inverted logic signal The first output signal is generated by a second upper level circuit; and the second output signal is generated by a second lower level circuit according to the second logic signal and the second inverted logic signal.